• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a subscriber matching device for matching a plurality of DS1E-class subscribers to a switching unit in an ATM switch. The apparatus of the present invention comprises: a line matching unit 41 for matching a plurality of DS1E lines; extracting valid ATM cells contained in a multiframe of a line matching unit, and mapping ATM cells input from a switching side to the multiframe. Cell extraction and mapping section 42; A header converter 43 for allocating a new VPI / CVI for use in the system from the VPI / VCI of the receiving cell; A multiplexer (44) for multiplexing the header-transformed multiple links of cells; A cell bus matching unit 47 for delivering the subscriber cells to the switching side via the cell bus; A cell bus controller 46 which generates a cell bus control signal for transmitting and receiving a cell with the switching side via the cell bus; A demultiplexer 45 which analyzes a port identifier header of a transmitting cell input through the cell bus and transmits the transmitting cell to a corresponding port; An IPC message storage unit 48 for storing IPC messages transmitted and received to the cell bus side; And a main processor unit 49 for controlling the operation of each block connected through a local bus and transmitting and receiving an IPC message to the IPC message storage unit to communicate with main processors of other boards. Connect to
    公开号:KR19980061776A
    申请号:KR1019960081153
    申请日:1996-12-31
    公开日:1998-10-07
    发明作者:홍성한
    申请人:유기범；대우통신 주식회사；
    IPC主号:
    专利说明:

    DS1E-class subscriber matching device of ATM switch
    The present invention relates to a subscriber matching device for matching subscribers to a switching unit in an ATM switch, and more particularly, to a subscriber matching device for matching a plurality of DS1E-class subscribers.
    In general, an ATM switch is a system that performs a node function to connect an ATM network, an ATM network, or a subscriber to an ATM network in the case of a public network based on an ATM method. (VP) is divided into exchanges.
    The ATM switching system is implemented with a subscriber matching device, a switch network, a relay line matching device, and the like and processors for controlling them.
    The subscriber matching device performs UPC traffic control functions along with UNI physical layer matching, ATM layer processing, IPC cell and user cell separation delivery, header conversion, and OAM processing. In addition, the subscriber matching device may include a low and low speed subscriber matching function for the existing subscriber service as well as ATM subscriber.
    ATM switch networks are realized by multiple stages of unit switches capable of high-speed switching of hundreds of Mbits. ATM unit switches are divided into input buffers, output buffers, common memories, common buses, cross point switches, and the like according to the configuration.
    ATM trunk line matching device performs NNI interface physical layer processing, ATM layer processing, OAM processing, and the traffic control function works in conjunction with switch network. It also includes interworking with other networks such as existing telephone network, N-ISDN, packet network, frame relay network, etc.
    On the other hand, the ATM switch is a large-capacity ATM switch for performing the function as a core node of the B-ISDN according to its capacity, and a local information communication network (MAN) to support ATM communication locally required in the process of B-ISDN. (Metropolitan Area Network) can be divided into a small amount of ATM switch used in the construction. In other words, ATM-MSS can be directly interworked with broadband ISDN and ATM-based MAN Switching System to accommodate the services that broadband ISDN can provide. )to be.
    Such a small ATM switch needs to connect various subscribers. To this end, a remote switching node (RSN) for connecting subscribers, a hub switching node (HSN) for connecting a plurality of remote switching nodes, and a system are managed. It is a switch of a distributed exchange structure composed of a network management system (MSS-EMS).
    However, a subscriber matching device is required to provide an ATM service to a subscriber through the existing DS1E-class link in such a small ATM switch.
    Accordingly, an object of the present invention is to provide a subscriber matching device for matching a plurality of DS1E-class subscribers to a switching node in a small capacity ATM switch.
    In order to achieve the above object, the apparatus of the present invention includes a line matching unit for matching a plurality of DS1E lines; A cell extracting and mapping unit for extracting valid ATM cells loaded in the multiframe of the line matching unit and mapping the ATM cells input from the switching side to the multiframe; A header converter for allocating a new VPI / CVI for use in the system from the VPI / VCI of the receiving cell; A multiplexer which multiplexes the header-transformed multiple links of cells; A cell bus matching unit for delivering subscriber cells to the switching side via cell buses; A cell bus controller which generates a cell bus control signal to transmit and receive a cell with a switching side through the cell bus; A demultiplexer for analyzing a port identifier header of a transmitting cell input through cell bus and transmitting the transmitting cell to a corresponding port; An IPC message storage unit for storing IPC messages transmitted and received to the cell bus side; And a main processor unit controlling the operation of each block connected through a local bus and transmitting and receiving an IPC message to the IPC message storage unit in order to communicate with main processors of another board.
    1 is a block diagram showing the overall structure of an ATM switch to which the present invention is applied;
    FIG. 2 is a detailed block diagram of the remote switching node RSN shown in FIG. 1;
    3 is a detailed block diagram of the hub switching node (HSN) shown in FIG.
    4 is an overall block diagram of a DS1E subscriber matching device according to the present invention;
    5 is a detailed block diagram of a subscriber matching device shown in FIG. 4;
    6 is a diagram illustrating a reception direction cell format;
    7 is a diagram illustrating a transmission direction cell format.
    * Explanation of symbols for main parts of the drawings
    41: line matching unit 42: cell extraction and mapping unit
    43: header conversion unit 44: multiplexer
    45: demultiplexer 46: cell bus controller
    47: cell bus matching unit 48: IPC message storage unit
    49: main processor unit
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    1 is a block diagram showing the structure of an ATM switch to which the present invention is applied, FIG. 2 is a detailed block diagram of a remote switching node (RSN) shown in FIG. 1, and FIG. 3 is a hub switching node shown in FIG. Detailed block diagram of (HSN).
    As shown in FIG. 1, the small-capacity ATM switch 1 to which the present invention is applied has a plurality of Remote Switching Nodes (RSNs) 10-1 to 10-5 for accommodating DS1E or DS3 level subscribers. And a hub switching node (HSN) 20 for connecting a plurality of remote switching nodes (RSNs) and a network management system (EMS) 30 for managing a system. At this time, another ATM switch 2 is connected to the hub switching node (HSN) 20 to configure a B-ISDN network.
    As shown in FIG. 2, the remote switching node RSN includes a subscriber matching module (SIM) 110, a cell switching module (CSM) 120, a remote switching node control module (RNCM) 130, and a node access module (NIM). The subscriber matching module (SIM: 110) includes a subscriber matching board (SAD3: 111) for matching DS3 level subscribers and a subscriber matching board (SAE1: 113) for matching DS1 level subscribers. And a subscriber registration board (FRIA: 114) for matching frame relays, a first multiplexing / demultiplexing board (D3MA: 112) for multiplexing and demultiplexing cells of a DS3 class subscriber, and multiplexing and demultiplexing a cell of a DS1 class subscriber. A second multiplexing / demultiplexing board (D1MA) 115 is provided for multiplexing.
    The cell switching module (CSM) 120 is composed of a plurality of cell switching boards (CSA), the node connection module (NIM) 140 is composed of a plurality of node connection boards (NIA), and a remote switching node control module (RNCM: 130 is composed of a hard disk drive (HDD: 132), a remote node management board (RNMA: 134).
    Referring to Figure 2, the node management board (RNMA: 134) performs the agent function of performance management, failure management, configuration management, security management, billing management function specified in the TMN, node management of the hub switching node (HSN) It establishes an ATM connection with the board (HNMA) and communicates with the network management system (EMS) connected to the node management board (HNMA) of the hub switching node (HSN) via Ethernet.
    The cell switching board (CSA) 120 receives a cell from each board in a node and transfers the cell to a corresponding destination board based on a routing field of a header. The cell switching board (CSA) 120 typically has 8x8 ports and each port exchanges a cell of up to 155Mbps. Have the ability. To support point-to-multipoint connections, cell copying can be performed as indicated in the cell header, and buffers are provided to prevent temporary congestion.
    The node connection module (NIM: 140) is composed of a plurality of node connection boards (NIA: 142,144), and serves to connect the hub switching node (HSN) and the remote switching node (RSN), and the node connection board (NIA) It connects hub switching node (HSN) and remote switching node (RSN) through one STM-1 link, and provides physical layer and physical layer management function, ATM layer and ATM layer management function, traffic management function, protection switching function, etc. Perform.
    Here, the physical layer function performs the function of terminating and generating the 155.52 Mbps line signal, terminating and generating the STM-1 frame, cell matching, and the physical layer management function extracts the performance coefficient of the physical layer, and the node management board It consists of a performance management function that reports to the RNMA and a failure management function that detects and recovers from failures in the physical layer, records the occurrence and release of it, and makes an emergency report.
    ATM layer functions include cell multiplexing and demultiplexing, cell generation and termination, discarding unassigned and invalid cells, and cell header conversion. ATM layer management functions are instructed by the Node Management Board (RNMA: 134). Performance monitoring, connectivity check, loopback, etc. are performed for the connection, and the result is reported or an alarm cell is generated and transmitted for the failure condition of a specific connection. The traffic management function extracts and reports the traffic parameters of the link.
    Subscriber matching module (SIM) 110 connects DS1E and DS3-class subscribers. Frame relay access board (FRIA) is connected to frame relay switch to send and receive frame relay packet, and circuit emulation access board (CIE) is the circuit of DS1E. Perform emulation function.
    In addition, the subscriber matching board (SAE1: 113) is connected to the DS1E multiplexing board (D1MA: 115) through four DS1E links. Cells received from each DS1E link are transmitted to the DS1E multiplexing board, and cells received from the DS1E multiplexing board are demultiplexed and transmitted to the corresponding link (port) based on the routing field of the header.
    The subscriber matching board (SAE1: 113) performs physical layer, physical layer management function, ATM layer and ATM layer management function, traffic management function, protection switching function, etc., and the physical layer function terminates and generates 2.048Mbps line signal. , CRC multiframe termination and generation, and cell matching. The physical layer management function consists of a performance management function that extracts the performance coefficient of the physical layer, reports it to the RNMA, and detects and recovers from a failure state of the physical layer, records the occurrence and release of the physical layer, and makes an emergency report.
    ATM layer functions include cell multiplexing and demultiplexing, cell generation and termination, discarding unallocated and invalid cells, and cell header translation. ATM layer management function performs the performance monitoring, connectivity check, loopback, etc. for the connection indicated by the node management board (RNMA), and reports the result or forms an alarm cell for the failure of a specific connection. Do this. The traffic management function extracts and reports the traffic parameters of the link.
    The DS1E Multiplexing Board (D1MA: 115) receives 16 DS1E signals and maps them into one STM-1 signal. The DS3 Multiplexing Board (D3MA) receives three DS3 signals and receives one STM-1. Performs the function of mapping to a grade signal.
    The DS3 subscriber matching board (SAD3: 111) transmits the cell received through the DS3 link to the DS3 multiplexing board 112 through the three DS3 links, and the cell received from the DS3 multiplexing board 113 is based on the routing field of the header. Demultiplex and transmit to the link.
    DS3 subscriber matching board (SAD3: 111) performs physical layer and physical layer management function, ATM layer and ATM layer management function, and traffic management function. The physical layer function is used to terminate and generate 44.736Mbps line signal and terminate PLCP frame. And perform functions such as generation and cell matching.
    Frame relay matching board (FRIA: 114) is in charge of interworking function between existing frame relay communication network and ATM switch. The connection speed with frame relay network is 4 2.048Mbps.
    Frame Relay Matching Board (FRIA: 114) has physical layer and physical layer management function, ATM layer and ATM layer management function, traffic management function, AAL and AAL management function. Perform configuration, error checking, line coding and line interface functions.
    The AAL function is an AAL type 5 function that performs transparent transmission, error detection and processing of CPCS-SDUs, transmission of congestion information and loss priority information, extraction and generation of frame relay frames, congestion control, and protocol mapping. The AAL management function manages and reports on the AAL's performance functions, maintains status information, FR matching functions, management functions for PVC services, and connection management functions.
    In addition, as shown in FIG. 3, the hub switching node (HSN) 20 includes a node connection module (NIM: 210), a cell switching module (CSM: 220), an exchanger connection module (EIM: 230), and a hub switching node control module. (HNCM: 240), the node connection module (NIM: 210) is composed of a plurality of node connection boards (NIA: 211, 212, 213), the cell switching module (CSM: 220) is composed of a cell switching board (CSA) The exchanger connection module (EIM) 230 is composed of the exchanger connection boards (EIA) 231 and 232. The hub switching node control module (HNCM: 240) is composed of an HDD 241, a hub switching matching board (HNMA: 242), a test board (TSA: 243), a clock distribution board (CDA: 244), and the like. The system (EMS: 30) is connected to the node management board (HNMA: 242) by Ethernet.
    Referring to Figure 3, the network management board (HNMA: 242) performs the agent of the performance management, failure management, configuration management, security management, billing management functions specified in the TMN, node management board of the remote switching node (RSN) (RNMA: 134) and the network management system (EMS: 30).
    The clock distribution board (CDA) 244 provides clocks and network synchronizer clocks necessary for each board, and the HDD 241 stores various information such as management information model, module-specific operation program, and statistical data in the node.
    The cell switching module (CSM) 220 receives a cell from each board in the node and delivers the cell to the corresponding board based on the routing field of the header, and has 16 x 16 ports, each of which has a cell switching capability of up to 155 Mbps. .
    The node connection module (NIM: 210) is composed of a set of node-to-node connection boards (NIA: 211, 212, 213). The node connection board (NIA) connects RSNs and HSNs through one STM-1 link. It handles layer management function, ATM layer and ATM layer management function, traffic management function and protection switching function.
    The physical layer function performs functions such as termination and generation of 155.52 Mbps line signal, termination and generation of STM-1 frame, cell matching, and physical layer management function is composed of performance management function and fault management function.
    ATM layer functions include cell multiplexing and demultiplexing, cell generation and termination, discarding unallocated and invalid cells, and cell header conversion. The ATM layer management function performs performance monitoring, connectivity check, loopback, etc. on the connection indicated by the network node management board (HNMA), reports the result, or generates and transmits an alarm cell for a specific connection failure condition. .
    The exchanger connection module (EIM: 230) consists of a set of access boards (EIA: 231,232) between other exchange nodes, and the exchanger connection board (EIA: 231,232) connects to other exchanges through one STM-1 link to the ATM exchanger. It is the function to connect the other exchange. The exchange access board (EIA) has a physical layer and a physical layer management function, an ATM layer and an ATM layer management function, a traffic management function, and a protection switching function.
    4 is a block diagram of the subscriber matching device according to the present invention, FIG. 5 is a detailed block diagram of the subscriber matching device shown in FIG. 4, and FIG. 6 is a view showing a receiving cell format in the subscriber matching device. 7 is a diagram illustrating a transmission cell format in a subscriber matching device.
    As shown in FIG. 4, the subscriber matching device according to the present invention extracts a line matching unit 41 for matching a plurality of DS1E lines, cells extracted in a frame of the line matching unit 41, and ATM cells. Cell extracting and mapping unit 42 for mapping a frame to a frame, a header converting unit 43 for allocating a new VPI / CVI for use in a system from a VPI / VCI of a receiving cell, and a multiplexing unit 44 for multiplexing header converted cells. ), A cell bus matching unit 47 for transmitting subscriber cells to the multiplexing unit through cell buses, a cell bus controller 46 for generating cell bus control signals to transmit and receive cells through cell buses, and input through cell buses A demultiplexer 45 for analyzing the port identifier header of the transmitted cell and transmitting the cell to the corresponding port, a main processor 49 for controlling the operation of each block connected through a local bus, and a main processor different from each other. Communicate with the main processors on the board It consists of IPC message storage portion 48 for storing the IPC message for group.
    Referring to FIG. 4, the subscriber matching device SAE1 extracts an ATM cell from four DS1E (2.048 Mbps) line signals according to an embodiment of the present invention, and multiplexes four ports to deliver them to the multiplexing board (D1MA). It performs the demultiplexing function by analyzing the port identifier header 1 byte of the ATM cell received from the multiplexing board (D1MA) and delivering the cell to the corresponding port.
    At this time, the process of multiplexing four-port cells uses a first-in, first-out buffer (FIFO) having a size of four cells in the physical layer protocol processor (PLPP). In particular, the subscriber matching device (SAE1) accommodates four ports, thereby multiplexing ATM. The cells output from each port are first converted into the only VPI / VCI in the system so that the cells can be identified.
    When the multiplexed 54-byte cell is stored in the RxFIFO, the Cellbus Control informs the cell multiplexing / demultiplexing (D1MA) board that the CAV * signal is asserted and there is a cell to transmit. In response, the cellbus controller of the multiplexing / demultiplexing board (D1MA) asserts an ENB * signal and simultaneously reads a 54-byte cell in 16-bit units.
    Cell reception from the multiplexing / demultiplexing device (D1MA) is a reverse process of transmission. When the multiplexing / demultiplexing board (D1MA) transmits a cell having a size of 54 bytes with the SEL * signal, the subscriber matching device (SAE1) receives the first message. Demultiplexing is accomplished by analyzing the first byte (ie, the byte with the port identifier) to identify the port and then forwarding the 53-byte cell to that port. Transmission and reception of an IPC cell, which is a system message, is performed through an IPC message storage unit (implemented by DPRAM).
    In FIG. 4, the line matching unit 41 extracts or maps an ATM cell in a PLCP multiframe structure in order to connect with a DS1E-class line signal. At this time, the line signal is a B8ZS line signal, and is composed of a line transceiver E1XC for restoring the DS1E multiframe structure.
    The cell insertion and extraction unit 42 is implemented as a physical layer protocol processor (PLPP) to extract ATM cells from DS1E multiframes or to map ATM cells to multiframes. To perform.
    The header converting unit 43 converts the header of the cell extracted by each cell inserting and extracting unit 42 into a new VPI / VCI to be used in the system, which can use the same VPI / VCI value for each port. It provides the ability to assign unique VPI / VCI values in the system for this purpose. The header conversion unit 43 is implemented using an address translation controller (ATC), which is a commercial device, and has a RAM to store a lookup table and parameter values in the ATC device to convert an input cell into a cell having a required value. And then print it out. However, since the ATC device does not support the UTOPA interface, it is necessary to control the cell flow by buffering the cell input / output terminals.
    The cell bus matching unit 47 transmits the multiplexed ATM cells from the subscriber matching board SAE1 to the multiplexing / demultiplexing board D1MA and receives the cells from the multiplexing station / multiplexing board D1MA. It has a data width of 16 bits.
    In addition, in order to transmit and receive cells through the cell bus matching unit 47, the cell bus controller 46 first converts an 8-bit cell stream into 16 bits and then outputs a cell to a multiplex / demultiplex (D1MA) board. When the signal is asserted, the cell bus controller of the multiplexing (D1MA) board reads a cell by transmitting a CLK signal together with the ENB * signal. In the transmission direction, when the multiplexing board (D1MA) transfers a 54-byte cell tagged with 1-byte port information to the SEL * signal to the CellBus matching unit 47, it is converted to 8-bit. It parses the port identification byte and forwards the ATM cell to that port.
    The IPC message matching unit 48 transmits and receives various IPC messages used for system control. The IPC message matching unit 48 is configured as a dual port RAM (DPRAM) to transfer data to a multiplexing / demultiplexing (D1MA) board. If a specific address is accessed after accessing the data, the interrupt is generated and the data is notified to the multiplexing / demultiplexing board (D1MA), and the reception of the multiplexing / demultiplexing board (D1MA) is performed by the multiplexing / demultiplexing board (D1MA). By taking the same operation as the board SAE1.
    The main processor unit 49 is implemented with an external 33 MHz and an internal 66 MHz using the MC68040, a 32-bit processor, and uses 512K bytes of EPROM for initialization and program storage, and 1M bytes of SRAM for data storage. Implement At this time, the processor unit performs functions such as initializing the subscriber registration board SAE1, controlling each functional unit, and analyzing the IPC cell.
    Subsequently, referring to the detailed block of the subscriber matching apparatus according to the present invention, as shown in FIG. 5, the line matching unit 41 is implemented with four line transmitters E1XC, and the cell extraction and mapping unit 42 is four. It is implemented with three physical layer protocol processors (PLPP), the header conversion unit 43 is implemented with four ATC and four buffers. The cell bus matching unit 47 includes a receiving FIFO and a transmitting FIFO, and the demultiplexer 45 converts a 16-bit wide cell into an 8-bit wide cell under the control of the cell bus controller. Implemented as a buffer.
    In the receiving direction after the system initialization, the unallocated and invalid cells are removed from the PLPP multiframe structure of the DS1E signal input through the arbitrary line transmitter (E1XC) and valid ATM cells are extracted. The extracted ATM cell is transferred to the header conversion unit to read the input cell's VPI / VCI, and is converted to the system VPI / VCI.
    Subsequently, one byte is added to the end of the 53-byte cell, and the 54-byte cell is stored in the receiving FIFO of the cell matching unit with a width of 16 bits, and an RXENB * signal indicating the existence of a valid cell to the multiplexing / demultiplexing board (D1MA) is obtained. Assert to allow multiplexing / demultiplexing board (DMA) to read one cell.
    The transmission direction is the reverse process. It checks the tag which is the first byte among the 54 byte cells having the 16 bit width transmitted from the multiplexing / demultiplexing board (D1MA), identifies the corresponding port, and converts the cell to 8 bit width. When the cell is delivered to the PLPP, the PLPP maps the cell to the PLPP multiframe structure and transmits the DS1E signal through the E1XC.
    At this time, the format of the ATM cell in the reception direction and the transmission direction is as shown in Figs. 54 bytes of data in which a tag (TAG) including a port identifier for identifying a port is added to the first byte is added.
    As described above, the subscriber matching device according to the present invention has the effect of connecting DS1E-class subscribers to the ATM network by matching four DS1E-class links and transmitting them to the Salswitching side.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] A line matching unit 41 for matching a plurality of DS1E lines;
    A cell extracting and mapping unit (42) for extracting valid ATM cells loaded in the multiframe of the line matching unit and mapping the ATM cells input from the switching side to the multiframe;
    A header converter 43 for allocating a new VPI / CVI for use in the system from the VPI / VCI of the receiving cell;
    A multiplexer (44) for multiplexing the header-transformed multiple links of cells;
    A cell bus matching unit 47 for delivering the subscriber cells to the switching side via the cell bus;
    A cell bus controller 46 which generates a cell bus control signal for transmitting and receiving a cell with the switching side via the cell bus;
    A demultiplexer 45 which analyzes a port identifier header of a transmitting cell input through the cell bus and transmits the transmitting cell to a corresponding port;
    An IPC message storage unit 48 for storing IPC messages transmitted and received to the cell bus side; And
    DS1E class subscriber registration device of the ATM exchanger is provided with a main processor (49) for controlling the operation of each block connected via a local bus and communicates with the main processors of the other board to the IPC message storage unit.
    [2" claim-type="Currently amended] 2. The system according to claim 1, wherein the cell bus matching unit 47 receives a first-in first-out (FIFO) buffer for transmitting the receiving cell to the switching side via the cell bus, and a transmission for receiving the transmitting cell from the switching side through the cell bus. DS1E-class subscriber matching device of an ATM switch, characterized in that the first-in, first-out (FIFO) buffer.
    [3" claim-type="Currently amended] The DS1E-class subscriber matching apparatus of claim 1, wherein the IPC message storing unit (48) is implemented as a dual port RAM (DPRAM).
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    同族专利:
    公开号 | 公开日
    KR100221300B1|1999-09-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-31|Application filed by 유기범, 대우통신 주식회사
    1996-12-31|Priority to KR1019960081153A
    1998-10-07|Publication of KR19980061776A
    1999-09-15|Application granted
    1999-09-15|Publication of KR100221300B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960081153A|KR100221300B1|1996-12-31|1996-12-31|Ds1e subscriber interface apparatus for atm switch|
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