• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In particular, the error correction of data for DVD is performed. In particular, an error polynomial unit for calculating a syndrome from an input data word and calculating coefficients of the error position polynomial and coefficients of the error evaluation polynomial using the syndrome, and coefficients of the error position polynomial; And an error position and error value calculation unit for calculating an error position and an error value using coefficients of an error evaluation polynomial, a counter for counting the number of errors from the detected error position, and the counted error number for correcting an internal code. A comparison unit that compares with or exceeds the GFS signal generator that generates a GFS signal when no sector synchronization is detected or the position thereof is incorrect, or an oar gate that generates an erase flag when the number of errors exceeds the correction capability or a GFS signal is generated. GFS, even if the number of errors in PI error correction does not exceed the correction capability When a signal is generated, an erase flag is forcibly generated for the frame, thereby preventing PO error correction during PO error correction, thereby increasing the PO error correction capability.
    公开号:KR19980059945A
    申请号:KR1019960079292
    申请日:1996-12-31
    公开日:1998-10-07
    发明作者:김진욱
    申请人:구자홍；엘지전자 주식회사；
    IPC主号:
    专利说明:

    Error correction device and method
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to error correction of data for a digital video disc (DVD). In particular, an error flag is forcibly generated when there is a high probability of an error after performing error correction in a horizontal direction. The present invention relates to an error correction apparatus and method for increasing vertical error correction capability.
    Recently, a system has been developed for recording and reproducing moving images from a high density optical disc or an optical disc after compressing an image using a high efficiency coding technique, and one of them is a DVD system.
    The DVD system employs a variable bit rate coding technique in which a code amount generated in response to complex image information is changed, and a system similar to MPEG 2 (Moving Picture Experts Group 2) for ensuring a high quality image.
    The error correction technique employed in such a DVD system is a product code consisting of an inner code and an outer code as shown in FIG. 1.
    The inner code adds 10 bytes of parity to 172 symbols of the source data in the horizontal direction to form one codeword with 182 bytes. The correction capability is up to 5 bytes.
    Accordingly, in decoding, when data of one frame, that is, one codeword, is transmitted, correction is performed up to five errors. If five or more errors exist, the correction capability is exceeded.
    In this case, since 208 internal codewords are gathered together to form a block, when all internal codes are completed for 208 frames, an external code is generated in a vertical direction. The external code adds 16 bytes of parity to 192 symbols in the vertical direction. Configure.
    In this case, error correction is performed on the data of the error position where the erasure flag is generated in the inner code. When 16 or less flags occur, all of the outer code can be corrected.
    As described above, the error correction of the DVD system is in a Reed-Solomon error correction format. Normally, 37856 bytes of data are performed in units of 182 bytes horizontally and 208 bytes vertically. At this time, the horizontal correction as the inner code is referred to as PI (Parity Inner) error correction, and the vertical correction as the outer code is referred to as PO (Parity Outer) error correction.
    Fig. 2 is a block diagram showing the configuration of an error correcting apparatus of the conventional DVD system. The syndrome calculating unit 10 for detecting an error by calculating a syndrome from a code word of data read from a disc and inputting an erase flag signal is shown in FIG. An error polynomial unit 20 that calculates the number of erases and an error of calculating the error position coefficient using the output of the syndrome calculating unit 10 or an error of calculating the erase flag position coefficient using the output of the erasing polynomial unit 20 An error evaluation polynomial unit 40 for calculating a coefficient of an error evaluation polynomial by using a position polynomial unit 30, an output of the syndrome calculation unit 10, and an output of the error position polynomial unit 50. The Q & S unit 50 for calculating an error value and an error position using coefficients of the error position polynomial output from 30 and coefficients of the error evaluation polynomial output from the error evaluation polynomial unit 40, and And an erase flag generator 60 for generating the number of errors and an erase flag by using the output of the error position polynomial unit 30 and the output of the Chien search unit 50.
    The erasing flag generation unit 60 includes a counter 61 for counting the number of errors from the error position detected by the Q & A unit 50, the number of errors output from the counter 61 and the error position polynomial unit. (30) Comparing unit 62, which compares the actual number of errors (L) that are output from the output to generate an erase flag if not equal.
    3 is a flowchart illustrating a method of correcting an error in such a conventional DVD system.
    In the conventional error correction scheme configured as described above, when the disc is played (step 301), it is discriminated whether it is PI error correction or PO error correction (step 302).
    If it is determined in step 302 that PI error correction is performed, the syndrome calculation unit 10 calculates a syndrome using a code word of data read from the disk and outputs the syndrome to the error position polynomial unit 20 (step 303).
    Here, the syndrome depends on the error type. That is, the presence or absence of an error is detected.
    The error position polynomial unit 20 obtains the coefficient of the error position polynomial σ (x) from the syndrome element s (x) (step 304).
    In order to obtain an error value for each error location, the error evaluation polynomial unit 40 multiplies the syndrome polynomial S (x) by the error location polynomial σ (x) to obtain a coefficient of the error evaluation polynomial Ω (x) Output to section 50 (step 305).
    The search engine 50 finds an error location by finding the root of the error location polynomial σ (x) as one of algorithms used to obtain an error location value.
    That is, all the elements 1, α, α 2 , ..., α 181 of the galoa field GF are sequentially substituted into the error position polynomial σ (x) to find a root whose value becomes zero.
    If the error position polynomial σ (x) = 0 at α p , p becomes the error position value, and at this time, the load signal is output to the counter 61 of the erasing flag generator 60.
    Then, using the obtained error position value and the coefficient of the error evaluation polynomial (X), an error value corresponding to each error position is obtained (step 306).
    In addition, it is determined whether the PI error correction is PO error correction in order to generate the erase flag while performing the chien search (step 307).
    If it is determined that the PI error correction is performed, the counter 61 of the erasing flag generator 60 counts up every time the error position is obtained when the load signal is output from the Q & A unit 50, thereby obtaining the total number of errors.
    When the search is completed and the total number of errors is obtained from the counter 61, the comparing unit 62 compares whether the number of errors exceeds the correction capability (step 308).
    That is, the comparison unit 62 orders the highest order term of the error position polynomial unit 30, for example, the number of errors actually generated L and the number of errors output from the counter 62, for example, the number of errors to be corrected. In comparison, if it is not the same, it is determined that the correction capability has been exceeded, and an erasing flag of correction capability is generated (step 309).
    If it is determined in step 308 that the number of errors has not exceeded the correction capability, the PI error is corrected since the error position and error value are known (step 310).
    On the other hand, if it is determined in step 302 that PO error correction, the syndrome calculation unit 10 calculates a syndrome using a code word of the received data, and the erasing polynomial unit 20 receives an erasing flag and calculates the number of erases. (Step 311), it is output to the error position polynomial unit 20.
    The error position polynomial unit 20 obtains a coefficient of the erase position polynomial Φ (x) from the syndrome element s (x) and the number of erases (step 312).
    The output of the erase position polynomial unit 312 is input to the error evaluation polynomial unit 40 and the Chien search unit 50 as in the case of PI error correction, thereby obtaining an error position value and an error value (steps 305 and 306). ).
    If the error position value and the error value are obtained and determined as PO error correction in step 307, PO error correction is performed (step 310).
    That is, PO error correction performs error correction only when the erase flag occurs.
    In this way, since PO error correction is performed by the result of PI error correction, when error correction occurs in PI error correction and no erasure flag is generated, PO error correction does not perform error correction for the corresponding error position.
    This miscorrection is caused by data errors due to system instability or disk scratches.
    In addition, when the sector synchronization is shaken, the reliability of the frame is lowered, which increases the probability of miscorrection.
    In other words, PO error correction is performed to compensate for PI error correction, but if a problem occurs in PI error correction and improper erasure flag information is sent, PO error correction uses the error correction to correct the PI error correction. If the erase flag does not occur, correction cannot be made.
    SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to raise an error correction capability by forcibly generating an erase flag when there is a high probability that there is an error even if an erase flag does not occur in PI error correction. A correction apparatus and method are provided.
    Another object of the present invention is to provide an error correction apparatus and method for enhancing an error correction capability by forcibly generating an erase flag when a GFS (Good Frame Sync) signal generated when a synchronization is not properly synchronized and turned on during PI error correction. have.
    The error correction apparatus according to the present invention for achieving the above object is an error polynomial unit for calculating a syndrome from an input data word, and using the syndrome to calculate the coefficient of the error position polynomial and the coefficient of the error evaluation polynomial; An error position and error value calculator for performing an error search to obtain an error position using coefficients of the error position polynomial and calculating an error value using coefficients of the error position polynomial and coefficients of the error evaluation polynomial; A counter for counting the number of errors from the detected error position, a comparator for comparing whether the counted error number exceeds the correction capability of the internal code, and a GFS signal for generating a GFS signal if the sector synchronization is not detected or the position is incorrect The generation unit and the comparison unit determine that the number of errors exceeds the error correction capability of the internal code. Or an OR gate for generating an erase flag in the frame when a GFS signal is generated in the GFS signal generator.
    A feature of an error correction method according to the present invention is the step of calculating a syndrome from an input data word, calculating a coefficient of an error position polynomial and an coefficient of an error evaluation polynomial using the syndrome, and using the coefficient of the error position polynomial. Obtaining an error position by using the coefficient of the error position polynomial and the coefficient of the error evaluation polynomial, counting the number of errors from the detected error position, and counting the number of errors Comparing the correcting capability of the apparatus; generating a GFS signal if no sector synchronization is detected or its position is incorrect; and erasing flag on the frame when the number of errors is determined to exceed the correcting capability or a GFS signal is generated. It comprises the step of generating a.
    1 is a diagram illustrating an error correction method employed in a general DVD system.
    2 is a block diagram of a conventional error correction apparatus
    3 is a flowchart illustrating a conventional error correction method.
    4 is a block diagram of an error correction apparatus according to the present invention.
    5 is a flowchart illustrating an error correction method according to the present invention.
    Explanation of symbols for main parts of the drawings
    10: syndrome calculation unit 20: error position polynomial unit
    30: Elimination polynomial part 40: Error evaluation polynomial part
    50: Chien search department 70: Clearing flag generation part
    71: counter 72: comparison
    73: linear speed part 74: ora gate
    Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    4 is a block diagram of an error correction apparatus according to the present invention, including the syndrome calculation unit 10 except the erasing flag generation unit 70, the erasing polynomial unit 20, the error position polynomial unit 30, and the error evaluation polynomial. The unit 40 and the Q & S unit 50 have the same configuration and operation as those of FIG.
    In FIG. 4, only the erase flag generator 70 will be described.
    That is, the erasing flag generator 70 counts the error positions detected by the CNN search unit 50 to obtain a total number of errors, and an error number output from the counter 71 and the error position polynomial. Comparator 72 that compares the actual number of errors (L) that are output from the unit 30, the constant line speed (Gnstant Liner) that generates a GFS signal when the system is unstable or there is a scratch on the disk and the sector is not correct A Velocity (CLV) section 73, an OR gate 74 for generating an erase flag by logically combining the output of the comparison section 72 and the CLV 73.
    5 is a flowchart for performing an error correction method according to the present invention.
    According to the present invention configured as described above, the GFS signal is mainly generated when the system is unstable or the disk is scratched and the sector is not aligned. Therefore, an error is likely to exist in the data generated by the signal.
    Therefore, even if the erase flag is not generated during PI error correction, the erase flag is forcibly added to the data of the frame in which the GFS signal is generated.
    That is, when the disc is played back and data is received (step 501), it is first determined whether PI error correction or PO error correction (step 502).
    If it is determined in step 502 that PI error correction is made, the syndrome calculation unit 10 calculates a syndrome using a code word of data read from the disk, detects the presence of an error, and outputs the error to the error position polynomial unit 20 (step 503). ).
    The error position polynomial unit 20 obtains the coefficient of the error position polynomial σ (x) from the syndrome coefficient s (x) (step 504).
    In order to obtain an error value for each error position, the error evaluation polynomial unit 40 multiplies the coefficients of the syndrome polynomial S (x) and the error location polynomial σ (x) to obtain a coefficient of the error evaluation polynomial Ω (x). It outputs to the CQ search part 50 (step 505).
    The search engine 50 finds an error location by finding the root of the error location polynomial σ (x) as one of algorithms used to obtain an error location value.
    That is, all the elements 1, α, α 2 , ..., α 181 of the galoa field GF are sequentially substituted into the error position polynomial σ (x) to find a root whose value becomes zero.
    If the error position polynomial σ (x) = 0 at α p , p becomes the error position value, and at this time, the load signal is output to the counter 71 of the erasing flag generator 70.
    In addition, the Q-search unit 50 obtains an error value corresponding to each error position by using the obtained error position value and the coefficient of the error evaluation polynomial (X) (step 506).
    Then, whether the PI error correction or the PO error correction is performed in order to generate an erase flag while performing the chien search (step 507).
    If it is determined that the PI error correction is performed, the counter 71 of the erasing flag generator 70 counts up every time the error position is obtained when the load signal is output from the Q & A unit 50 to obtain the total number of errors.
    When the search is completed and the total number of errors is obtained from the counter 71, the comparing unit 72 compares whether the number of errors exceeds the correcting capability (step 508).
    That is, the comparison unit 72 is an order of the highest order term of the error position polynomial unit 30. For example, the number of errors actually generated and the number of errors output from the counter 72 are not equal. Otherwise, it is determined that the correction capability has been exceeded, and an erase flag of the correction disable capability is generated through the ora gate 74 (step 511).
    At this time, the CLV unit 73 generates a GFS signal and outputs the GFS signal to the OR gate 74 when the synchronization detection unit is not properly synchronized.
    Therefore, the OR gate 74 generates an erase flag when the GFS signal is generated in the CLV unit 73 even if the number of errors exceeds the correction capability or the number of errors does not exceed the correction capability (step 511).
    That is, when a GFS signal is generated, an erase flag is unconditionally generated even though no error occurs in PI error correction.
    As such, even if it is determined in step 508 that the number of errors has not exceeded the correction capability, an erase flag is generated when it is determined in step 509 that a GFS signal is generated.
    Therefore, PI error correction is made only if the number of errors does not exceed the correction capability and no GFS signal is generated (step 510).
    At this time, since the error search unit and the error value are known by the Q & A unit 50, PI error correction can be performed.
    On the other hand, if it is determined in step 502 that PO error correction, the syndrome calculation unit 10 calculates a syndrome using the received data code word, and the erase polynomial unit 20 receives an erase flag and calculates the erase count ( Step 512), outputs to the error position polynomial unit 20.
    The error position polynomial unit 20 obtains the coefficient of the erase position polynomial (X) from the syndrome element s (x) and the number of erases (step 513).
    Then, as in the case of output PI error correction of the erasure position polynomial unit 30, the error position polynomial unit 40 and the Chien search unit 50 are input to obtain an error position value and an error value (steps 505 and 506). .
    If the error position value and the error value are obtained and determined as PO error correction in step 507, PO error correction is performed (step 510).
    As described above, according to the error correction apparatus and method according to the present invention, when the error count in PI error correction does not exceed the correction capability and there is a high probability that there is an error, for example, sector synchronization is not correct. When the GFS signal is generated, an erase flag is forcibly generated for the frame, thereby preventing the error correction during PO error correction, thereby increasing the PO error correction capability.
    权利要求:
    Claims (8)
    [1" claim-type="Currently amended] An error polynomial means for calculating a syndrome from an input data word, calculating the coefficient of the error position polynomial and the coefficient of the error evaluation polynomial using the syndrome, and obtaining the error position using the coefficient of the error position polynomial; Error position and error value calculation unit for calculating error values using coefficients of polynomials and error evaluation, a counter for counting the number of errors from the detected error positions, and the counted error number for correcting an internal code A comparison unit for comparing whether or not, a GFS signal generator for generating a Good Frame Sync (GFS) signal when the sector synchronization is not detected or the position thereof is incorrect, and the result of the comparison unit and the output of the GFS signal generator are logically erased. Error correction device comprising a logic unit for generating a flag.
    [2" claim-type="Currently amended] The error correcting apparatus according to claim 1, wherein the error position and error value calculating means uses a Chien search algorithm.
    [3" claim-type="Currently amended] The error correcting apparatus according to claim 1, wherein the comparing unit compares the counted error number with the number of highest order terms of the error position polynomial and determines that the error number exceeds a correcting capability if not equal.
    [4" claim-type="Currently amended] The error correcting apparatus of claim 1, wherein the logic unit generates an erase flag in the frame when it is determined by the comparing unit that the number of errors exceeds the error correcting capability of an internal code.
    [5" claim-type="Currently amended] The error correcting apparatus of claim 1, wherein the logic unit generates an erase flag in a frame when a GFS signal is generated in the GFS signal generator.
    [6" claim-type="Currently amended] The error correcting apparatus of claim 1, wherein the logic unit comprises an OR gate for performing an OR between the output of the comparator and the output of a GFS signal generator.
    [7" claim-type="Currently amended] Calculating a syndrome from an input data word, calculating a coefficient of an error position polynomial and a coefficient of an error evaluation polynomial using the syndrome, obtaining an error position using the coefficient of the error position polynomial, and calculating the coefficient of the position polynomial And calculating an error value using the coefficient of the error evaluation polynomial, counting the number of errors from the detected error position, comparing whether the counted error number exceeds the correctability of an internal code, and Generating a GFS signal if the synchronization is not detected or the position thereof is wrong, and determining that the number of errors exceeds the correcting capability, or generating an erase flag in the frame when the GFS signal is generated. Correction method.
    [8" claim-type="Currently amended] 8. The error correction method according to claim 7, wherein the step compares the number of counted errors with the number of error position polynomial highest order terms and determines that the number of errors exceeds the correction capability if not equal.
    类似技术:
    公开号 | 公开日 | 专利标题
    KR960003094B1|1996-03-04|Error correction code generator
    KR100923871B1|2009-10-27|Recording method, optical disc, and reproduction apparatus
    AU604836B2|1991-01-03|Method and apparatus for error correction
    US5247523A|1993-09-21|Code error correction apparatus
    US7103829B2|2006-09-05|Coding for informed decoders
    US5051998A|1991-09-24|Data block deinterleaving and error correction system
    EP0150811B1|1990-12-12|Method and apparatus for recording digital signals
    US6631490B2|2003-10-07|Encoding unit and decoding unit
    US7900125B1|2011-03-01|Majority detection in error recovery
    JP2821324B2|1998-11-05|Error correction circuit
    CN100444275C|2008-12-17|Method of correcting data on a high-density recording medium
    US4564945A|1986-01-14|Error-correction code for digital data on video disc
    US6003151A|1999-12-14|Error correction and detection system for mass storage controller
    CA1258134A|1989-08-01|Error correction method
    US6512644B1|2003-01-28|Method and apparatus for read-after-write verification with error tolerance
    US6272659B1|2001-08-07|Error correction code processor employing adjustable correction power for miscorrection minimization
    US4764927A|1988-08-16|Code error correcting method
    US6772385B2|2004-08-03|Error-correcting device and decoder enabling fast error correction with reduced circuit scale
    US7350129B2|2008-03-25|Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method
    US8166369B2|2012-04-24|Method for error processing in optical disk memories
    EP0998791B1|2002-06-05|Concurrent row/column syndrome generator for a product code
    US6367047B1|2002-04-02|Multi-level error detection and correction technique for data storage recording device
    US6363511B1|2002-03-26|Device and method for decoding data streams from storage media
    EP0291167A2|1988-11-17|A code error detecting method
    US5020060A|1991-05-28|Error code correction device having a galois arithmetic unit
    同族专利:
    公开号 | 公开日
    KR100209676B1|1999-07-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-31|Application filed by 구자홍, 엘지전자 주식회사
    1996-12-31|Priority to KR1019960079292A
    1998-10-07|Publication of KR19980059945A
    1999-07-15|Application granted
    1999-07-15|Publication of KR100209676B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960079292A|KR100209676B1|1996-12-31|1996-12-31|Error correction apparatus and method|
    [返回顶部]