Method for preventing degradation of the gate oxide film using the polysilicon layer for the main ga

专利摘要:
When forming a gate by dry etching such as plasma etching, a method of preventing damage to the gate oxide film by preventing pairs of charges on the gate is provided. A method of the present invention comprises the steps of: sequentially depositing a gate oxide film and a material layer for a gate electrode on a semiconductor substrate; Forming a photoresist pattern on the gate electrode material layer; Dry etching the gate electrode material layer using the photoresist pattern as a mask, and performing the dry etching until the thickness of the gate electrode material layer is about 20-100 μm, thereby forming a material layer for the main gate electrode. Doing; Removing the photoresist pattern; Forming a gate electrode by oxidizing the material layer for the main gate electrode. The dry etching is performed by plasma etching.
公开号:KR19980057697A
申请号:KR1019960076996
申请日:1996-12-30
公开日:1998-09-25
发明作者:김승현
申请人:김광호；삼성전자 주식회사；
IPC主号:

专利说明:

Deterioration Prevention Method of Gate Oxide Film Using Polysilicon Layer for Remain Gate Electrode
The present invention relates to a method for preventing deterioration of a gate oxide film, and more particularly, to a method capable of preventing damage to a gate oxide film from a flow of uneven ions and electrons during plasma etching.
As semiconductor devices are highly integrated, the gate oxide film thickness of transistors is also thinning. The thin gate oxide film has a problem of being easily deteriorated in the manufacturing process of the semiconductor device. In particular, the gate oxide film is damaged a lot during plasma etching.
The deterioration of the gate oxide film by plasma etching results from the nonuniformity of the plasma. Non-uniformity of plasma refers to the flow of ions or electrons that are locally nonuniform. That is, ions and electrons do not occur at an equal ratio with each other, and any one species is relatively generated locally. If a locally non-uniform flow of ions / electrons occurs during plasma etching, for example, if a relatively large amount of positive charges locally occurs, charges begin to build up at the end of the etching. Accumulated charge is concentrated in the weak region of the gate oxide, increasing the Fowler-Nordheim turnneling current. As a result, a high electric field is applied to the weak region of the gate oxide film. The high electric field puts stress on the fragile region, causing severe breakdown of the gate oxide. Even such severe levels can cause gate leakage, low breakdown fields, and reduced device reliability.
Hereinafter, damage to the gate oxide film during plasma etching will be described in detail with reference to FIGS. 1A to 1C.
FIG. 1A is a cross-sectional view of a gate electrode polysilicon layer and a gate oxide film when plasma etching is in progress, and FIG. 1B is a gate electrode polysilicon layer and a gate below which electric charges begin to accumulate at the end of plasma etching. The oxide film is shown in cross-sectional view, and FIG. 1C is an enlarged cross-sectional view showing damage to the gate oxide film at the portion where the charge is accumulated.
As shown in FIG. 1A, a photoresist pattern 9 is formed on a structure in which a semiconductor substrate 50, a gate oxide film 7, and a polysilicon layer 3 for a gate electrode 3 are sequentially formed to form a gate electrode. Plasma etching is performed as a mask. At this time, the flow of cations is larger than the flow of electrons as a locally non-uniform plasma is generated (1). Ji and -Je in FIG. 1A represent a cation flow and an electron flow, respectively. When etching is performed using the photoresist pattern 9 as a mask in a state where such non-uniform plasma is generated, excess charge flows into the polysilicon layer 3 for the gate electrode (5). The introduced charge is dispersed in the conductive polysilicon layer for the gate electrode. As the charge continues to dissipate, the balance of total cations / electrons in the plasma etch system will be maintained. In addition, the gate oxide film 7 under the gate electrode polysilicon layer 3 is not affected by the excess charge.
However, as shown in FIG. 1B, when the etching of the polysilicon layer for the gate electrode reaches the end point, the gate electrode is separated into an island-like shape and the excess charge cannot be distributed to other regions. . Excess charge that has not been dispersed begins to accumulate in the gate electrode 3.
FIG. 1C is an enlarged cross-sectional view of the portion indicated by 11 in FIG. 1B. As can be seen from this, the accumulated charge is concentrated in the weak region of the gate oxide film 7, that is, the portion 13 where the gate oxide film is thinned. The concentrated charge stresses the gate oxide film, which not only affects the reliability and yield of the transistor, but also severely causes a short circuit as shown in FIG. This deterioration of the gate oxide film becomes more serious as the gate oxide film becomes thinner.
As a result, in order to form a thin gate oxide film for highly integrated semiconductor devices, deterioration of the gate oxide film during etching must be prevented.
The technical problem of the present invention for solving the above problems is to provide a method that can prevent damage to the gate oxide film by preventing the charge accumulation at the interface between the gate electrode and the gate oxide film when forming the gate electrode by plasma etching. .
1A to 1C are cross-sectional views illustrating a deterioration of a gate oxide layer when etching a polysilicon layer for a gate electrode by plasma etching according to the related art.
2A to 2D are cross-sectional views illustrating a method of preventing degradation of a gate oxide film according to the present invention.
The present invention for achieving the above technical problem, the step of sequentially stacking a gate oxide film and a polysilicon layer for the gate electrode on a semiconductor substrate; Forming a photoresist pattern on the polysilicon layer for the gate electrode; Dry etching the polysilicon layer for the gate electrode using the photoresist pattern as a mask, and performing the dry etching until the thickness of the polysilicon layer for the gate electrode remains about 20-100 μm. Forming a layer; Removing the photoresist pattern; Forming a gate electrode by oxidizing the polysilicon layer for the main gate electrode. The dry etching is performed by plasma etching.
Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
Referring to FIG. 2A, a gate oxide film 103 is formed on the semiconductor substrate 101 to a thickness of about 100 GPa, and then a polysilicon layer 105 for a gate electrode is formed by CVD. Next, the photoresist is covered and exposed to alignment and development to form the photoresist pattern 107, and then plasma etching is performed using the photoresist as a mask. At this time, a locally non-uniform plasma 109 is generated and excess charge is introduced into the polysilicon layer 105 for the gate electrode and then dispersed (111). It is known that the main cause of the plasma non-uniformity lies in hardware and process conditions. Locally uneven plasma occurs when the design of the electrodes is poor or the magnetic field is uneven in hardware, ie plasma etching equipment. In addition, non-uniform plasma may be generated from process conditions such as pressure or flow rate selection or gas selection during operation of the equipment.
Referring to FIG. 2B, the polysilicon layer 105 ′ for the main gate electrode is formed without leaving all the polysilicon layers 105 for the gate electrode etched by about 20 to 100 μm. As it can be seen from Figure 2b, the polysilicon layer for the main gate electrode of the present invention is formed in a structure in which the entire polysilicon layer is not etched to remain about 20-100Å so as to disperse the positive charges introduced by the non-uniform plasma It is done. Next, N-ion implantation is performed in the state where the photoresist pattern 107 is present (113) to form the N-junction region 115.
Referring to FIG. 2C, the photoresist pattern 107 is removed using a sulfuric acid strip. Next, the polysilicon layer 105 ′ for the main gate electrode is oxidized to form an oxide film 117 and a gate electrode 119.
Referring to FIG. 2D, a spacer 121 is formed by depositing a high temperature oxide layer (HTO) on the oxide layer 117 and then performing front surface dry etching to implement a lightly doped drain (LDD) structure. Next, N + ion implantation 123 is performed on the resultant.
The present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical spirit of the present invention. For example, the present invention is applicable not only to plasma etching but also to reactive ion etching. When a glow discharge is initiated in reactive ion etching, electrons begin to be stored in the photoresist and blocking capacitor, for example. When the photoresist becomes polar with the stored electrons, positive charges begin to build up on the surface of the polysilicon layer below the photoresist. After the polysilicon layer is patterned and separated into island shapes, that is, when the polysilicon gate is formed, an excessive amount of positive charges that are not dispersed deteriorates the gate oxide layer. In order to prevent this, the gate oxide film degradation prevention method using the polysilicon layer for the main gate electrode of the present invention may be adopted.
In addition, although the present invention describes only polysilicon as a material constituting the gate electrode, it is obvious to those skilled in the art that the present invention can be applied to forming a gate made of other conductive materials. to be.
According to the present invention, it is possible to prevent deterioration of the gate oxide film due to charge accumulation by preventing the accumulation of charges on the polysilicon layer by not etching the gate silicon polysilicon layer to the end.

权利要求:
Claims (2)
[1" claim-type="Currently amended] Sequentially depositing a gate oxide layer and a material layer for the gate electrode on the semiconductor substrate;
Forming a photoresist pattern on the gate electrode material layer;
Dry etching the gate electrode material layer using the photoresist pattern as a mask, and performing the dry etching until the thickness of the gate electrode material layer is about 20-100 μm, thereby forming a material layer for the main gate electrode. Doing;
Removing the photoresist pattern;
And forming a gate electrode by oxidizing the material layer for the main gate electrode.
[2" claim-type="Currently amended] The method of claim 1, wherein the dry etching is performed by plasma etching.

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同族专利:

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公开号 | 公开日

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KR100213224B1|1999-08-02|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1996-12-30|Application filed by 김광호, 삼성전자 주식회사

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1996-12-30|Priority to KR1019960076996A

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1998-09-25|Publication of KR19980057697A

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1999-08-02|Application granted

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1999-08-02|Publication of KR100213224B1

优先权:

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申请号 | 申请日 | 专利标题

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KR1019960076996A|KR100213224B1|1996-12-30|1996-12-30|Method for preventing deterioration of gate oxide using polysilicon layer for gate electrode|