• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to an alignment pattern, and by marking the alignment keys (x-align key and y-align key) respectively, there is no fear of assisting the other layers in the case of the stepper during wafer manual alignment. In the case of the scanner, two wafer alignment keys are created for each layer, and the intervals of the respective alignment keys are set differently so that manual assist may be induced even if the first chip is misaligned, even if the first chip is misaligned.
    公开号:KR19980056453A
    申请号:KR1019960075723
    申请日:1996-12-28
    公开日:1998-09-25
    发明作者:양현조
    申请人:문정환；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Alignment pattern
    1 is a view illustrating a conventional alignment pattern,
    2 is a view illustrating an alignment pattern of the present invention.
    * Explanation of symbols for main parts of the drawings
    10: y-align key 11: x-align key
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alignment pattern, and more particularly, to an alignment pattern suitable for manual assist.
    In the exposure apparatus for forming a fine pattern in a semiconductor manufacturing process, a stepper and a scanner are mainly used.
    When the exposure process is performed using these exposure apparatuses, alignment is performed on the previous layer, which is first subjected to the entire wafer alignment and chip alignment stages.
    In the first step, the whole wafer is aligned, the shift and rotation components in the x and y directions of the wafer are aligned with an accuracy of several micrometers to several tens of micrometers.
    1 is a view for explaining a conventional alignment pattern, Figure 1 (a) (c) is a view showing a patterned wafer, Figure 1 (b) is a stopper X-align key and Y -A diagram showing a conventional alignment pattern having an alignment key, and FIG. 1 (d) shows a conventional alignment pattern having a wafer alignment key in the case of a scanner.
    Hereinafter will be described with reference to the accompanying drawings.
    Full wafer alignment is performed automatically at first, and manual assist is provided if automatic alignment fails.
    In the second step, several chips in the wafer are finely aligned for each chip, and x, y shift, rotation, and magnification are calculated to align the alignment chip with an alignment accuracy of about 0.1 μm or less.
    As shown in (a) and (b) of FIG. 1, in the case of the stepper, the wafer alignment method uses the y-align key 10 on the left field A and the right field to align the y-shift and the wafer rotation components. The x-shift component is aligned using the x-align key 11 using the x-align key of the field B on the right axis.
    1 (c) and (d), in the case of the scanner, the wafer alignment method uses the wafer alignment key 12 of the left field A 'and the right field B' on the x, y-shift. And wafer rotation components.
    However, in the conventional alignment pattern, when a plurality of layers are progressed, a plurality of wafer alignment keys exist. It is not known which key is a layer to be aligned.
    Therefore, it often happens to assist other layers. In the case of the stepper, if you misalign the y-align key, the x-align key will not be found. There is a lot of trial and error.
    In the case of the scanner, incorrectly assisting the wafer alignment key results in an invalid wafer alignment key, and thus, an alignment key cannot be found during chip alignment.
    Accordingly, the present invention has been made to solve such a problem, and in order to prevent misalignment in other layers during wafer manual assist, an alignment pattern capable of preventing misalignment due to failure to find an alignment key in a subsequent chip arrangement is performed. The purpose.
    The present invention is an alignment pattern in which a name is inserted into the y-array key of each X-array key, thereby preventing inadvertently assisting another pattern during manual assist.
    Figure 2 is a view for explaining the alignment pattern of the present invention, Figure 2 (a) (c) is a view showing a wafer on which the pattern is formed, Figure 2 (b) is a respective alignment to align the wafer FIG. 2D illustrates an alignment pattern in which the spacing of each alignment key is formed differently to align the wafers.
    Hereinafter, with reference to the accompanying drawings will be described.
    In the alignment pattern of the present invention for arranging wafers, names are inserted into the X-array key and the y-array key of each pattern, as shown in FIG.
    In the case of the stepper, manual assist should be performed on the first wafer.
    Therefore, if a layer name is inserted for each wafer alignment key, assisting another layer does not occur during manual assist.
    As an embodiment of the alignment pattern of the present invention, as shown in FIG. 2 (c) (d), two wafer alignment keys are formed for each layer, and the gaps between the respective wafer alignment keys are formed differently.
    In the case of a scanner, manual assist is provided only when automatic alignment fails, and there is a possibility that automatic alignment is performed on another layer when the wafer is greatly out of position.
    Therefore, two wafer alignment keys are created for each layer, and the distance between the two alignment keys is put differently, and when the alignment is performed, as shown in (c) and (d) of FIG. 2, in the left chip (c '), (d) You can set the left key to use and the right key to use the right chip (d ').
    Then, if the automatic alignment is performed on another layer, the position is changed at the second position, so that the wafer alignment may fail, and the manual assist may be induced.
    As described above, in the alignment pattern of the present invention, if the name of each layer is put in the wafer alignment key, it is possible to prevent the case of assisting to another layer during manual assist, and also to arrange the automatic alignment in the wrong layer. To prevent this problem, insert two wafer alignment keys, and change the distance between the two alignment keys for each layer. Therefore, if the left chip (c ') is aligned using the left alignment key and the right chip (d') is aligned using the right alignment key, the alignment is different from the left chip (c '). do.
    Therefore, automatic sorting can be misaligned with other layers, preventing the chip sorting key from failing.
    That is, in the present invention, by inserting a name into the alignment key, there is no fear of assisting another layer during manual assist, and thus, trial and error can be reduced during alignment.
    In addition, two wafer alignment keys are created for each layer, and the intervals of the respective alignment keys are set differently so that manual assist can be induced because the alignment is not performed at the second position even if the first chip is misaligned.
    权利要求:
    Claims (2)
    [1" claim-type="Currently amended] An alignment pattern for arranging wafers, wherein the names are inserted into the X-align key and the y-align key of each pattern, respectively.
    [2" claim-type="Currently amended] An alignment pattern for automatically arranging wafers, wherein two alignment keys are formed in each pattern, and the alignment pattern is formed differently between the respective alignment keys.
    类似技术:
    公开号 | 公开日 | 专利标题
    KR970010666B1|1997-06-30|Measurement of attern overlay of semiconductor device
    CN101334802B|2011-02-09|Method for verifying pattern of semiconductor device
    US6489068B1|2002-12-03|Process for observing overlay errors on lithographic masks
    US5696835A|1997-12-09|Apparatus and method for aligning and measuring misregistration
    US8685853B2|2014-04-01|Dual damascene copper process using a selected mask
    EP0370834B1|2000-02-02|Method of manufacturing a semiconductor device
    US5877861A|1999-03-02|Method for overlay control system
    KR850002681A|1985-05-15|Mask pattern inspection method for semiconductor device manufacturing
    EP0061536B1|1985-04-24|Method of manufacturing a semiconductor device having improved alignment marks and alignment marks for said method
    US4849313A|1989-07-18|Method for making a reticle mask
    KR100782489B1|2007-12-05|Fabrication method for photomask, fabrication method for device and monitoring method for photomask
    US6529625B2|2003-03-04|Position detecting method and position detecting device for detecting relative positions of objects having position detecting marks by using separate reference member having alignment marks
    US8183123B2|2012-05-22|Method of forming mark in IC-fabricating process
    EP0097831A2|1984-01-11|Optical projection systems and methods of producing optical images
    JP3042639B2|2000-05-15|Photo reticles for semiconductor device manufacturing
    US5786267A|1998-07-28|Method of making a semiconductor wafer with alignment marks
    US20050112504A1|2005-05-26|Method of producing semiconductor integrated circuit device and method of producing multi-chip module
    US20120244461A1|2012-09-27|Overlay control method and a semiconductor manufacturing method and apparatus employing the same
    EP0466335B1|1998-10-14|Process of manufacturing semiconductor devices
    US4985374A|1991-01-15|Making a semiconductor device with ammonia treatment of photoresist
    US6225013B1|2001-05-01|Stitching design rules for forming interconnect layers
    US20030174879A1|2003-09-18|Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same
    US6861186B1|2005-03-01|Method for backside alignment of photo-processes using standard front side alignment tools
    US4883359A|1989-11-28|Alignment method and pattern forming method using the same
    KR100470181B1|2005-05-19|Simplified hole interconnect process
    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-28|Application filed by 문정환, 엘지반도체 주식회사
    1996-12-28|Priority to KR1019960075723A
    1998-09-25|Publication of KR19980056453A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960075723A|KR19980056453A|1996-12-28|1996-12-28|Alignment pattern|
    [返回顶部]