Metal wiring formation method of semiconductor device
专利摘要:
The present invention relates to a method for manufacturing a semiconductor device, and by performing a double mask process to form a via hole and a metal wiring, unnecessary vias are added during the manufacturing process to solve the problem of causing productivity problems and difficulty. Provided is a method of forming a metal wiring of a semiconductor device that can reduce cost and improve productivity by forming a mask capable of forming holes and metal wirings simultaneously through a double exposure process of a photosensitive film. 公开号:KR19980054458A 申请号:KR1019960073621 申请日:1996-12-27 公开日:1998-09-25 发明作者:김종일 申请人:김영환;현대전자산업 주식회사; IPC主号:
专利说明:
Metal wiring formation method of semiconductor device BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device. Referring to the accompanying drawings, the problem of the prior art is as follows. 1A to 1D are cross-sectional views sequentially illustrating a metal wiring forming method by a conventional dual damascene process. FIG. 1A is a cross-sectional view of forming a via hole mask 13 after forming an oxide film 12 on a semiconductor substrate 11 and applying a photosensitive film. FIG. 1B is a cross-sectional view of the oxide film 12 being etched using the via hole mask to form the via hole 14 and then removing the via hole mask. FIG. 1C is a cross-sectional view of a metal wiring mask 15 formed by applying a photosensitive film on the oxide film 12 on which the via hole 14 is formed. As shown in FIG. 1D, the selected area of the oxide layer 12 is etched using the metal wiring mask to form a metal wiring pattern, and then the metal wiring mask is removed. After the metal 16 is sufficiently coated to fill the formed metal wires and via holes, the metal on the oxide film 12 is removed to expose the surface of the oxide film 12. In this case, the metal embedded in the via hole and the metal wiring is in equilibrium with the oxide film surface. As described above, the metal wiring forming method by the damascene process is unnecessary during the manufacturing process by using a via mask and a metal wiring mask to form a via hole and a pattern on which the metal wiring is to be formed. This addition leads to a loss of productivity and difficulty. Accordingly, an object of the present invention is to provide a metal wiring forming method which can improve productivity by simultaneously forming a via hole and a metal wiring using a mask once. The present invention for achieving the above object is to form an oxide film on the semiconductor substrate and to form a photosensitive film, and to perform a double exposure process on the photosensitive film to form a mask for use in via holes and metal wiring, and the mask Simultaneously forming the via hole and the metal wiring pattern by etching the oxide film, removing the photoresist film used as the mask, and depositing metal to form the buried hole and the metal wiring at the same time; Characterized in that the step consisting of removing. 1A to 1D are cross-sectional views of devices sequentially shown in order to explain a metal wiring forming method by a conventional dual damascene process. 2A to 2D are cross-sectional views of devices sequentially shown for explaining the metal wiring forming method according to the present invention. * Description of the symbols for the main parts of the drawings * 11, 21: semiconductor substrate 12, 22: oxide film 13: via hole mask 14, 24: via hole 15: metal wiring mask 16, 25: metal 23: via hole and metal wiring mask The present invention will be described in detail with reference to the accompanying drawings. 2A to 2D are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings according to the present invention. As shown in FIG. 2A, an oxide film 22 is formed on the semiconductor substrate 21 and a photoresist film is formed on the oxide film 22. A double exposure process is performed on the photosensitive film to form a mask 23 for use in the via hole and the metal wiring. 2B is a cross-sectional view of simultaneously forming the via hole 24 and the metal wiring pattern by etching the oxide film 22 using a mask. FIG. 2C is a cross-sectional view of removing the photoresist film used as a mask and depositing metal 25 to form a buried via hole and metal wiring. 2D is a cross-sectional view of the oxide film 22 exposed by removing the metal on the oxide film 22 by the CMP process. As described above, the process can be simplified by simultaneously forming the via hole and the metal wiring formed through the double mask work through one mask work. As described above, according to the present invention, the number of processes can be reduced to reduce costs and the productivity can be improved.
权利要求:
Claims (1) [1" claim-type="Currently amended] Forming an oxide film on the semiconductor substrate and forming a photosensitive film; Performing a double exposure process on the photoresist to form a mask for via holes and metal wiring; Simultaneously forming the via hole and the metal wiring pattern by etching the oxide film using the mask; Removing the photoresist film used as the mask and depositing a metal to simultaneously form a buried via hole and a metal wiring; Removing the metal on the oxide film.
类似技术:
公开号 | 公开日 | 专利标题 KR100388591B1|2003-06-25|Fine pattern formation method and semiconductor device or liquid crystal device manufacturing method employing this method KR970030645A|1997-06-26|Device isolation insulating film formation method of semiconductor device KR970007174B1|1997-05-03|Method wiring method for semiconductor device JP3981353B2|2007-09-26|Method of manufacturing an integrated circuit KR100641500B1|2006-10-31|Method for fabricating dual damascene pattern in a semiconductor KR100822581B1|2008-04-16|Method of manufacturing a flash memory device KR970007831B1|1997-05-17|Simultaneously forming method of metal wire and contact plug US6511916B1|2003-01-28|Method for removing the photoresist layer in the damascene process KR100769405B1|2007-10-22|Pattern forming method KR970003459A|1997-01-28|Method of forming via hole in semiconductor device KR970018221A|1997-04-30|Flattening method KR100460064B1|2004-12-04|Method for forming metal wiring of semiconductor device KR20040055459A|2004-06-26|Method for forming bit line of semiconductor device KR100265596B1|2000-10-02|Method for manufacturing semiconductor device JPH11204654A|1999-07-30|Method for forming gate electrode with double gate insulating films JP2720023B2|1998-02-25|Method for manufacturing semiconductor device JPH0669351A|1994-03-11|Manufacture of contact of multilayer metal interconnection structure KR100562308B1|2006-03-22|Method for forming contact hole in semiconductor device CN1050693C|2000-03-22|Method of planarizing film of semiconductor device KR100505414B1|2005-08-04|method for forming align key JP4082812B2|2008-04-30|Semiconductor device manufacturing method and multilayer wiring structure forming method JP4023236B2|2007-12-19|Method for forming metal wiring KR20030000475A|2003-01-06|Method for forming a pattern KR20030051000A|2003-06-25|Method of forming miniature pattern semiconductor device KR100363642B1|2002-12-05|Method for forming contact hole of semiconductor devices
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引用文献:
公开号 | 申请日 | 公开日 | 申请人 | 专利标题
法律状态:
1996-12-27|Application filed by 김영환, 현대전자산업 주식회사 1996-12-27|Priority to KR1019960073621A 1998-09-25|Publication of KR19980054458A
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申请号 | 申请日 | 专利标题 KR1019960073621A|KR19980054458A|1996-12-27|1996-12-27|Metal wiring formation method of semiconductor device| 相关专利
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