• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for stabilizing an address supplied to a semiconductor memory. In general semiconductor memory circuits, since there is no special preparation means, error data is generated or even if provided, the configuration is complicated and the cost is increased. There was a bug let in. Therefore, in order to solve this problem, the present invention provides an address detector 11, an address transition detection signal ATD, and an output signal of the address detector 11 that examine a temporal state of change of an address signal and output a detection signal accordingly. An address latch unit 12 for latching different logic values when a valid address signal and an invalid address signal are supplied on the basis thereof, and a predetermined value when an invalid address signal is input based on a logic value latched to the address latch unit 12. A valid address detection unit 10A configured of a detection signal output unit 13 for outputting a valid address detection signal a1 of? When all the valid address detection units 10A-10N detect a valid address signal, it is comprised by the all valid address determination part 14 which outputs the predetermined valid address detection signal V. FIG.
    公开号:KR19980054415A
    申请号:KR1019960073576
    申请日:1996-12-27
    公开日:1998-09-25
    发明作者:정준섭
    申请人:문정환；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Effective Address Detection Circuit of Semiconductor Memory
    1 is a valid address detection circuit diagram for one address of the present invention.
    2 is an overall circuit diagram of an effective address detection circuit of the semiconductor memory of the present invention.
    Explanation of symbols on the main parts of the drawings
    11 address detecting unit 12 address latching unit
    13 detection signal output section 14 all valid address determination section
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for stabilizing an address supplied to a semiconductor memory and the like, and more particularly, to an effective address detection circuit of a semiconductor memory in which an error caused by stabilizing an address affected by noise to a valid address is prevented.
    In general, when an address is supplied to output data from a semiconductor memory, the address is affected by noise generated from a peripheral device or noise introduced from the outside. For example, the voltage level of an address is momentarily caused by noise. The new address will act as if a new address was supplied.
    Nevertheless, a general semiconductor memory circuit is not provided with a special preparation means, so that error data may occur or even if provided, there is a defect that the cost is increased due to the complicated configuration.
    Accordingly, it is an object of the present invention to provide a valid address detection circuit of a simple configuration in which an address that does not last for a certain time is observed as an address generated by noise by observing a change in the address.
    FIG. 1 is a basic circuit diagram of an effective address detection circuit of a semiconductor memory of the present invention for achieving the above object. As shown therein, an address detection unit 11 for investigating a temporal state of change of an address signal and outputting a detection signal accordingly. )Wow; An address latch unit 12 for latching different logical values when a valid address signal and an invalid address signal are supplied based on an address transition detection signal ADT and an output signal of the address detection unit 11; The detection signal output section 13 outputs a predetermined valid address detection signal a1 when an invalid address signal is input based on the logical value latched to the address latch section 12.
    2 is an overall block diagram of an effective address detection circuit of a semiconductor memory of the present invention for achieving the above object, as shown in FIG. A valid address detection unit 10A-10N for respectively outputting detection signals a1-an; When the valid address detection unit 10A-10N detects all valid address signals, the effective address detection unit 14 outputs a predetermined valid address detection signal V. The operation of the present invention and The effect will be described in detail as follows.
    First, the validation detection process for one address signal Add1 will be described with reference to FIG.
    When the address transition detection signal ADT is supplied high and the PMOS MP1 and the NMOS MN2 are turned on, and the address signal Add1 is temporarily turned high due to noise, the address signal Add1 Is supplied directly to one input terminal of the exclusive noah gate (XNOR1), and is delayed for a predetermined time through the delay 11A, and is supplied to the other input terminal of the exclusive noah gate (XNOR1). Is output.
    Accordingly, PMOS MP2 is turned on by the low signal compared to and output from the exclusive noar gate XNOR1, while NMOS MN1 is turned off, and the low signal is latched to the latch 12A. The latched low signal is inverted to a high signal again through the inverter I3 and then supplied to the gate of the NMOS MN3 so that the NMOS MN3 is turned on so that the effective address detection signal a1 is outputted low. .
    However, unlike the above, when the address signal Add1 is substantially supplied, that is, when the address signal Add1 is valid, even if noise occurs, the low signal is output from the exclusive nodal gate XNOR1 for a while and then continues. Since the high level signal is output and the address transition detection signal ATD is turned low, both the NMOS MN1 and the MN2 are turned on while the PMOS MP2 is turned off, and the high signal is applied to the latch 12A. Is latched. The latched high signal is inverted back to a low signal through the inverter I3 and then supplied to the gate of the NMOS MN3 so that the NMOS MN3 is turned off, so that the effective address detection signal a1 terminal has a floating state. do.
    Since the effective address detection unit 10A operating in the same manner as the first diagram is provided for each address signal Add1-Addn, the overall circuit configuration is the same as that of the second diagram.
    That is, when one or more address signals are generated by noise as a result of detecting each address signal Add1-Addn through each valid address detection unit 10A-10N, that is, an invalid address exists. In this case, one or more detection signals among the valid address detection signals a1-an will be output low, and thus, the effective address detection for outputting the low signal through the power supply terminal voltage V DD NMOS MN4 will be performed. The effective address detection signal V is output from the inverter I4 through the terminal of the signal and the corresponding NMOS to output a high signal.
    Therefore, it is possible to prohibit the memory chip from performing the initialization operation unnecessarily based on the high signal.
    However, as a result of detecting each address signal Add1-Addn through each valid address detection unit 10A-10N, when all of the valid address detection signals a1-an are valid, the address signals Add1-Addn are valid. Since the floating state is maintained, the power supply terminal voltage V DD is supplied to the input terminal of the inverter I4 through the NMOS MN4, and a valid address detection signal V is output from the low signal.
    As described in detail above, the present invention has the effect of allowing the system to be operated more stably by detecting an invalid address signal generated by noise using a detection circuit of a simple configuration.
    权利要求:
    Claims (2)
    [1" claim-type="Currently amended] Valid address signals and invalid addresses based on the address detection unit 11, the address transition detection signal ATD, and the output signals of the address detection unit 11, which examine the temporal state of change of the address signal and output a detection signal accordingly. The address latch unit 12 latches different logic values when a signal is supplied, and outputs a predetermined valid address detection signal a1 when an invalid address signal is input based on the logic values latched to the address latch unit 12. A valid address detection unit 10A including a detection signal output unit 13; The effective address of the semiconductor memory, characterized in that the plurality of valid address detection units 10A-10N comprise all the valid address determination units 14 which output a predetermined valid address detection signal V when all valid address signals are detected. Detection circuit.
    [2" claim-type="Currently amended] 2. The address detection unit (11) according to claim 1, further comprising: a delay unit (11A) for delaying and outputting the address signal by a predetermined time; An effective address detection circuit of a semiconductor memory, comprising an exclusive no-gate (XNOR1) for performing an exclusive Noa operation on an address signal supplied directly and an address signal supplied through the delay unit (11A).
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-27|Application filed by 문정환, 엘지반도체 주식회사
    1996-12-27|Priority to KR1019960073576A
    1998-09-25|Publication of KR19980054415A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960073576A|KR19980054415A|1996-12-27|1996-12-27|Effective Address Detection Circuit of Semiconductor Memory|
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