• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to an I 2 C bus control circuit in a video reproducing apparatus that enables communication between the memory and the microcomputer (i.e., the microcomputer) even when only standby power ST is supplied in a state where no operating power is supplied to the memory. A plurality of slaves (10, 11, 12, ---) and a microcomputer (1) for controlling the slaves are connected to an I 2 C bus formed of a data transmission line (SDA) and a clock transmission line (SCK). In the video reproducing apparatus in which the microcomputer 1 and the slaves 10, 11, 12, --- can transmit and receive various data signals and clock signals through the I 2 C bus, standby power is supplied. When the I 2 C bus between the micom 1 and a specific slave is operated to enable bidirectional communication between the micom 1 and a specific slave and when operating power is supplied, the micom 10 and the slave to the I 2 C bus between the (10,11,12, ---), the operation Further it includes a buffer control unit 20 to two-way communication is to be between yikeom and said slave (10,11,12, ---) is characterized in that configured.
    公开号:KR19980046450A
    申请号:KR1019960064792
    申请日:1996-12-12
    公开日:1998-09-15
    发明作者:김철；이기순
    申请人:배순훈；대우전자 주식회사；
    IPC主号:
    专利说明:

    Inner Intergrated Circuit (I2C) Bus Control Circuit in Video Playback Equipment
    The present invention relates to an I 2 C bus control circuit in a video reproducing apparatus. More particularly, the present invention relates to a communication between the memory and a microcomputer (i.e., a microcomputer) even when only standby power is supplied without operating power supplied to the memory. An I 2 C bus control circuit in a video reproducing apparatus.
    In general, an image display device employed as an image reproducing apparatus is classified into a direct view type image display device and a projection type image display device according to its display method. A direct view type image display device composed of a CRT (Cathode Ray Tube) or the like has a high image quality. Although it is good, there is a limitation in providing a large screen due to the disadvantage that the larger the screen, the larger the weight and thickness and the higher the price. The projection type image display device composed of a liquid crystal display (LCD) is a large screen and thinner. Although it is possible to reduce the weight, the light loss due to the polarizing plate is large, and since the thin film transistors for driving the liquid crystal display are formed for each pixel, there is a limit to increase the aperture ratio (light transmission area) and the problem of low light efficiency. have.
    The prior art will be described with reference to FIG. 1.
    A plurality of slaves (10,11,12, ---) and their slaves (10,11,12, ---) are included in the I 2 C bus, which consists of a data transmission line (SDA) and a clock transmission line (SCK). The microcomputer 1 for controlling the microcomputer 1 is connected, and the microcomputer 1 applies various control signals to the slaves 10, 11, 12, --- via the I 2 C bus. the slave (10,11,12, ---), the microcomputer (1), to mediate the I 2 C bus by receiving a signal reporting the status to be applied is applied through the I 2 C bus and said slave from the (10, Bi-directional communication between 11,12, --- is possible.
    On the other hand, in the above structure, the microcomputer 1 maintains an operating state (LIVE state) based on standby power (STAND-BY VOLTAGE) supplied from a power supply unit (not shown). (12, ---) is the operating state only when the operating power is supplied from the power supply unit, so when the power is turned off while the AC plug of the video player is plugged in, only the microcomputer 1 maintains the operating state. The slaves 10, 11, 12,-are in an operating state when the power is turned on and the operating power is supplied.
    However, if the power is turned off when the memory 10 is a memory storing state setting data for the video reproducing apparatus in the above case, the operation power is not applied to the memory 10 because the operating power is not applied. State, the microcomputer 1 reads out the state setting data stored in the memory 10 when the power is turned on, and the state for the video reproducing apparatus is based on the state setting data. Perform control.
    On the other hand, since the memory 10 maintains its operating state only when the power is turned on, communication between the microcomputer 1 and the memory 10 is not only possible when the standby power is supplied, but also the power of the video reproducing apparatus. Since the microcomputer 1 reads the state setting data stored in the memory 10 every time it is turned on, the microcomputer 1 writes the memory 10 to the memory 10 when the video player is frequently turned on and off. There has been a problem that a large amount of power is consumed to read the set state setting data.
    Accordingly, the present invention has been made in view of the above-described circumstances, and the video reproducing apparatus enables communication between the memory and the microcomputer (i.e., the microcomputer) even when only the standby power ST is supplied while the operating power is not supplied to the memory. Its purpose is to provide an I 2 C bus control circuit in.
    According to an embodiment of the present invention for realizing the above object, a plurality of slaves and a microcomputer for controlling the slaves in the I 2 C bus consisting of a data transmission line (SDA) and a clock transmission line (SCK) An image reproducing apparatus connected to the microcomputer and the slave to transmit / receive various data signals and clock signals through the I 2 C bus, wherein an standby power is supplied to the I 2 C bus between the microcomputer and a specific slave. Is operated to enable bidirectional communication between the micom and a specific slave, and when an operating power is supplied, an I 2 C bus between the micom and the slave operates to enable bidirectional communication between the micom and the slave. An I 2 C bus control circuit in an image reproducing apparatus further comprising a buffer control unit is provided.
    According to the present invention having the above-described configuration, the communication between the microcomputer and the memory becomes possible because the microcomputer and the memory are kept in the operating state when the standby power is supplied.
    1 is a diagram showing the configuration of an I 2 C bus in a conventional video reproducing apparatus;
    2 is a view showing the configuration of an I 2 C bus control circuit in a video reproducing apparatus according to an embodiment of the present invention;
    3 is a diagram showing an example of a circuit configuration of a buffer control unit shown in FIG. 2;
    4 is a view showing signal waveforms in the buffer control unit;
    5 is a signal waveform diagram of an I 2 C bus control circuit in an image reproducing apparatus according to an embodiment of the present invention.
    Explanation of symbols on the main parts of the drawings
    1: microcomputer, 10: memory
    11: Slave 1 12: Slave 2
    20: buffer control unit.
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    2 is a diagram illustrating a configuration of an I 2 C bus control circuit in an image reproducing apparatus according to an embodiment of the present invention, wherein reference numeral 1 denotes a default setting or operation control of other devices in a circuit system. As a microcomputer that performs a controlling function, in the present invention, when the standby power ST is supplied, the microcomputer 1 reads out the state setting data stored in the memory 10 and utilizes the default value.
    Then, when the operating power is turned on, the microcomputer 1 delivers the state setting data read from the memory 10 to each slave, and delivers the state setting data set by the user to each slave. do.
    When the operation power is turned off, the microcomputer 1 and the memory 10 maintain the operating state. At this time, the microcomputer 1 stores various data held in the memory 10. The memory 10 preserves data even when the operating power is turned off.
    In FIG. 1, reference numeral 20 denotes a buffer BUFFER when the operating power (+ 5V) and the standby power (+ 5V) are normally supplied to the I 2 C bus line, but only the standby power (+ 5V). a buffer controller which when a slave 1 11 and the second slave (12) to separate with the I 2 C bus to operate only the I 2 C bus between the microprocessor 1 and the memory 10 is supplied.
    Meanwhile, as shown in FIG. 3, the buffer control unit 20 has a resistor R5, a resistor R3, and a resistor R4 connected in parallel to an operation power supply terminal, and the other end of the resistor R5 is a resistor R6. The base terminal of the transistor Q1 is connected to the base terminal of the transistor Q1, and the collector terminal of the transistor Q1 is connected to the other end of the resistor R3. The other end of the resistor R5 is connected to the base terminal of the transistor Q2, and the collector terminal of the transistor Q2 is connected to one end of the resistor R4.
    In addition, resistors R1 and R2 are connected in parallel to the standby power supply terminal, the other end of the resistor R1 is connected to the emitter terminal of the transistor Q1, and the other end of the resistor R2 is connected to the transistor ( It is connected to the emitter terminal of Q2).
    In the circuit constituting the buffer control unit 20, a data transfer line SDA is connected to the emitter terminal of the transistor Q1, and a clock transfer line SCL is connected to the emitter terminal of the transistor Q2. The data transmission line SDA1 is connected to the collector terminal of the transistor Q1, and the clock transmission line SCL1 is connected to the collector terminal of the transistor Q2.
    Next, the operation of the I 2 C bus control circuit in the video reproducing apparatus according to the embodiment of the present invention having the above-described configuration will be described in detail.
    First, when standby power (+ 5V) is supplied to the buffer controller 20, power is supplied to the data transmission line SDA through the resistor R1 and the clock transmission is performed through the resistor R2. As power is supplied to the line SCL, the I 2 C bus between the microcomputer 1 and the memory 10 operates to enable bidirectional communication between the microcomputer 1 and the memory 10.
    In this state, when the user turns on the corresponding image reproducing apparatus and the operating power (+ 5V) is supplied to the buffer control unit 20, the base of the transistor Q1 is mediated through the resistor R5 and the resistor R6. As the power is applied to the terminal and the power is applied to the base terminal of the transistor Q2 through the resistor R5, the transistor Q1 and the transistor Q2 become conductive.
    Accordingly, the data transfer line SDA1 is connected to the data transfer line SDA through the transistor Q1 and simultaneously connected to the clock transfer line SCL to the microcomputer 1 and the memory 10. And two-way communication between the slaves 1 and 2 (11 and 12).
    Meanwhile, the operation of the buffer control unit 20 will be described in more detail with reference to the signal waveform diagram of the buffer control unit 20 shown in FIG. 4.
    As shown in FIG. 4 (a), the microcomputer 1 and the memory 10 are supplied with standby power (+ 5V) and operating power (+ 5V) as shown in FIG. 4 (b). As shown in FIGS. 4 (c) and 4 (d), the operation power is supplied through the data transmission line SDA between the first and second clock transmission lines SCL between the microcomputer 1 and the memory 10. It can be seen that the I 2 C bus including the data transmission line SDA and the clock transmission line SCK operates normally in an area in which only standby power is supplied and not standby power.
    In addition, when the operating power is supplied, the data transmitted through the data transmission line SDA and the clock transmission line SCK is transferred to the data transmission line SDA1 as shown in FIGS. 4E and 4F. ) And the I 2 C bus between the microcomputer 1, the memory 10, and the slaves 1, 2 (11, 12) as the microcomputer 1 is transmitted to the clock transmission line SCK1. The bidirectional communication between the memory 10 and the slaves 1, 2 (11, 12) is possible.
    Accordingly, the memory 10 is shown in FIG. 5 in a state where standby power (+ 5V) is supplied as shown in FIG. 5 (a) and operating power (+ 5V) is supplied as shown in FIG. 5 (b). As shown in (c), the I 2 C bus between the microcomputers 1 operates normally in a section 'a' to which standby power is supplied, thereby enabling bidirectional communication with the microcomputer 1, and the slave 1, 2 (11, 12) enables the I 2 C bus between the microcomputers 1 to operate normally in the 'b' section where the operating power is supplied, thereby enabling bidirectional communication with the microcomputer 1.
    As described above, according to the I 2 C bus control circuit in the image reproducing apparatus according to the exemplary embodiment of the present invention, even when the standby power (+ 5V) is supplied, bidirectional communication between the microcomputer and the memory enables data transmission. may, as well as the operation power (+ 5V) is the state in which the supply becomes possible for two-way communication with any slave connected to the I 2 C bus, the microprocessor can control the mode slaves are connected to the I 2 C bus, Will be.
    In addition, unlike the conventional method of reading the state setting data stored in the memory every time the image reproducing apparatus is turned on and performing the state control on the image reproducing apparatus while the state setting data is retained, the micom always reads the memory. The state setting data stored in the memory can be changed while the state setting data stored in the memory can be changed, thereby reducing power consumption.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] A plurality of slaves (10, 11, 12, ---) and a microcomputer (1) for controlling the slaves are connected to an I 2 C bus formed of a data transmission line (SDA) and a clock transmission line (SCK). In the video reproducing apparatus in which the microcomputer (1) and the slave (10, 11, 12,-) can transmit and receive various data signals and clock signals through the I 2 C bus,
    When standby power is supplied, the I 2 C bus between the microcomputer 1 and a specific slave operates to enable bidirectional communication between the microcomputer 1 and a specific slave, and when the operating power is supplied, the microcomputer 10 operates. A buffer control unit configured to enable bi-directional communication between the microcomputer and the slaves 10, 11, 12, --- by operating an I 2 C bus between the slave and the slaves 10, 11, 12, --- I 2 C bus control circuit in the video reproducing apparatus, characterized in that it further comprises 20).
    [2" claim-type="Currently amended] 2. The I 2 C bus control circuit according to claim 1, wherein the specific slave is a memory (10) storing state setting data for the corresponding video reproducing apparatus.
    [3" claim-type="Currently amended] The first and second switching devices Q1 and Q2 of claim 1, wherein the buffer control unit 20 is turned on / off by the operation power supply. Is turned off, the first current path for operating the I 2 C bus between the microcomputer 1 and the memory 2 based on a standby power source, and the first and second switching elements Q1 and Q2 are turned on. The second current path for operating the I 2 C bus between the microcomputer 1, the memory 2, and the slaves 11 and 12 based on an operating power source. I 2 C bus control circuit.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-12|Application filed by 배순훈, 대우전자 주식회사
    1996-12-12|Priority to KR1019960064792A
    1998-09-15|Publication of KR19980046450A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960064792A|KR19980046450A|1996-12-12|1996-12-12|I2C bus control circuit in video playback device|
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