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    • 专利摘要:
    The application relates to an integrated circuit with SRAM memory and provided with several superposed levels of transistors, the integrated circuit comprising SRAM cells provided with a first transistor and a second transistor belonging to a higher level of transistors and each having a double- gate composed of an upper electrode and a lower electrode arranged on either side of a semiconductor layer (110), a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor .
    公开号:FR3079966A1
    申请号:FR1853115
    申请日:2018-04-10
    公开日:2019-10-11
    发明作者:Francois Andrieu；Remy Berthelon；Bastien Giraud
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics Crolles 2 SAS；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    3D SRAM CIRCUIT WITH IMPROVED DOUBLE-GRID TRANSISTORS DESCRIPTION
    TECHNICAL AREA AND PRIOR ART
    The present invention relates to the field of SRAM type memories (SRAM for “Static Random Access Memory”), and relates more particularly to that of integrated circuits with transistors distributed over several levels and provided with a device SRAM memory.
    In general, in the field of microelectronics, it is continuously sought to increase the density of transistors.
    For this, a solution consists in distributing the transistors on several levels of semiconductor layers arranged one above the other.
    Such devices thus generally comprise a lower level provided with a first semiconductor layer from which transistors are formed and at least one upper level provided with at least a second semiconductor layer from which transistors are formed, the first and second semiconductor layers being superimposed and separated from each other by at least one insulating layer.
    We are looking to create a new SRAM memory device with improved electrical performance while limiting the size.
    STATEMENT OF THE INVENTION
    According to one embodiment, the present invention relates to an integrated circuit with SRAM memory provided with several superimposed levels of electronic components comprising:
    - a lower level provided with one or more electronic components, formed in and on at least one first semiconductor layer,
    - an upper level comprising transistors having respective channel regions formed in at least a second semiconductor layer disposed above the first semiconductor layer, the integrated circuit comprising a memory device formed by a plurality of memory cells SRAM, the memory device comprising a first transistor and a second transistor belonging to said upper level and each having a double gate composed of an upper electrode formed on the second semiconductor layer and a lower electrode arranged between the second semi layer -conductive and the first semiconductor layer, the lower gate electrode of the first transistor being connected or coupled to the lower gate electrode of the second transistor, the lower gate electrode of the first transistor and the lower gate electrode of the second transistor being connected or coupled to a line c polarization wave.
    Such an arrangement of the lower grid electrodes makes it possible to improve the electrical performance of the memory device while limiting the space requirement.
    The electronic components of the lower level can be transistors or another type of electronic component.
    According to a possible configuration of the circuit, the lower electrodes form a common lower gate electrode coupled or connected to the conductive bias line disposed above the first and second transistor through at least one via conductor.
    Advantageously, according to another configuration, the electrodes of the lower gates are separate and coupled or connected to said conductive bias line, in particular by means of conductive vias. This can further reduce the density of interconnects in the upper stage which typically already has a high density of interconnects.
    The first transistor and the second transistor may be transistors of separate SRAM cells of the same memory plane, and in particular transistors of different cells of the same row (horizontal row) or of the same column (vertical row) of cells.
    As a variant, the first transistor and the second transistor can be transistors of the same SRAM cell.
    A particular embodiment of this variant provides that the first transistor and the second transistor are access transistors of the same SRAM cell.
    In this case, the upper gate electrode of the first transistor and the upper gate electrode of the second transistor can be connected or coupled to the same word line. The conductive line of polarization can then be an additional conductive line of polarization distinct from said word line.
    This additional polarization conducting line can in particular be provided to make it possible to improve performance during read and / or write accesses to the SRAM cell.
    An SRAM cell is typically formed in addition to other transistors, in particular load transistors and conduction transistors, forming inverters producing a flip-flop. Advantageously, the charge and conduction transistors can also each be provided with a double gate composed of an electrode called “upper gate” or “front gate” arranged on the second semiconductor layer and another electrode called "Lower grid" or "rear grid" arranged between the second semiconductor layer and the first semiconductor layer.
    A particular embodiment provides that the additional conductive bias line fulfills a function of write assistance line. Thus, in this case, provision is typically made for applying to this additional conductive line of polarization a potential given during write operations performed on the cell and a potential different from said given potential during read operations performed on said cell SRAM as well as when the SRAM cell is in the retention phase of the stored logical information.
    The load transistors can also have a lower gate electrode coupled or connected to the polarization conductive line, in particular when the latter fulfills the function of assistance in writing.
    Another particular embodiment provides that the additional conductive bias line fulfills a function of assistance line for accessing an SRAM cell. In this case, provision is typically made to apply to this additional polarization conductive line a potential given during write and / or read operations performed on said SRAM cell and a potential different from said given potential when said SRAM cell is in the retention phase of the stored logical information.
    Another particular embodiment provides that the additional bias conductive line fulfills a writing aid function and is coupled or connected to the lower gate electrode of each of the charge transistors. Thus, in this case, provision is typically made to apply to this additional conductive bias line a potential given during write operations on said SRAM cell and a potential different from said given potential during read operations performed on said cell SRAM and / or during retention phases of said SRAM cell.
    Another particular embodiment provides that the conduction transistors have a lower gate electrode coupled or connected to the additional bias conductor line. In this case, advantageously, the charge transistors have a lower gate electrode coupled or connected to an additional conductive bias line.
    According to another particular embodiment in which the first transistor and the second transistor are respectively a first access transistor coupled or connected to a first storage node of an SRAM cell and a second access transistor coupled or connected to a second storage node of this SRAM cell, the SRAM cell can also be provided with a first charge transistor and a second charge transistor each having a double gate, a lower gate electrode of the second charge transistor and the first access transistor being coupled or connected to a first bit line, a lower gate electrode of the first load transistor and the second access transistor being coupled or connected to a second bit line.
    The SRAM cell can also be provided with a first conduction transistor and a second conduction transistor, each having a double gate, the lower gate electrode of the second conduction transistor being coupled or connected to the first bit line. , the lower gate electrode of the first conduction transistor being coupled to or connected to a second bit line.
    According to another particular embodiment in which the first transistor and the second transistor are conduction transistors of the same SRAM cell, the conductive bias line can fulfill a reading assistance function. Thus, in this case, provision is typically made to apply a potential given during read operations performed on said SRAM cell and a potential different from said given potential during write operations performed on said SRAM cell or when the cell is in a phase of information retention.
    According to another particular embodiment in which the first transistor and the second transistor are load transistors of the same SRAM cell, the conductive bias line can fulfill a writing assistance function. Thus, in this case, provision is typically made for applying a potential given during write operations and retention phase and a potential different from said given potential during read operations performed on said same SRAM cell.
    Alternatively, the conductive bias line may be a word line to which the upper gate electrode and the lower gate electrode of each of the access transistors is coupled or connected as well as the lower gate electrode of each load transistors.
    According to another aspect, an embodiment of the integrated circuit in which the first transistor and the second transistor are conduction or load transistors, respectively of a first memory cell and of a second memory cell of the same row of memory cells, said conductive bias line may be a first bit line.
    In this case, a complementary bit line can be connected or coupled to a lower gate electrode of another conduction or load transistor of the first cell. This complementary bit line can also be connected or coupled to another lower gate electrode of another charge or conduction transistor of another cell in the same row as the first cell.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of examples of embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which:
    - Figure 1, used to illustrate an example of diagram of static random access memory cell 6T integrated into a 3D circuit, with access transistors provided with an additional gate electrode connected to an additional conductive assistance line. writing,
    - Figure 2A, serves to illustrate an example of configuration of rear gate electrode common to upper level transistors of a circuit having several superposed levels of transistors, the rear gate electrode being connected to an additional conductive line polarization,
    FIG. 2B illustrates another configuration example of rear gate electrodes of upper level transistors of a circuit provided with several superposed levels of transistors, the rear gate electrodes being connected to an additional conductive bias line,
    FIG. 2C is used to illustrate an example of configuration of gate electrodes of a double gate transistor in a 3D circuit,
    FIG. 3 gives a particular example of arrangement of the transistors of a higher level and belonging to in SRAM cells implemented according to an embodiment of the present invention,
    FIG. 4 is used to illustrate an example of a SRAM memory cell diagram with access and double-gate charge transistors and having a gate electrode controlled by the same conductive line,
    FIG. 5 is used to illustrate another example of arrangement of the transistors of SRAM cells,
    - Figure 6, used to illustrate a variant cell arrangement
    SRAM
    - Figure 7, serves to illustrate an example of a particular configuration of SRAM cell in which the access transistors are double-gate and provided with a gate electrode controlled by a conductive line activated during read or write accesses of the cell,
    FIG. 8 is used to illustrate an example of a particular configuration of an SRAM cell in which the conduction transistors are double-gate and provided with a gate electrode controlled by a conducting line activated during read accesses of the cell,
    - Figure 9, serves to illustrate an example of a particular configuration of SRAM cell in which the load transistors are double-gate and provided with a gate electrode controlled by a conductive line activated during write accesses and when the cell is in the retention phase,
    FIG. 10 serves to illustrate an example of a particular configuration of an SRAM cell in which the access and conduction transistors are double-gate and provided with a rear gate electrode controlled by the same conductive line,
    FIG. 11 is used to illustrate a variant of the arrangement of FIG. 10 in which the charge transistors are with double gate and have common or connected rear gate electrodes,
    - Figure 12, serves to illustrate an example of a particular configuration of SRAM cell in which the access and conduction transistors are double-gate and provided with common back gate electrodes or connected together and controlled by the same line conductive,
    - Figure 13, serves to illustrate an example of a particular configuration of SRAM cell in which the access and load transistors are double-gate and provided with common back gate electrodes or connected together and controlled by the same line word,
    FIG. 14 is used to illustrate an example of a particular configuration of an SRAM cell with double-gate charge transistors and provided with rear gate electrodes connected respectively to a first bit line and to a second bit line,
    - Figure 15, serves to illustrate a variant of the arrangement of Figure 14 in which the conduction transistors are also double-gate and provided with back gate electrodes connected respectively to a first bit line and to a second bit line,
    Identical, similar or equivalent parts of the different figures have the same reference numerals so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    An example of an arrangement of an SRAM memory cell 2 capable of being integrated into a circuit as implemented according to an embodiment of the present invention is illustrated in FIG. 1.
    The cell 2 shown in FIG. 1 is provided with two storage nodes T and F, provided for keeping a first logical information, and a logical information complementary to the first information. The maintenance of the logical information in the nodes T, F is ensured by transistors forming inverters looped on themselves.
    In this example, cell 2 is of the type commonly called “6T” and thus formed of 6 transistors, the two inverters being typically produced by two load transistors TL T and TL F , in this example PMOS transistors commonly called “pull up ”and two conduction transistors TD T and TD F in this example NMOS type transistors and typically called“ pull down ”. The inverters are supplied by a supply potential VDD.
    Access to the storage nodes T and F is achieved by means of two access transistors TA ' T and TA' F connected respectively to so-called bit lines BL T and BL f generally shared by the SRAM cells of a same column of cells from a matrix of cells similar to the one illustrated.
    Access to the storage nodes T and F is controlled by a word line WL generally shared by one or more SRAM cells of the same row of cells in the matrix. The access transistors TA ' T and TA' F are thus provided to allow access or block access to the first node T and to the second node F respectively.
    Cell 2 comprises double-gate transistors which are integrated in an upper level of the integrated circuit provided with several superimposed levels of transistors, the double gate being formed by an upper gate electrode also called “front gate” and by a lower gate electrode also called “back gate” distributed on either side of a semiconductor layer in which the channel regions of these double-gate transistors are provided.
    In the particular embodiment illustrated in FIG. 1, these are the access transistors TA ' T , TA' F which are provided with a double gate. A gate electrode of the first access transistor TA ' T and a gate electrode of the second access transistor TA' F are also connected to each other and to the same word line WL.
    A lower gate electrode of the first access transistor TA ' T and a lower gate electrode of the second access transistor TA' F are connected to each other and to the same conductive area. This conductive area is in the form of a conductive line or connected to a conductive bias line. In the particular example illustrated in FIG. 1, the conductive line is an additional bias line fulfilling a so-called “writing assistance” function WLA. This WLA write assistance line is typically activated only during write operations performed on cell 2. Thus, an activation signal is applied to this WLA line during write operations performed on cell cell 2 while during read operations no signal or a different signal is applied to this WLA line. The simultaneous activation of the word line WL and the writing assistance line WLA during writing operations makes the access transistors TA ' T , TA' F more conductive than they are used during read operations for which only the word line WL is activated.
    A cell 2 as illustrated in FIG. 1 has an improved writing margin and a writing current compared to a cell 6T of conventional arrangement and devoid of writing assistance line. For example, for a potential of the order of IV applied to the WLA writing assistance line, the writing current can be increased by around 35%.
    A particular embodiment provides for connecting the lower gate electrode of each of the access transistors TA ' T and TA' F to the additional bias line, here of WLA writing assistance.
    For this, the access transistors TA ' T and TA' F can have an arrangement for example such as that of the transistors T 2i , T 22 illustrated in FIG. 2A or such as that illustrated in FIG. 2B.
    The device illustrated in these figures is formed from a substrate comprising a first Ni level provided with at least one first surface semiconductor layer 12 in which channel regions of transistors of the first Ni level are provided. The substrate may be of the semiconductor on insulator type, in particular a SOI (“Silicon On Insulator” or “silicon on insulator”) substrate, advantageously according to a totally deserted semiconductor on insulator technology also called FDSOI (for "Fully Depleted Silicon On Insulator"), In this case, the first surface semiconductor layer 12 is placed on an insulating layer 11 commonly known as BOX (for "Burried Oxide", in other words "buried oxide"), itself resting on a semiconductor support layer 10.
    In the example illustrated, a transistor Tu of the first level Ni is covered with at least one insulating layer 13, for example made of silicon oxide.
    The circuit is provided with at least a second level N 2 of one or more transistors arranged on the first level Ni and the respective channel regions of which extend in at least one second semiconductor layer 120 (not visible on the sectional view of Figure 2A).
    The second level N 2 comprises transistors T 2i , T 22 , with a double gate formed by an upper gate electrode 37 located on the second semiconductor layer and a lower electrode 35 located under the second semi-conductive layer conductive, in other words between the second semiconductor layer and the first semiconductor layer 12.
    The lower gate electrode 35 is typically separated from the second semiconductor layer by a dielectric layer 34. This dielectric layer 34 has a composition and a thickness provided to allow electrostatic coupling also called capacitive coupling between the gate electrode. lower 35 and the second semiconductor layer. Thus, the channel regions of the transistors T 2 i, T 22 / are in this example also controlled from below, respectively by means of electrodes of lower gates.
    In the example of arrangement illustrated in FIG. 2A, the double-gate transistors T 2 i, T 22 , share a common lower electrode 35 located under the semiconductor layer in which their channel regions are provided. The common lower electrode 35 can be connected to a conductive bias line 44 located on the second level N 2 of transistors. The connection between the lower electrode 35 and the conductive line 44 is typically implemented by means of a vertical or substantially vertical conductive element 42 which passes through the dielectric layer 34 and of the type commonly called "via".
    The conductive line 44 can for example fulfill the function of WLA write assistance line described previously in connection with FIG. 1. In this case, the activation signal of the WLA line is routed by the higher level N 2 above the transistors T 2 i, T 22 and can be applied under the transistors T 2i , T 22 by means of the lower electrode 35.
    In the alternative embodiment illustrated in FIG. 2B, the double-gate transistors T 2 i, T 22 have respective lower electrodes 35a, 35b connected to each other by means of a structure provided with a conductive line 54 of polarization located under the second level N 2 of transistors, and in particular under the lower electrodes 35a, 35b. The conductive polarization line 54 can for example fulfill the function of additional WLA writing assistance line mentioned above or be connected to the additional WLA writing assistance line. The connection between the lower electrodes 35a, 35b and the conductive line 54 is typically implemented by means of vertical conductive elements 52 or "vias".
    A particular embodiment provides an SRAM cell in which the charge and / or conduction transistors have an arrangement for example such as that of transistor T 23 illustrated in FIG. 2C.
    This transistor T 23 belongs to the second level N 2 and has a channel region which extends in the second semiconductor layer 120. The transistor T 23 comprises a double gate formed by an upper gate electrode 37 located on the second semiconductor layer 120 and a lower gate electrode 135 located between the second semiconductor layer 120 and the first semiconductor layer 12 of the first level Ni of transistors. The first semiconductor layer 12 and the second semiconductor layer have an arrangement similar to that described above in connection with FIGS. 2A-2B and are this time visible in the sectional view of FIG. 2C.
    FIG. 3 gives an example of arrangement of the upper level N 2 of a 3D circuit provided with SRAM memory cells according to the configuration of FIG. 1 and provided with access transistors having a configuration of the type of that of FIG. 2B with lower electrodes 35a, 35b connected to a writing assistance line (not shown in this figure).
    In this example, it is further provided that transistors TA ' F , TA 2 of cells 2i, 2 2 different, but belonging to the same row (or row) of cells have a common lower gate electrode 35b or gate electrodes lower interconnected via the same conductive area.
    In an SRAM cell of an integrated circuit, other transistors can also be provided with a double gate, and in particular certain transistors forming the inverters, in other words the flip-flop of an SRAM cell.
    In the embodiment illustrated in FIG. 4, the SRAM cell differs from that described previously in connection with FIG. 1, in that it is this time provided with a charge transistor TL ′ T and another charge transistor TL ' F each having an additional gate electrode connected to the WLA write assistance line. This additional grid electrode can be a lower grid electrode 35 or
    35a, or 35b of arrangement of the type described above in connection with FIG. 2A or with FIG. 2B.
    In such a configuration, during write operations, while increasing the conduction of the access transistors TA ' T , TA' F , here of the NMOS type, decreasing that of the load transistors TL ' T , TL ' F generally of opposite type, in this example of PMOS type.
    Compared to a conventional 6T memory cell configuration without writing assistance line, this increases the writing margin as well as the writing current. This can also increase the write margin compared to a memory cell configuration as illustrated in the figure.
    1.
    FIG. 5 gives an example of an arrangement of the upper level N 2 of a 3D circuit provided with SRAM memory cells according to the configuration of FIG. 4 and provided with access transistor TA ' T (respectively TA' F ) sharing an electrode rear gate 35a (resp. 35b) common with a charge transistor TL ' T , (respectively TL' F ) according to a configuration of the type of that of FIG. 2B, the lower electrodes 35a, 35b being connected to a line of writing assistance (not shown) located under the semiconductor layer 120 in which extend channels of transistors of the upper level N 2 and which is capable of being divided into active zones or separate semiconductor islands.
    A variant of SRAM cell in which the access transistors as well as all the transistors forming the inverters are provided with a double gate can also be provided.
    FIG. 6 gives a particular arrangement of an SRAM cell formed in the upper level N 2 of an integrated circuit with charge transistors TL ' T , TL' F having a double gate, with a lower gate electrode 135 according to a configuration of the type for example that of FIG. 2C, and which is common to the load transistors TL ' T , TL' F and connected to a bias line PUA situated under the lower gate electrode 135 and above the level lower Ni.
    The load transistors TD ' T and TD F , and the access transistors TA' T and TA'f have a double gate according to a configuration which can be for example of the type of that of FIG. 2C. Each access transistor TA ' T or TA' F is provided with a back gate electrode 135 connected to a PGA bias line located under the bottom gate electrode 135 and above the lower level Ni. Each conduction transistor TD ' T or TD' F is provided with a back gate electrode 135 connected to a PDA bias line located under the bottom gate electrode 135 and above the lower level Ni.
    Each type of transistor, of access TA ' T , TA' F or of conduction TD ' T , TD' f , or of load TL ' T , TL' F is controlled by means of a polarization line PGA, PDA, PUA which is specific to it, which allows independent control between the different types of transistors in the same cell.
    In the embodiment of FIG. 7, the charge transistors TL T and TL F , as well as the conduction transistors TD T and TD F thus each have an upper gate electrode and a lower gate electrode.
    In this example, the double-gate access transistors TA ' T , TA' F have lower gate electrodes connected to each other and to the same AAL line called "cell access assistance" line. The access transistors TA ' T , TA' F can have an arrangement for example as illustrated in FIG. 2B or in FIG. 2A.
    The AAL access assistance line is typically activated during write and read operations performed on the cell. Thus, a given potential is applied for example corresponding to a logic level '1' on this line AAL during write and write operations performed on the cell. When the cell is in the retention phase, a different potential, for example corresponding to a logic level '0' is applied to this AAL line. This reduces read and write access times while limiting leakage currents.
    Another variant of SRAM cell is illustrated in FIG. 8, with access transistors TA T , TA F and double-gate charge transistors TL T , TL F , this time conduction transistors TD ' T and TD ' F having gate electrodes connected to each other and to the same RAL line called "reading assistance". The conduction transistors TD ' T and TD' F can thus have an arrangement of the type described previously in connection with FIG. 2A or with FIG. 2B, with electrodes of lower gates 35 or 35a, 35b connected to each other and to a conductive line 44 or 54, which in this example forms the so-called RAL line for reading assistance.
    The RAL reading assistance line is typically activated during reading operations performed on the cell. A potential is applied for example corresponding to a logical level '1' on this RAL line during the read operations, while when the cell is in retention mode or when a write is implemented, a different potential, for example corresponding to a logic level '0' is applied to this RAL line. This can reduce read access times and reduce the static noise margin, while reducing static consumption.
    According to another variant of SRAM cell, illustrated in FIG. 9, it is possible to provide access transistors TA T , TA F and conduction transistors TD T , TD f with double gate, this time with load transistors TL ' T and TL' F having gate electrodes connected to each other and polarized by means of the same line WA 'called "writing aid".
    We apply on this line WA 'a potential corresponding for example at logic level' 1 'during write operations or in retention mode, while when a read operation is performed on the cell, a different potential, for example corresponding to a logical level '0' is applied to this line WA 'of writing assistance. This can reduce write access times and the noise margin during write operations, while reducing the static noise margin.
    The load transistors TL ' T and TL' F can then have an arrangement of the type described previously in connection with FIG. 2A or with FIG. 2B, with electrodes of lower gates 35 connected together and to a conductive line 44 or 54, which in this example forms the writing aid line WA 'or is connected to such a writing aid line WA'.
    In the embodiment of FIG. 10, the conduction transistors TD ' T and TD' F and the access transistors TA ' T and TA' F each have a double-gate structure and are provided with gate electrodes connected to each other and to the same RA '"reading aid" line. Typically it is the electrodes of the lower gates which are connected to each other. The conductive line 44 or 54 as illustrated in FIG. 2A or 2B, can fulfill the function of line RA 'of reading aid or be connected to such a line of reading aid RA'.
    In particular, provision may be made to apply to this line RA ′ a given potential corresponding for example to logic level 1 1 ′ during reading operations, while when the cell is in retention mode, a different potential, for example corresponding to a logic level '0' is applied to this line RA 'of reading aid. This can reduce read access times as well as leakage currents in retention mode. When such a way of polarizing the line RA ′ is applied to unselected cells, in other words cells belonging to a line of cells for which the word line has not been activated or of a line of cells for which the access transistors have not been turned on, this improves the lpg_on / lpg_off ratio. This ratio can be defined as the ratio between the current in the on state of the access transistors and the current in the off state of the access transistors.
    According to an improved variant of the exemplary embodiment of FIG. 10, one can also provide, as in FIG. 11, double-gate charge transistors TL ′ T and TL ′ F having this time electrodes, in particular their electrodes of lower grids, connected to each other and to an additional conductive line SUL.
    A polarization of the lines RA 'and SUL so, for example, that a potential corresponding to logic level T is applied to the reading aid line RA' and a different potential corresponding to logic level '0' on the additional line can be expected. In this case, the reading operations are improved, in particular in terms of reading time and noise margin.
    Reverse polarization of the lines RA 'and SUL so, for example, that a potential corresponding to logic level' 0 'is applied to the reading aid line RA' and a potential corresponding to logic level T to the additional line may be scheduled for the retention phase. This reduces leakage currents during the retention phase. When such a way of polarizing the line RA ′ is applied to unselected cells, this makes it possible to improve the ratio lpg_on / lpg_off.
    The lines RA 'and SUL can be polarized so that a potential corresponding to logic level' 1 'is applied to the reading aid line RA' and a potential corresponding to logic level T to the additional line SUL during 'write operations. This helps reduce write times and noise margin during write operations.
    In another example of SRAM cell illustrated in FIG. 12, it is this time the charge transistors TL ' T and TL' F and the access transistors TA T , TA F which have gate electrodes connected to each other and to the same line WA 'for writing assistance.
    In particular, provision can be made to apply a potential corresponding to this line WA ', for example at logic level' 1 'during writing operations, in order to reduce the time required for writing and to improve the noise margin. during write operations.
    An alternative embodiment illustrated in FIG. 13, this time provides conduction transistors TD T and TD F with double gate and access transistors TAi T and TAi F also having double gate structures but each also having electrodes of lower and upper grid connected together and to a word line WL. The charge transistors TL ' T and TL' F also each have a double gate structure with, among their two gate electrodes, a gate electrode connected to the word line WL. Such an arrangement can, as for the previous one, make it possible to reduce the writing time and to reduce the margin to writing noise while having a limited bulk.
    In the embodiment illustrated in FIG. 14, the access transistors TA't and TA ' F and the conduction transistors TD T and TD F have an arrangement similar to that in the cell described previously in connection with the figure 7.
    The charge transistors TL 2T and TL 2F have a double gate structure and a particular arrangement of their additional gate electrode. A first charge transistor has a gate electrode, typically its lower gate electrode, connected to the second bit line BLF.
    Insofar as the second bit line BLF is typically shared by cells of the same given row of cells, in particular a vertical row or a column, one or more other charge transistors belonging respectively to other cells of this same row of cells as that shown can also be provided with a rear gate electrode connected to that of the TL 2T transistor according to a configuration of the type of that of FIG. 2B.
    A second load transistor has a gate electrode, typically its lower gate electrode connected to the first bit line BLT. Likewise, the first bit line BLT being typically shared by other cells of the given row of cells to which the cell shown in FIG. 14 belongs, at least one other load transistor belonging to another cell can also be provided a back gate electrode connected to that of the transistor TL 2T according to a configuration of the type of that of FIG. 2B.
    The access transistors TA ' T and TA' F in this example have a lower gate electrode connected to an assistance line for access AAL to which a potential corresponding to a logic level '1' is applied for example write and read operations performed on the cell. Such a cell can have a reduced read and write time as well as a reduced write noise margin.
    During retention phases, a different potential, in this example corresponding to a logic level '0', is typically applied to this AAL line. The leakage currents are thus improved, in particular when the bit lines BLT and BLF are preloaded at a logic level Ί ', corresponding for example to a voltage level equal to VDD.
    An alternative embodiment of the example described above is given in FIG. 15.
    For this variant, the conduction transistors TD 2T and TD 2F have a double-gate structure and a particular arrangement of their additional gate electrode, similar to that implemented for the charge transistors TL 2T and
    Tl_2F- A first conduction transistor TD 2T comprises a gate electrode, typically its lower gate electrode connected to the second bit line BLF, just like the lower gate electrode of the transistor of the first charge transistor TL 2T . A second conduction transistor TD 2F comprises a gate electrode, typically its lower gate electrode connected to the first bit line BLT.
    The lower gate electrode of the second load transistor TL 2F is also connected to the first bit line BLT. Such a configuration makes it possible, compared to the previous one, to improve the performance of the read and write operations.
    权利要求:
    Claims (18)
    [1" id="c-fr-0001]
    1. Integrated circuit with SRAM memory and provided with several levels (Ni, N 2 ) superimposed on components comprising:
    - a lower level (Ni) provided with one or more electronic components (Tu) formed in and on at least one first semiconductor layer (12),
    - an upper level (N 2 ), arranged on the lower level, comprising transistors having respective channel regions formed in at least a second semiconductor layer disposed above the first semiconductor layer, the integrated circuit with SRAM memory comprising an SRAM memory device formed of a plurality of memory cells, the SRAM memory device comprising a first transistor (T 2i ) and a second transistor (T 22 ) belonging to said upper level and each having a double gate composed of an electrode upper (37) formed on the second semiconductor layer and a lower electrode (35, 35a, 35b, 135) arranged between the second semiconductor layer and the first semiconductor layer, the lower gate electrode of the first transistor being coupled to or connected to the lower gate electrode of the second transistor, the lower gate electrode of the first transistor and the lower gate electrode of the second transistor being coupled or connected to a conductive bias line (44, 54, WLA).
    [2" id="c-fr-0002]
    2. Integrated circuit according to claim 1, in which the first transistor (T 2i ) and the second transistor (T 22 ) belong to the same memory cell of the SRAM memory device or respectively belonging to a cell and to another cell of a same row of memory cells.
    [3" id="c-fr-0003]
    3. Integrated circuit according to one of claims 1 or 2, wherein the first transistor (T 2i ) and the second transistor (T 22 ) have respective separate lower gate electrodes (35a, 35b) and connected or coupled to said polarization conductive line (54), in particular by means of conductive vias (52).
    [4" id="c-fr-0004]
    4. Integrated circuit according to one of claims 1 or 2, in which the first transistor (T 2 i) and the second transistor (T 22 ) have a common lower gate electrode (35) connected or coupled to the conductive line ( 44) additional bias disposed above the first and second transistor through at least one via conductor (42).
    [5" id="c-fr-0005]
    5. Integrated circuit according to one of claims 1 to 4, in which the first transistor and the second transistor are access transistors (TA ' T , TA' F ) of the same SRAM cell, the gate electrode upper of the first transistor and the upper gate electrode of the second transistor being connected or coupled to the same word line (WL), the conductive line (44, 54) of polarization being an additional conductive line (WLA, AAL, RA ' , AA ′) of polarization distinct from said word line (WL).
    [6" id="c-fr-0006]
    6. The integrated circuit as claimed in claim 5, in which the SRAM cell is further formed by other transistors (TL ' T , TL' F , TD ' T , TD' F , TL t , TL f , TD t , TD f ) producing a rocker and each having a double grid composed of an electrode arranged on the second semiconductor layer and another electrode arranged between the second semiconductor layer and the first semiconductor layer.
    [7" id="c-fr-0007]
    7. The integrated circuit according to claim 5, in which the additional conductive bias line is a write assistance line (WLA) to which a given potential is applied during write operations on said SRAM cell and a potential different from said given potential is applied during read operations performed on said SRAM cell and during retention phases of said SRAM cell.
    [8" id="c-fr-0008]
    8. The integrated circuit as claimed in claim 5, in which the additional conductive bias line is a cell access assistance line (AAL) to which a given potential is applied during write and read operations. performed on said SRAM cell and a potential different from said given potential is applied during retention phases of said SRAM cell.
    [9" id="c-fr-0009]
    9. Integrated circuit according to claim 5 or 6, in which the charge transistors (TL ' T , TL' F ) have a gate electrode connected or coupled to the additional conductive line (44, 54, WLA) of polarization.
    [10" id="c-fr-0010]
    10. Integrated circuit according to claim 9, in which the additional conductive bias line is a write aid line (WA ′) to which a given potential is applied during write operations on said SRAM cell and a potential different from said given potential is applied during read operations performed on said SRAM cell or is a write assistance line (WLA) to which a given potential is applied during write operations on said cell SRAM and a potential different from said given potential is applied during read operations performed on said SRAM cell and during retention phases of said SRAM cell.
    [11" id="c-fr-0011]
    11. Integrated circuit according to claim 5 or 6, in which the conduction transistors (TL ' T , TL' F ) have a lower gate electrode connected or coupled to the additional conductive line (RA ') of polarization.
    [12" id="c-fr-0012]
    12. The integrated circuit as claimed in claim 11, in which the charge transistors (TD ' T , TD' F ) have a gate electrode connected or coupled to an additional polarization conductive line (SUL).
    [13" id="c-fr-0013]
    13. Integrated circuit according to one of claims 1 to 4, in which the first transistor and the second transistor are access transistors (TA ' T , TA' F ) of an SRAM cell and in which the conductive line ( 44, 54, WLA) of polarization is a word line, the upper gate electrode and the lower gate electrode of each of the access transistors being coupled or connected to this word line (WL), said line of word being connected or coupled to a gate electrode of a first double-gate charge transistor (TL ' T ) of said SRAM cell as well as to a gate electrode of a second charge transistor (TL' T ) with double grid of said SRAM cell.
    [14" id="c-fr-0014]
    14. The integrated circuit as claimed in claim 5, in which the first transistor and the second transistor are respectively a first access transistor (TA't) connected or coupled to a first storage node (T) of an SRAM cell and a second access transistor (TA ' F ) connected or coupled to a second storage node (F) of the SRAM cell and in which the SRAM cell is provided with a first load transistor (TL 2T ) and a second charge transistor (Tl_ 2F ) each having a double gate, the lower gate electrode of the second charge transistor (Tl_ 2F ) being coupled or connected to a first bit line (BLT), the lower gate electrode of the first load transistor (TL 2T ) being coupled to or connected to a second bit line (BLF).
    [15" id="c-fr-0015]
    15. The integrated circuit as claimed in claim 14, in which the SRAM cell is provided with a first conduction transistor (TD 2T ) and a second conduction transistor (TD 2F ) each having a double gate, a gate electrode. of the second conduction transistor (TD 2F ) being connected or coupled to the first bit line (BLT), a gate electrode of the first conduction transistor (TD 2T ) being connected or coupled to a second bit line (BLF).
    [16" id="c-fr-0016]
    16. Integrated circuit according to one of claims 1 to 4, in which the first transistor and the second transistor are conduction transistors (TD ' T , TD' F ) of the same SRAM cell, the conductive line (44, 54, WLA) of polarization being in particular a reading assistance line (RAL) to which a given potential is applied during read operations performed on said same SRAM cell and a potential different from said given potential during operations of writing performed on said SRAM cell or when the cell is in a phase of information retention.
    [17" id="c-fr-0017]
    17. Integrated circuit according to one of claims 1 to 4, in which the first transistor and the second transistor are load transistors (TL ' T , TL' F ) of the same SRAM cell, the conductive line (44, 54, WLA) of polarization being in particular a writing aid line (WA ′) to which a given potential is applied during writing operations on said same SRAM cell and of retention phase and a different potential of said potential given during read operations performed on said SRAM cell.
    5
    [0018]
    18. The integrated circuit as claimed in claim 2, in which the first transistor (T 2 i) and the second transistor (T 22 ) are conduction (TD 2F ) or load (Tl_ 2F ) transistors, respectively of a first cell. memory and a second memory cell of the same row of memory cells, the conductive bias line (54) being a first bit line (BLT), a second bit line (BLF) 10 complementary to the first line of bit being connected or coupled to a lower gate electrode of another conduction (TD 2T ) or load (TI_ 2T ) transistor of said first cell.
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    同族专利:
    公开号 | 公开日
    US10741565B2|2020-08-11|
    US20190312039A1|2019-10-10|
    FR3079966B1|2022-01-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20070183185A1|2006-01-11|2007-08-09|The Regents Of The University Of California|Finfet-based sram with feedback|
    US20100328990A1|2006-12-07|2010-12-30|Nat.Inst. Of Adv Industrial Science And Technology|Sram device|
    US20080175039A1|2006-12-28|2008-07-24|Commissariat A L'energie Atomique|Memory cell provided with dual-gate transistors, with independent asymmetric gates|
    EP2131396A1|2008-06-02|2009-12-09|Commissariat a L'Energie Atomique|SRAM memory cell with integrated transistors on several levels, with dynamically adjustable voltage threshold VT|
    US20110242881A1|2010-03-30|2011-10-06|National Institute Of Advanced Industrial Science And Technology|Sram device|
    US20120113708A1|2010-11-04|2012-05-10|Industry-Academic Cooperation Foundation, Yonsei University|Stable SRAM Bitcell Design Utilizing Independent Gate Finfet|FR3103963A1|2019-12-03|2021-06-04|Commissariat A L'energie Atomique Et Aux Energies Alternatives|3D MEMORY DEVICE INCLUDING SRAM-TYPE MEMORY CELLS WITH ADJUSTABLE REAR POLARIZATION|US6643159B2|2002-04-02|2003-11-04|Hewlett-Packard Development Company, L.P.|Cubic memory array|
    TWI456739B|2011-12-13|2014-10-11|Nat Univ Tsing Hua|Control scheme for 3d memory ic|
    US8964452B2|2012-12-26|2015-02-24|Applied Micro Circuits Corporation|Programmable resistance-modulated write assist for a memory device|
    US9875789B2|2013-11-22|2018-01-23|Taiwan Semiconductor Manufacturing Company, Ltd.|3D structure for advanced SRAM design to avoid half-selected issue|FR3083912A1|2018-07-13|2020-01-17|Commissariat A L'energie Atomique Et Aux Energies Alternatives|SRAM / ROM RECONFIGURABLE BY SUBSTRATE POLARIZATION|
    法律状态:
    2019-04-29| PLFP| Fee payment|Year of fee payment: 2 |
    2019-10-11| PLSC| Publication of the preliminary search report|Effective date: 20191011 |
    2020-04-30| PLFP| Fee payment|Year of fee payment: 3 |
    2021-04-29| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1853115A|FR3079966B1|2018-04-10|2018-04-10|SRAM 3D CIRCUIT WITH IMPROVED LAYOUT DUAL-GRID TRANSISTORS|
    FR1853115|2018-04-10|FR1853115A| FR3079966B1|2018-04-10|2018-04-10|SRAM 3D CIRCUIT WITH IMPROVED LAYOUT DUAL-GRID TRANSISTORS|
    US16/379,476| US10741565B2|2018-04-10|2019-04-09|3D SRAM circuit with double gate transistors with improved layout|
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