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    • 专利摘要:
    The present invention describes an insulation layer structure for a semiconductor product. The insulation layer structure comprises a device substrate (1), a support substrate (2) and a thin film layer (3). The device substrate (1) and the support substrate (2) are silicon wafers. The thin film layer (s) (3) is / are provided on the device substrate (1) and / or the support substrate (2), and is / are one of a layer silicon dioxide, a silicon oxynitride layer, a silicon nitride layer, a polysilicon layer, and an amorphous silicon layer. The device substrate (1) and the support substrate (2) are bonded together through the thin film layer (3) provided on at least one of the device substrate (1) and the support substrate ( 2) to form an integral multilayer SOI structure. The present invention also further relates to a method of preparing the insulation layer structure for the semiconductor product. The special insulation layer structure formed by the present invention is diverse, solves the problems of high spontaneous heating of an existing SOI device, high deformation of an existing SOI structure caused by high temperature annealing, poor characteristic radio frequency and the like, and has a relatively higher predictable economic and social value. Figure to be published with the abstract: Fig. 1
    公开号:FR3077424A1
    申请号:FR1872569
    申请日:2018-12-10
    公开日:2019-08-02
    发明作者:Wenlin GAO；Xiang Li；Qingchao Liu
    申请人:Shenyang Silicon Tech Co Ltd；
    IPC主号:
    专利说明:

    The present invention relates to the preparation of semiconductor materials, and more particularly an insulating layer structure for a semiconductor product and a method of preparing the insulating layer structure which is formed using of a bonding process.
    BACKGROUND [0004] In the prior art, a device provided with an SOI (silicon on insulator) structure can reduce the junction capacity and the leakage current, increase a switching speed and reduce energy consumption. significantly due to the unique superiority of the SOI structure, and, thus, allow operation at high speed and low energy consumption. Therefore, the use of this device is much better than a conventional silicon device and circuit. Today, the application of the SOI device has gradually moved from the military, aerospace and industrial sector to that of data processing, communications, consumer electronics and the like. SOI technology, which is the next generation silicon-based integrated circuit technology, is widely used not only in most areas of microelectronics, but also in other fields such as optoelectronics and MEMS. So SOI technology is the subject of much research because of the above advantages and its many applications, and is known as "21st century silicon integrated circuit technology".
    SOI materials also have the following limitations, although they can be applied to high speed integrated circuit products with low power consumption.
    (1) There are still limitations with regard to the application of high temperature and high power devices (such as cars, household appliances, electrical installations, and the like). One of the main problems is the spontaneous heating effect, namely a failure of the device due to overheating caused by poorer thermal conductivity of the insulating layer of SiO2 (its thermal conductivity is only about 1 % of that of silicon).
    (2) A conventional SOI device exhibits poor circuit performance at a high frequency due to the existence of a stray capacitance and a leakage current, and it is difficult to obtain better RF performance. even if the resistivity of a substrate is increased.
    It is therefore desirable to obtain an insulating layer structure intended for a semiconductor product and a process for preparing the insulating layer structure which have an excellent technical effect.
    SUMMARY An object of the present invention is to provide an insulating layer structure for a semiconductor product and a process for preparing the insulating layer structure which have excellent technical effects.
    An insulation layer structure intended for a semiconductor product and provided by the present invention comprises a device substrate 1, a support substrate 2 and a thin film layer 3. The device substrate 1 and the support substrate 2 are wafers of silicon; and the thin film layer (s) 3 is / are provided on the device substrate 1 and / or the support substrate 2, and is / are one of a layer of silicon dioxide, a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon and a layer of amorphous silicon.
    The device substrate 1 and the support substrate 2 are bonded together through the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 in order to form a structure Integral multilayer SOI (silicon on insulator).
    The preferable protective content of the insulating layer structure intended for a semiconductor product is as follows.
    At least one intermediate layer 4 is provided on the thin film layer 3 on at least one of the device substrate 1 and the support substrate 2, and is one of the following or a combination of the following: a layer of silicon dioxide, a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon and a layer of amorphous silicon.
    An intermediate layer 4 is provided on the thin film layer 3 on at least one of the device substrate 1 and the support substrate 2; and the device substrate 1 and the support substrate 2 are bonded together through the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 and the intermediate layer 4 on the thin film layer 3 in order to form an integral multilayer SOI structure.
    The insulation layer structure for the semiconductor product meets one or a combination of the following requirements:
    First, the resistivity of a silicon wafer used as device substrate 1 and / or support substrate 2 is between 0.1 and 10,000 ohm.cm;
    Then, when the thin film layer 3 or the intermediate layer 4 is a layer of silicon dioxide, the thickness of the layer of silicon dioxide is between 0 and 5 μm, and the thickness of the structures of subsequent layers, comprising the silicon oxynitride layer, the silicon nitride layer, the polysilicon layer and the amorphous silicon layer, as a thin film layer 3 or an intermediate layer 4, is between 0.01 and 10 pm;
    Then, the diameter of the silicon wafer is 150 mm, or 200 mm, or
    300 mm; and then, the thin film layer (s) 3 provided on the device substrate 1 and / or the support substrate 2 and the intermediate layer (s) 4 provided ( s) on the thin film layer (s) are bonded together to form the integral multilayer SOI structure.
    The present invention also relates to a process for preparing an insulating layer structure for a semiconductor product. The requirements of the preparation process are as follows.
    First, a device substrate 1 and a support substrate 2 of an insulating layer structure for a semiconductor product are prepared; and a thin film layer 3 on at least one of the surfaces of the device substrate 1 and the support substrate 2 is prepared. The device substrate 1 and the support substrate 2 are wafers of silicon. The thin film layer (s) 3 is / are provided on the device substrate 1 and / or the support substrate 2, and is / are one of a layer of silicon dioxide, d a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon and a layer of amorphous silicon.
    Then, the device substrate 1 and the support substrate 2 are bonded together by means of the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 in order to form an integral multi-layer SOI structure.
    The process for preparing the insulating layer structure for the semiconductor product is characterized in that, before the bonding, at least one intermediate layer 4 is provided beforehand on the thin film layer 3 of at least one of the device substrate 1 and the support substrate 2, and is one of or a combination of the following: the layer of silicon dioxide, the layer of silicon oxynitride, the layer of nitride silicon, the polysilicon layer and the amorphous silicon layer.
    The bond meets the following requirements: the thin film layer and the intermediate layer 4 are successively arranged on a base body of at least one of the device substrate 1 and the support substrate 2 before the bond; and the other of the device substrate 1 and the support substrate 2 to be bonded is a base body without the thin film layer 3 or the intermediate layer 4, or a body provided with only the thin film layer 3, or a base body provided with the thin film layer 3 and the intermediate layer 4.
    The process for preparing the insulating layer structure for the semiconductor product is characterized in that the device substrate 1 and the support substrate 2 selected, before bonding, are slices of silicon which have a resistivity of 0.1 to 10,000 ohm.cm;
    When the thin film layer 3 is the silicon dioxide layer, the thickness of the silicon dioxide layer is between 0 and 5 μm;
    When at least one intermediate layer 4 is provided on the layer (s) of thin film (3) on the device substrate 1 and / or the support substrate 2, the thickness of the intermediate layer 4 is between 0.01 and 10 pm; and the intermediate layer 4 is one of the silicon oxynitride layer, the silicon nitride layer, the polysilicon layer and the amorphous silicon layer.
    The diameter of the silicon wafer is 150 mm, or 200 mm, or 300 mm.
    / The layer (s) of thin film 3 provided (s) on the device substrate 1 and / or the support substrate 2 and / / the intermediate layer (s) 4 provided (s) on the thin film layer (s) are bonded together to form the integral multilayer SOI structure.
    The preferable steps of the process for preparing the insulating layer structure for the semiconductor product are as follows.
    First, a silicon wafer which has any crystalline phase, any type of conductivity, a diameter of 150 mm, or 200 mm or 300 mm, and a resistivity of 0, 1 to 10,000 ohm.cm is chosen as device substrate 1 and support substrate 2.
    Then, the device substrate 1 and the support substrate 2 are successively cleaned by ultrasound using a mixed solution of HE, H2SO4 and H2O2 and deionized water in order to remove a layer d natural oxide and contaminants on the surfaces of the device substrate 1 and the support substrate 2 in order to obtain the silicon wafers with high quality surfaces; the device substrate 1 and the support substrate 2 are wrung out after cleaning; and the device substrate 1 and / or the support substrate 2 to be developed with a thin film layer 3 is / are placed in a reaction chamber of a plasma activated chemical vapor deposition apparatus or chemical vapor deposition under reduced pressure.
    Next, an in situ plasma cleaning is carried out on the device substrate 1 and / or the support substrate 2 with a hydrogen flow rate of 20 to 200 sccm and a cleaning time of 5 to 20 minutes.
    Then, the thin film layer 3 is deposited on a base body of at least one of the device substrate 1 and the support substrate 2, and, according to the different materials of the thin film layers 3, the gases used for the deposition are oxygen, hydrogen, nitrogen, silane, nitrous oxide, hydrogen and argon with flow rates from 0 to 20 sim, 0 at 10 sim, 0 to 1 sim, 0 to 25 sccm, 0 to 20 sccm, 0 to 50 sccm and 0 to 60 sccm, respectively; a deposition pressure is between 0 and 10 Pa; the thickness of deposition of a layer of silicon dioxide as a thin film layer 3 is between 0 and 5 μηι; and a deposition thickness of a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon or a layer of amorphous silicon as a thin film layer 3 is between 0 and 10 μηι.
    Next, an in situ plasma cleaning is carried out on the device substrate 1 and / or the support substrate 2 with a hydrogen flow rate of 20 to 200 sccm and a cleaning time of 5 to 20 minutes.
    Next, an intermediate layer 4 is deposited on the surface of the thin film layer 3 on the device substrate 1 and / or the support substrate 2, and, according to the different materials of the intermediate layer 4, the gases used for the deposition are silane, nitrous oxide, hydrogen, argon and ammonia with flow rates from 0 to 25 sccm, 2 to 20 sccm, 10 to 50 sccm, 30 to 60 sccm, respectively; a deposition pressure is between 5 and 10 Pa; and the thickness of the deposit is between 0.01 and 10 μηι.
    Then, a hydrogen plasma etching is carried out once the intermediate layer 4, as a thin film layer, has been deposited with a hydrogen flow rate of 30 to 120 sccm and an etching time of 0.5 to 10 minutes.
    Then, another intermediate layer 4 is deposited on the surface of the intermediate layer 4 prepared in the above steps, and this step is repeated n (n> 0) times until the total deposit thickness meets a requirement.
    Then, the device substrate 1 and / or the support substrate 2 treated (s) by the above steps is / are treated (s) in a manner I or II in order to obtain an SOI material with a buried layer of special insulation, way I comprising: making a vacuum connection at low temperature on the device substrate 1 and the support substrate 2, and grinding and polishing a bonded sheet obtained in above step in order to obtain the SOI material having a greater silicon thickness between
    1.5 and 250 μηι; and Method II comprises: injecting hydrogen ions into the substrate of device 1 with an injection depth of 100 to 1500 nm, making a vacuum connection at low temperature on the substrate of device 1 and the support substrate 2 in order to obtain a bonded sheet, carrying out a low-temperature annealing process on the sheet bonded at an annealing temperature of 150 to 300 ° C., performing a separation by microwave or laser on this sheet bonded in order to form a SOI structure material, and carrying out a chemical-mechanical planarization process on the SOI structure in order to form the SOI material having an upper layer thickness of between 0.02 and 1.5 pm.
    Microwave separation has the following requirements: a microwave power is between 1 and 4 KW; a microwave duration is between 2 and 5 minutes; and a microwave temperature is between 70 and 400 ° C. Laser separation has the following requirements: an infrared laser is adopted; a laser point size is between 0.5 and 2 mm; a laser power is between 100 mw and 100 w; a heating time is between 10 and 30 s; a laser scanning path is located along the diameter direction of the silicon wafer; the number of scans of the silicon wafer is between 8 and 28; a laser beam scans the silicon wafer at an angle of incidence between 45 ° and 135 °; and the surface temperature of the silicon wafer increases rapidly by laser heating to allow the hydrogen ions in the silicon wafer to accumulate in order to achieve separation.
    The process for preparing the insulating layer structure for the semiconductor product meets one or a combination of the following requirements. First, during the deposition process of the intermediate layer 4, a hydrogen plasma etching step is added, so that a fragile Si-N bond is broken while filling a pendant bond of silicon with the through an etching effect of the hydrogen plasma, and that a new stable Si-N bond is reformed. At the same time, a surface activity of the thin film is increased and the nucleation energy is reduced in order to prepare a high quality silicon nitride film as an intermediate layer 4.
    Then, a change in deformation of the SOI caused by the difference in thermal expansion coefficients after the annealing at high temperature is reduced by adjusting the thicknesses of the film of silicon oxynitride and of the film of silicon nitride in the intermediate layer. 4.
    During the laser separation process, the laser acts on the surface of the silicon wafer in order to heat the surface of the silicon wafer, so that the injected H + is accumulated in gas molecules which fill the cracks so to form hydrogen microbubbles; and, with the continuous accumulation of hydrogen molecules, a layer of hydrogen is finally peeled off in order to carry out the separation, and, thus, an SOI structure is formed. Compared with microwave separation technology, laser heating separation has the following advantages: a crystal defect and metal inclusion caused by the hydrogen ion injection layer are eliminated, a material d Surface absorption is eliminated, and the surface roughness is improved.
    The above additional instructions are as follows.
    The problem of limiting the SOI material of the prior art can be resolved by modifying the structure of the insulation layer.
    (1) The SiO2 film in the insulation layer is replaced by a silicon nitride film or a silicon oxynitride film. The silicon nitride film or the silicon oxynitride film can become a material capable of replacing SiO2 as a buried insulating layer, and can allow industrialization due to its high thermal conductivity, its excellent insulating capacity. , its high dielectric constant, its high heat dissipation coefficient, its compact structure, its stable chemical properties, its simple preparation process, its high process compatibility, its low cost, and the like.
    (2) The SiO2 layer of the insulation layer is replaced by a polysilicon film or an amorphous silicon film which can effectively combine with silicon oxide in order to effectively suppress the parasitic surface conductance of the silicon substrate, limit the change in capacitance and reduce the power of the harmonics generated. Thus, the radiofrequency characteristic is improved.
    (3) A silicon nitride film deposited by the conventional LPCVD / PECVD process contains many defects such as dislocations, surface states and pending bonds, which considerably reduces the quality of the nitride film of silicon. During the deposition process of the intermediate layer 4, a hydrogen plasma etching step is added, so that a fragile Si-N bond is broken while filling a pendant bond of silicon by means of an effect. etching the hydrogen plasma, and that a new stable Si-N bond is reformed. At the same time, a surface activity of the thin film is increased and the nucleation energy is reduced in order to prepare a high quality silicon nitride film as an intermediate layer 4. In addition, a change in SOI deformation caused by the difference in coefficients of thermal expansion after high temperature annealing is reduced by adjusting the thicknesses of the silicon oxynitride film and the silicon nitride film in the intermediate layer 4.
    (4) The laser separation process mentioned in the present invention is advantageous for the preparation of high quality SOI. The laser acts on the surface of the silicon wafer in order to heat the surface of the silicon wafer, so that the injected H + is accumulated in gas molecules which fill the cracks in order to form microbubbles of hydrogen; and, with the continuous accumulation of hydrogen molecules, a layer of hydrogen is finally peeled off in order to carry out the separation, and, thus, an SOI structure is formed. Compared with microwave separation technology, laser heating separation has the following advantages: a crystal defect and metal inclusion caused by the hydrogen ion injection layer are eliminated, a material d Surface absorption is eliminated, and the surface roughness is improved.
    The present invention adopts a bonding process to form a special insulation layer structure which is diverse and meets the design requirements of MEMS, radio frequency and optical devices.
    The structure prepared by the present invention is diverse. More particularly, the diversity of the structure is illustrated in the embodiments. This diversity of the multilayer structure can be in accordance with the design requirements of the various devices and has great technical advantages.
    The present invention has the following advantages.
    1. The method provided by the present invention forms the special insulation layer structure through the bonding process. In this structure, through the bonding process, a layer of silicon oxynitride, a layer of silicon nitride, a layer of silicon dioxide or a layer of polysilicon which is formed on the silicon wafer using of a process such as plasma activated chemical vapor deposition or chemical vapor deposition under reduced pressure is combined with a silicon wafer and a silicon dioxide wafer, a silicon oxynitride wafer, a wafer of silicon nitride, a wafer of polysilicon, or a layer of amorphous silicon to form a multilayer SOI structure.
    2. The structure formed by the method of the present invention is diverse and can meet the design requirements of different devices.
    3. One of the innovations of the technical solution of the present invention is that the layer of silicon nitride or the layer of silicon oxynitride is used to replace the layer of silicon dioxide as a layer of insulation, so that the problem of strong spontaneous heating of an existing SOI device which uses the silicon dioxide film as a buried layer of insulation is resolved.
    4. The method of the present invention also creatively uses polysilicon or amorphous silicon to replace silicon dioxide as an insulating layer material, so that the problem of poor radiofrequency characteristic of the device Existing SOI that uses the silicon dioxide film as the buried insulation layer be resolved.
    5. The process for preparing the insulation layer material used in the process of the present invention is simple, very compatible with other processes, and inexpensive.
    6. The insulation layer material used in the process of the present invention has a high selectivity and can serve as a barrier layer against thermal corrosion and acid corrosion.
    7. The SOI material which exhibits excellent thermal conductivity is prepared by the method of the present invention, so that the problems of strong spontaneous heating of an existing SOI device which uses the SiO2 film as a buried layer d he isolation and strong deformation of this SOI caused by high temperature annealing are resolved. At the same time, with the introduction of laser separation technology, the device layer density defects are reduced, so that the production yield and product quality are improved.
    In summary, the insulating layer structure provided by the present invention has a relatively higher predictable economic and social value.
    Brief Description of the Drawings [0064] Figure 1 is a schematic view of an insulating layer structure for a semiconductor product according to embodiment 1;
    Figure 2 is a schematic view of another insulating layer structure for the semiconductor product according to embodiment 2;
    Figure 3 is a schematic view of another insulating layer structure for the semiconductor product according to embodiment 3;
    Figure 4 is a schematic view of another insulating layer structure for the semiconductor product according to embodiment 4; and FIG. 5 is a schematic view of another structure of an insulating layer intended for the semiconductor product according to embodiment 5.
    Description of Embodiments Embodiment 1 An insulating layer structure for a semiconductor product comprises a device substrate 1, a support substrate 2 and a thin film layer 3. The device substrate 1 and support substrate 2 are wafers of silicon; and the thin film layer (s) 3 is / are provided on the device substrate 1 and / or the support substrate 2, and is / are one of a layer of silicon dioxide, a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon and a layer of amorphous silicon.
    The device substrate 1 and the support substrate 2 are bonded together by means of the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 in order to form a structure. Integral multilayer SOI (silicon on insulator).
    The insulation layer structure intended for the semiconductor product meets a combination of the following requirements:
    First, the resistivity of a silicon wafer used as device substrate 1 and / or support substrate 2 is between 0.1 and 10,000 ohm.cm;
    Then, when the thin film layer 3 or the intermediate layer 4 is a layer of silicon dioxide, the thickness of the layer of silicon dioxide is between 0 and 5 μm, and the thickness of the structures of subsequent layers, comprising a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon and a layer of amorphous silicon, as a thin film layer 3 or an intermediate layer 4, is between 0.01 and 10 qm;
    Then, the diameter of the silicon wafer is 150 mm, or 200 mm, or
    300 mm; and then, the thin film layer (s) 3 provided on the device substrate 1 and / or the support substrate 2 and the intermediate layer (s) 4 provided ( s) on the thin film layer (s) are bonded together to form an integral multilayer SOI structure.
    The present invention also relates to a process for preparing an insulating layer structure for a semiconductor product. The requirements of the preparation process are as follows.
    First, a device substrate 1 and a support substrate 2 of an insulating layer structure for a semiconductor product are prepared; and a thin film layer 3 is prepared on at least one of the surfaces of the device substrate 1 and the support substrate 2. The device substrate 1 and the support substrate 2 are silicon wafers. The thin film layer (s) 3 is / are provided on the device substrate 1 and / or the support substrate 2, and is / are one of a layer of silicon dioxide, d a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon and a layer of amorphous silicon.
    Then, the device substrate 1 and the support substrate 2 are bonded together by means of the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 in order to form an integral multi-layer SOI structure.
    At least one intermediate layer 4 is provided on the thin film layer 3 on at least one of the device substrate 1 and the support substrate 2 before bonding, and is one of or a combination of this. which follows: the layer of silicon dioxide, the layer of silicon oxynitride, the layer of silicon nitride, the layer of polysilicon and the layer of amorphous silicon.
    The bond meets the following requirements: the thin film layer and the intermediate layer 4 are successively arranged on a base body of at least one of the device substrate 1 and the support substrate 2 before the bond; and the other of the device substrate 1 and of the support substrate 2 to be bonded is a base body without the thin film layer 3 and the intermediate layer 4, or a body provided with only the thin film layer 3, or a base body provided with the thin film layer 3 and the intermediate layer 4.
    The device substrate 1 and the support substrate 2 selected, before the bonding, are silicon wafers which have a resistivity of 0.1 to 10,000 ohm.cm.
    When the thin film layer 3 is the silicon dioxide layer, the thickness of the silicon dioxide layer is between 0 and 5 μιη.
    When at least one intermediate layer 4 is provided on the thin film layer (s) (3) on the device substrate 1 and / or the support substrate 2, the thickness of the intermediate layer 4 is between 0.01 and 10 μιη; and the intermediate layer 4 is one of the silicon oxynitride layer, the silicon nitride layer, the polysilicon layer and the amorphous silicon layer.
    The diameter of the silicon wafer is 150 mm, or 200 mm, or 300 mm.
    The thin film layer (s) 3 provided on the device substrate 1 and / or the support substrate 2 and the intermediate layer (s) 4 provided on the thin film layer (s) are bonded together to form the integral multilayer SOI structure.
    The specific steps of the process for preparing the insulating layer structure for the semiconductor product are as follows.
    First of all, a silicon wafer which has any crystalline phase, any type of conductivity, a diameter of 150 mm, or 200 mm or 300 mm, and a resistivity of 0, 1 to 10,000 ohm.cm is chosen as device substrate 1 and support substrate 2.
    Then, the device substrate 1 and the support substrate 2 are successively cleaned by ultrasound using a mixed solution of HE, H2SO4 and H2O2 and deionized water in order to remove a layer d natural oxide and contaminants on the surfaces of the device substrate 1 and the support substrate 2 in order to obtain the silicon wafers with high quality surfaces; the device substrate 1 and the support substrate 2 are wrung out after cleaning; and the device substrate 1 and / or the support substrate 2 to be developed with a thin film layer 3 is / are placed in a reaction chamber of a plasma activated chemical vapor deposition apparatus or chemical vapor deposition under reduced pressure.
    Then, an in situ plasma cleaning is carried out on the device substrate 1 and / or the support substrate 2 with a hydrogen flow rate of 20 to 200 sccm and a cleaning time of 5 to 20 minutes.
    Next, the thin film layer 3 is deposited on a base body of at least one of the device substrate 1 and the support substrate 2, and, according to the different materials of the thin film layers 3, the gases used for the deposition are oxygen, hydrogen, nitrogen, silane, nitrous oxide, hydrogen and argon with flow rates from 0 to 20 sim, 0 at 10 sim, 0 to 1 sim, 0 to 25 sccm, 0 to 20 sccm, 0 to 50 sccm and 0 to 60 sccm, respectively; deposition pressure is between 0 and 10
    Pa; the deposition thickness of a layer of silicon dioxide as a thin film layer 3 is between 0 and 5 μm; and a deposition thickness of a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon or a layer of amorphous silicon as a thin film layer 3 is between 0 and 10 pm.
    Next, an in situ plasma cleaning is carried out on the device substrate 1 and / or the support substrate 2 with a hydrogen flow rate of 20 to 200 sccm and a cleaning time of 5 to 20 minutes.
    Next, an intermediate layer 4 is deposited on the surfaces of the thin film layer 3 on the device substrate 1 and / or the support substrate 2, and, according to the different materials of the intermediate layer 4, the gases used for the deposition are silane, nitrous oxide, hydrogen, argon and ammonia with flow rates from 5 to 25 sccm, from 2 to 20 sccm, from 10 to 50 sccm, from 30 to 60 sccm and 5 to 20 sccm, respectively; a deposition pressure is between 5 and 10 Pa; and the thickness of the deposit is between 0.01 and 10 μm.
    Then, hydrogen plasma etching is carried out once the intermediate layer 4, as a thin film layer, has been deposited with a hydrogen flow rate of 30 to 120 sccm and an etching time of 0.5 to 10 minutes.
    Next, another intermediate layer 4 is deposited on the surface of the intermediate layer 4 prepared in the above steps, and this step is repeated n (n> 0 and is an integer) times until the total deposit thickness is in accordance with a requirement.
    Then, the device substrate 1 and / or the support substrate 2 treated with the above steps is / are treated with manner I or II in order to obtain an SOI material with a buried layer of special insulation, way I comprising: making a vacuum connection at low temperature on the device substrate 1 and the support substrate 2, and grinding and polishing a bonded sheet obtained in above step in order to obtain the SOI material having a greater silicon thickness between
    1.5 and 250 pm.
    Method II comprises: injecting hydrogen ions into the device substrate 1 with an injection depth of 100 to 1500 nm, making a vacuum connection at low temperature on the substrate device 1 and the support substrate 2 in order to obtain a bonded sheet, performing a low temperature annealing process on the bonded sheet at an annealing temperature of 150 to 300 ° C, performing a separation by microwave or by laser on this sheet bonded to form a SOI structure material, and carrying out a chemical mechanical planarization process on the SOI structure in order to form the SOI material having a layer thickness greater than between 0 , 02 and 1.5 pm.
    Microwave separation has the following requirements: a microwave power is between 1 and 4 KW; a microwave duration is between 2 and 5 minutes; and a microwave temperature is between 70 and 400 ° C. Laser separation has the following requirements: an infrared laser is adopted; a laser point size is between 0.5 and 2 mm; a laser power is between 100 mw and 100 w; a heating time is between 10 and 30 s; a laser scanning path is located along the diameter direction of the silicon wafer; the number of scans of the silicon wafer is between 8 and 28; a laser beam scans the silicon wafer at an angle of incidence between 45 ° and 135 °; and the surface temperature of the silicon wafer increases rapidly by laser heating to allow the hydrogen ions in the silicon wafer to accumulate in order to achieve separation.
    The process for preparing the insulating layer structure for the semiconductor product meets a combination of the following requirements.
    First of all, during the deposition process of the intermediate layer 4, a hydrogen plasma etching step is added, so that a fragile Si-N bond is broken while filling a pendant bond of silicon through a hydrogen plasma etching effect, and that a new stable Si-N bond is reformed. At the same time, a surface activity of the thin film is increased and the nucleation energy is reduced in order to prepare a high quality silicon nitride film as an intermediate layer 4.
    Then, a change in SOI deformation caused by the difference in thermal expansion coefficients after high temperature annealing is reduced by adjusting the thicknesses of the silicon oxynitride film and the silicon nitride film in the intermediate layer. 4.
    During the laser separation process, the laser acts on the surface of the silicon wafer in order to heat the surface of the silicon wafer, so that the injected H + is accumulated in gas molecules which fill the cracks so to form hydrogen microbubbles; and, with the continuous accumulation of hydrogen molecules, a layer of hydrogen is finally peeled off in order to carry out the separation, and, thus, an SOI structure is formed. Compared with microwave separation technology, laser heating separation has the following advantages: a crystal defect and metal inclusion caused by the hydrogen ion injection layer are eliminated, a material d Surface absorption is eliminated, and the surface roughness is improved.
    The above additional instructions are as follows.
    The problem of limitations of the SOI material of the prior art can be resolved by modifying the structure of the insulation layer.
    (1) The film of SiO2 in the insulation layer is replaced by a film of silicon nitride or a film of silicon oxynitride. The silicon nitride film or a silicon oxynitride film can become a material capable of replacing SiO2 as a buried insulating layer, and can allow industrialization because of its high thermal conductivity, its excellent insulating capacity. , its high dielectric constant, its high heat dissipation coefficient, its compact structure, its stable chemical properties, its simple preparation process, its high process compatibility, its low cost, and the like.
    (2) The SiO2 layer of the insulation layer is replaced by a polysilicon film or an amorphous silicon film which can effectively combine with silicon oxide in order to effectively suppress the parasitic surface conductance of the silicon substrate, limit the change in capacitance and reduce the power of the harmonics generated. Thus, the radiofrequency characteristics are improved.
    (3) A silicon nitride film deposited using the conventional LPCVD / PECVD process contains many defects such as dislocations, surface states and dangling bonds, which considerably reduces the quality of the nitride film of silicon. During the deposition process of the intermediate layer 4 of the present embodiment, a step of etching with hydrogen plasma is added, so that a fragile Si-N bond is broken while filling a pendant bond of silicon with the through an etching effect of the hydrogen plasma, and that a new stable SiN bond is reformed. At the same time, a surface activity of the thin film is increased and the nucleation energy is reduced in order to prepare a high quality silicon nitride film as an intermediate layer 4. In addition, a change in SOI deformation caused by the difference in coefficients of thermal expansion after high temperature annealing is reduced by adjusting the thicknesses of the silicon oxynitride film and the silicon nitride film in the intermediate layer 4.
    (4) The laser separation process mentioned in this embodiment is advantageous for the preparation of high quality SOI. The laser acts on the surface of the silicon wafer in order to heat the surface of the silicon wafer, so that the injected H + is accumulated in gas molecules which fill the cracks in order to form microbubbles of hydrogen; and, with the continuous accumulation of hydrogen molecules, a layer of hydrogen is finally peeled off in order to carry out the separation, and, thus, an SOI structure is formed. Compared with microwave separation technology, laser heating separation has the following advantages: a crystal defect and metal inclusion caused by the hydrogen ion injection layer are eliminated, a material d Surface absorption is eliminated, and the surface roughness is improved.
    The present embodiment adopts a bonding process to form a special insulation layer structure which is diverse and meets the design requirements of MEMS, radio frequency and optical devices.
    The structure prepared by the present invention is diverse. More particularly, the diversity of the structure is illustrated in the embodiments. This diversity of the multilayer structure can comply with the design requirements of the various devices and has great technical advantages.
    The present embodiment has the following advantages.
    1. The method provided by this embodiment forms the special insulation layer structure through the bonding process. In this structure, through the bonding process, a layer of silicon oxynitride, a layer of silicon nitride, a layer of silicon dioxide, a layer of polysilicon or a layer of amorphous silicon which is formed on the wafer of silicon using a method such as plasma activated chemical vapor deposition or chemical vapor deposition under reduced pressure is combined with a silicon wafer, a silicon dioxide wafer, a silicon wafer silicon oxynitride, a wafer of silicon nitride, a wafer of polycrystalline silicon, or a layer of amorphous silicon to form a multilayer SOI structure.
    2. The structure formed by the method of this embodiment is diverse and can meet the design requirements of different devices.
    3. One of the innovations of the technical solution of the present embodiment is that the layer of silicon nitride or the layer of silicon oxynitride is used to replace the layer of silicon dioxide as a layer d insulation, so that the problem of strong spontaneous heating of an existing SOI device which uses the silicon dioxide film as a buried layer of insulation is solved.
    4. The method of this embodiment also creatively uses polysilicon or amorphous silicon to replace silicon dioxide as an insulating layer material, so that the problem of poor radio frequency characteristic of the existing SOI device that uses the silicon dioxide film as the buried insulation layer be resolved.
    5. The process for preparing the insulation layer material used in the process of this embodiment is simple, very compatible with other processes, and inexpensive.
    6. The insulation layer material used in the process of the present embodiment has a high selectivity and can serve as a barrier layer against thermal corrosion and acid corrosion.
    7. The SOI material which exhibits excellent thermal conductivity is prepared by the method of the present embodiment, so that the problems of strong spontaneous heating of an existing SOI device which uses the SiO 2 film as a buried layer isolation and strong deformation of SOI caused by high temperature annealing are resolved. At the same time, with the introduction of laser separation technology, the device layer density defects are reduced, so that the production yield and product quality are improved.
    In summary, the present embodiment has a relatively higher predictable economic and social value.
    Embodiment 2 [0121] The content of this embodiment is almost identical to that of embodiment 1, and the difference between them is as follows.
    The insulating layer structure for the semiconductor product is illustrated in FIG. 1. The insulating layer structure for the semiconductor product comprises a device substrate 1, a support substrate 2 and a thin film layer 3. The device substrate 1 and the support substrate 2 are silicon wafers. The thin film layer (s) 3 is / are provided on the device substrate 1 and / or the support substrate 2, and is / are a layer (s) of silicon dioxide.
    At least one intermediate layer 4 is provided on the thin film layer 3 on at least one of the device substrate 1 and the support substrate 2, and is one of the following: a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon and a layer of amorphous silicon.
    An intermediate layer 4 is provided on the thin film layer 3 on at least one of the device substrate 1 and the support substrate 2; and the device substrate 1 and the support substrate 2 are bonded together through the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 and the intermediate layer 4 on the thin film layer 3 in order to form an integral multilayer SOI structure.
    [0125] Embodiment 3 [0126] The content of this embodiment is almost identical to that of embodiment 1, and the difference between them is as follows.
    The insulating layer structure for the semiconductor product is illustrated in FIG. 2. The insulating layer structure for the semiconductor product comprises a device substrate 1, a support substrate 2 and a thin film layer 3. The device substrate 1 and the support substrate 2 are silicon wafers. The thin film layer (s) 3 is / are provided on the device substrate 1 and / or the support substrate 2, and is / are a layer (s) of silicon nitride. The device substrate 1 and the support substrate 2 are bonded together by means of the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 in order to form an integral multilayer SOI structure. (silicon on insulator).
    Embodiment 4 [0129] The content of this embodiment is almost identical to that of Embodiment 1, and the difference between them is as follows.
    The insulating layer structure for the semiconductor product is illustrated in FIG. 3. The insulating layer structure for the semiconductor product comprises a device substrate 1, a support substrate 2 and a thin film layer 3. The device substrate 1 and the support substrate 2 are silicon wafers. The thin film layer 3 is provided on the device substrate 1 and is a layer of silicon dioxide.
    At least one intermediate layer 4 is provided on the thin film layer 3 on at least one of the device substrate 1 and the support substrate 2, and is a layer of silicon nitride.
    An intermediate layer 4 is provided on the thin film layer 3 on at least one of the device substrate 1 and the support substrate 2; and the device substrate 1 and the support substrate 2 are bonded together through the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 and the intermediate layer 4 on the thin film layer 3 in order to form an integral multilayer SOI structure.
    Embodiment 5 [0134] The content of this embodiment is almost identical to that of embodiment 1, and the difference between them is as follows.
    The insulating layer structure for the semiconductor product is illustrated in FIG. 4. The insulating layer structure for the semiconductor product comprises a device substrate 1, a support substrate 2 and a thin film layer 3. The device substrate 1 and the support substrate 2 are silicon wafers. The thin film layer 3 is provided on the device substrate 1 and is a layer of silicon dioxide.
    At least one intermediate layer 4 is provided on the thin film layer 3 on at least one of the device substrate 1 and the support substrate 2, and is a layer of polysilicon.
    An intermediate layer 4 is provided on the thin film layer 3 on at least one of the device substrate 1 and the support substrate 2; and the device substrate 1 and the support substrate 2 are bonded together through the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 and the intermediate layer 4 on the thin film layer 3 in order to form an integral multilayer SOI structure.
    Embodiment 6 [0139] The content of the present embodiment is almost identical to that of the embodiment 1, and the difference between them is as follows.
    The insulating layer structure for the semiconductor product is illustrated in FIG. 5. The insulating layer structure for the semiconductor product comprises a device substrate 1, a support substrate 2 and a thin film layer 3. The device substrate 1 and the support substrate 2 are silicon wafers. The thin film layer 3 is provided on the device substrate 1 and is a layer of silicon oxynitride and a layer of composite thin film of silicon nitride.
    The device substrate 1 and the support substrate 2 are bonded together by means of the thin film layer 3 provided on at least one of the device substrate 1 and the support substrate 2 in order to form a structure. Integral multilayer SOI (silicon on insulator).
    权利要求:
    Claims (1)
    [1" id="c-fr-0001]
    claims
    An insulating layer structure for a semiconductor product, the layer structure comprising: a device substrate (1), a support substrate (2) and a thin film layer (3), the device substrate ( 1) and the support substrate (2) being wafers of silicon; the thin film layer (s) (3) is / are provided on the device substrate (1) and / or the support substrate (2), and is / are one of a layer silicon dioxide, a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon and a layer of amorphous silicon; and wherein the device substrate (1) and the support substrate (2) are bonded together through the thin film layer (3) provided on at least one of the device substrate (1) and the substrate support (2) to form an integral multilayer SOI structure.
    Insulation layer structure for the semiconductor product according to claim 1, wherein at least one intermediate layer (4) is provided on the thin film layer (3) of at least one of the device substrate ( 1) and the support substrate (2), and is one of the following or a combination of the following: the layer of silicon dioxide, the layer of silicon oxynitride, the layer of silicon nitride, the layer of polysilicon and the amorphous silicon layer; or in which an intermediate layer (4) is provided on the thin film layer (3) on at least one of the device substrate (1) and the support substrate (2); and the device substrate (1) and the support substrate (2) are bonded together through the thin film layer (3) provided on at least one of the device substrate (1) and the support substrate (2) and the intermediate layer (4) on the thin film layer (3) to form an integral multilayer SOI structure.
    An insulating layer structure for the semiconductor product according to claim 1 or 2, wherein the insulating layer structure meets one or a combination of the following requirements: first, the resistivity of a silicon wafer used as device substrate (1) and / or support substrate (2) is between 0.1 and 10,000 ohm.cm; then, when the thin film layer (3) or the intermediate layer (4) is a layer of silicon dioxide, the thickness of the layer of silicon dioxide is between 0 and 5 [Claim 4] [Claim 5] qm, and the thickness of the following layer structures, comprising the silicon oxynitride layer, the silicon nitride layer, the polysilicon layer and the amorphous silicon layer, as a thin film layer (3) or intermediate layer (4), is between 0.01 and 10 qm; then, the diameter of the silicon wafer is 150 mm, or 200 mm, or 300 mm; and then, the thin film layer (s) (3) provided on the device substrate (1) and / or the support substrate (2) and the intermediate layer (s) (4) on the thin film layer (s) are bonded together to form the integral multilayer SOI structure.
    Process for preparing an insulating layer structure intended for a semiconductor product, the process comprising:
    first, the preparation of a device substrate (1) and a support substrate (2) of the insulating layer structure for the semiconductor product, and the preparation of a film layer thin (3) on at least one of the surfaces of the device substrate (1) and the support substrate (2), wherein the device substrate (1) and the support substrate (2) are wafers of silicon , the thin film layer (s) (3) is / are provided (s) on the device substrate (1) and / or the support substrate (2), and is / are one of layer of silicon dioxide, a layer of silicon oxynitride, a layer of silicon nitride, a layer of polysilicon and a layer of amorphous silicon; and then bonding the device substrate (1) and the support substrate (2) through the thin film layer (3) provided on at least one of the device substrate (1) and the substrate support (2) in order to form an integral multilayer SOI structure.
    Method for preparing the insulating layer structure for the semiconductor product according to claim 4, in which, before bonding, at least one intermediate layer (4) is provided beforehand on the thin film layer (3) at least one of the device substrate (l) and the support substrate (2), and is one of or a combination of the following: the layer of silicon dioxide, the layer of oxynitride of silicon, the silicon nitride layer, the polysilicon layer and the amorphous silicon layer; and the bond meets the following requirements: the thin film layer and the intermediate layer (4) are successively arranged on a base body of at least one of the device substrate (1) and the support substrate (2) before bonding; and the other of the device substrate (1) and the support substrate (2) to be bonded is [Claim 6] [Claim 7] [Claim 8] a base body without the thin film layer (3) and the layer intermediate (4), or a body provided with only the thin film layer (3), or a base body provided with the thin film layer (3) and the intermediate layer (4).
    A method of preparing the insulating layer structure for the semiconductor product according to claim 4 or 5, wherein the device substrate (1) and the support substrate (2) selected, before bonding, are wafers silicon which have a resistivity of 0.1 to 10,000 ohm.cm; when the thin film layer (3) is the silicon dioxide layer, the thickness of the silicon dioxide layer is between 0 and 5 μιη; when at least one intermediate layer (4) is provided on the thin film layer (s) (3) on the device substrate (1) and / or the support substrate (2), the thickness of the intermediate layer (4) is between 0.01 and 10 µm; and the intermediate layer (4) is one of the silicon oxynitride layer, the silicon nitride layer, the polysilicon layer and the amorphous silicon layer.
    A method of preparing the insulating layer structure for the semiconductor product according to claim 6, wherein the diameter of the silicon wafer is 150 mm, or 200 mm, or 300 mm; and the thin film layer (s) (3) on the device substrate (1) and the support substrate (2) and the intermediate layer (s) (4) on the layer (s) (s) of thin film (3) are bonded together to form the integral multilayer SOI structure. A method of preparing the insulating layer structure for the semiconductor product according to claim 7, the method of preparing comprising the following steps: first, selecting a silicon wafer which has any crystalline phase, any type of conductivity, a diameter of 150 mm, or 200 mm or 300 mm, and a resistivity of 0.1 to 10,000 ohm.cm as device substrate (1) and support substrate ( 2); then successive ultrasonic cleaning of the device substrate (1) and the support substrate (2) using a mixed solution of HF, H 2 SO 4 and H 2 O 2 and deionized water in order to remove a layer of natural oxide and the contaminants on the surfaces of the device substrate (1) and of the support substrate (2) in order to obtain the silicon wafers with high quality surfaces, the device substrate (1) and support substrate (2) after cleaning, and placing the device substrate (1) and / or the support substrate (2) to be developed with a thin film layer (3) in a reaction chamber of a plasma activated chemical vapor deposition or chemical vapor deposition apparatus under reduced pressure; then, the plasma cleaning in situ on the device substrate (1) and / or the support substrate (2) with a hydrogen flow rate of 20 to 200 sccm and a cleaning time of 5 to 20 minutes; then depositing the thin film layer (3) on a base body of at least one of the device substrate (1) and the support substrate (2), in which, according to the different materials of the layers thin film (3), the gases used for the deposition are oxygen, hydrogen, nitrogen, silane, nitrous oxide, hydrogen and argon with flow rates from 0 to 20 sim, 0 to 10 sim, 0 to 1 sim, 0 to 25 sccm, 0 to 20 sccm, 0 to 50 sccm and 0 to 60 sccm, respectively, a deposition pressure between 0 and 10 Pa, a thickness of deposition of a layer of silicon dioxide as a thin film layer (3) of between 0 and 5 μm, and a thickness of deposition of a layer of silicon oxynitride, of a layer of nitride of silicon, a layer of polysilicon or a layer of amorphous silicon as a thin film layer (3) of between 0 and 10 qm; then, the plasma cleaning in situ on the device substrate (1) and / or the support substrate (2) with a hydrogen flow rate of 20 to 200 sccm and a cleaning time of 5 to 20 minutes; then the deposition of an intermediate layer (4) on the surfaces of the thin film layer (3) on the device substrate (1) and / or the support substrate (2), and, depending on the different materials the intermediate layer (4), the gases used for the deposition are silane, nitrous oxide, hydrogen, argon and ammonia with flow rates from 5 to 25 sccm, from 2 to 20 sccm, from 10 to 50 sccm, from 30 to 60 sccm and from 5 to 20 sccm, respectively, a deposition pressure between 5 and 10 Pa, and a deposition thickness between 0.01 and 10 qm; then, hydrogen plasma etching once the intermediate layer (4), as a thin film layer, has been deposited with a hydrogen flow rate of 30 to 120 sccm and an etching time of 0.5 10 minutes; then the deposition of another intermediate layer (4) on the surface of the intermediate layer (4) prepared in the above steps, and the repetition of this step n (n> 0) times until the total deposit thickness meets a requirement; and then, the treatment of the device substrate (1) and / or the support substrate (2) treated by the steps ci23 [Claim 9] above in a manner I or II in order to obtain an SOI material with a buried layer d special insulation, in which way I comprises: making a vacuum connection at low temperature on the device substrate (1) and the support substrate (2), and grinding and polishing a bonded sheet obtained in the above step in order to obtain the SOI material having a greater silicon thickness of between 1.5 and 250 μιη; and manner II comprises: injecting hydrogen ions into the device substrate (1) with an injection depth of 100 to 1500 nm, making a vacuum connection at low temperature on the substrate device (1) and the support substrate (2) in order to obtain a bonded sheet, performing a low temperature annealing process on the bonded sheet at an annealing temperature of 150 to 300, performing a separation by microwave or laser on the glued sheet in order to form a SOI structure material, and carrying out a chemical-mechanical planarization process on the SOI structure in order to form the SOI material having an upper layer thickness included between 0.02 and 1.5 μιη; microwave separation has the following requirements: a laser power is between 1 and 4 KW, a microwave duration is between 2 and 5 minutes, and a microwave temperature is between 70 and 400 ° VS ; and laser separation has the following requirements: an infrared laser is adopted, a laser point size is between 0.5 and 2 mm, a laser power is between 100 mw and 100 w, a heating time is between 10 and 30 s, a laser scanning path is located along the diameter direction of the silicon wafer, the number of scans of the silicon wafer is between 8 and 28, a laser beam scans the silicon wafer at an angle of incidence between 45 ° and 135 °, and the surface temperature of the silicon wafer increases rapidly by laser heating in order to allow the hydrogen ions of the silicon wafer to accumulate in order to effect the separation .
    A method of preparing the insulating layer structure for the semiconductor product according to claim 8, wherein the method of preparation meets one or a combination of the following requirements: first, during the deposition process of the intermediate layer (4), a hydrogen plasma etching step is added, so that a fragile Si-N bond is broken while filling a pendant silicon bond through an etching effect of the hydrogen plasma, and that a new stable Si-N bond is reformed; at the same time, a surface activity of the thin film is increased and the nucleation energy is reduced in order to prepare a high quality silicon nitride film as an intermediate layer (4); and then, a change in SOI deformation caused by the difference in thermal expansion coefficients after high temperature annealing is reduced by adjusting the thicknesses of the silicon oxynitride film and the silicon nitride film in the intermediate layer (4 ).
    [Claim 10] A method of preparing the insulating layer structure for the semiconductor product according to claim 8, wherein, during the laser separation process, the laser acts on the surface of the silicon wafer to heating the surface of the silicon wafer, so that the injected H + is accumulated in gas molecules which fill the cracks in order to form microbubbles of hydrogen; and, with the continuous accumulation of hydrogen molecules, a layer of hydrogen is finally peeled off in order to carry out the separation, and, thus, an SOI structure is formed.
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    同族专利:
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20020089016A1|1998-07-10|2002-07-11|Jean-Pierre Joly|Thin layer semi-conductor structure comprising a heat distribution layer|
    JP2000353797A|1999-06-11|2000-12-19|Mitsubishi Electric Corp|Semiconductor wafer and manufacture thereof|
    US20080213981A1|2005-01-31|2008-09-04|Freescale Semiconductor, Inc.|Method of Fabricating a Silicon-On-Insulator Structure|
    CN101101891A|2006-07-07|2008-01-09|上海新傲科技有限公司|Silicon of insulator and its making technology|
    EP1975998A3|2007-03-26|2013-12-04|Semiconductor Energy Laboratory Co., Ltd.|Method for manufacturing a plurality of island-shaped SOI structures|
    JP4577382B2|2008-03-06|2010-11-10|信越半導体株式会社|Manufacturing method of bonded wafer|
    FR2977069B1|2011-06-23|2014-02-07|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE USING TEMPORARY COLLAGE|
    CN102299093A|2011-06-30|2011-12-28|上海新傲科技股份有限公司|Method for preparing semiconductor substrate with insulation burying layer and semiconductor substrate|
    CN104112694B|2013-04-22|2018-01-30|高地|Method for film transfer|
    KR102294812B1|2014-01-23|2021-08-31|글로벌웨이퍼스 씨오., 엘티디.|High resistivity soi wafers and a method of manufacturing thereof|
    FR3027451B1|2014-10-21|2016-11-04|Soitec Silicon On Insulator|SUBSTRATE AND METHOD FOR MANUFACTURING SUBSTRATE|
    CN106992140A|2016-01-20|2017-07-28|沈阳硅基科技有限公司|A kind of method that use laser sliver technology prepares soi wafer|
    EP3758050A1|2016-03-07|2020-12-30|GlobalWafers Co., Ltd.|Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof|CN113454755A|2019-02-19|2021-09-28|应用材料公司|Polysilicon liner|
    WO2021079745A1|2019-10-24|2021-04-29|信越半導体株式会社|Semiconductor substrate manufacturing method and semiconductor substrate|
    CN112151534B|2020-11-09|2021-08-17|微龛半导体有限公司|Bidirectional ESD protection device, structure and preparation method|
    CN112951709A|2021-01-27|2021-06-11|济南晶正电子科技有限公司|Semiconductor substrate, electronic component and preparation method of semiconductor substrate|
    CN113471224B|2021-09-01|2021-11-16|绍兴中芯集成电路制造股份有限公司|SOI structure and manufacturing method thereof, MEMS device and manufacturing method thereof|
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    优先权:
    申请号 | 申请日 | 专利标题
    CN201810075853.XA|CN110085550A|2018-01-26|2018-01-26|A kind of semiconductor product insulation layer structure and preparation method thereof|
    CN201810075853.X|2018-01-26|
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