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    • 专利摘要:
    The invention relates to a photonic chip (1) comprising a light-guiding layer (12) supported by a substrate (10) and covered by an encapsulation layer (13). The chip has a front face (F1) on the side of the encapsulation layer (13) and a rear face (F2) on the side of the substrate (10). The light-guiding layer includes a light guiding structure (121) optically coupled to a vertical coupler (122) configured to receive light from the waveguide and form a beam of light directed to one front and back faces. The chip further comprises a collimation structure (14) formed at least in part in the light-guiding layer (12), and an arrangement of one or more reflective structures (151, 152) each on one of the front and back faces. This arrangement is designed to ensure the propagation of light between the vertical coupler and the collimation structure in an optical path having at least one folding.
    公开号:FR3074587A1
    申请号:FR1761723
    申请日:2017-12-06
    公开日:2019-06-07
    发明作者:Sylvie Menezo；Salim BOUTAMI；Bruno Mourey
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    FOLDING PHOTONIC CHIP
    OPTICAL ROUTE AND INTEGRATED COLLIMATION STRUCTURE
    DESCRIPTION
    TECHNICAL AREA
    The field of the invention is that of integrated photonics on a chip or integrated circuit. The invention relates to a photonic chip which has input (s) / output (s) to / from the chip, light beams having an enlarged mode size for coupling with an external device, for example with another photonic chip. , an optical fiber or a set of optical fibers, or for reception / emission of a beam of light in free propagation.
    PRIOR STATE OF THE ART
    A Photonic Integrated Circuit has several components interconnected by light waveguides. The photonic circuit generally having to communicate with the outside world, it is necessary to be able to inject / extract the light in / from the circuit in the form of an unguided light beam.
    In order to be able to inject / extract light to / from an integrated photonic circuit perpendicular to the plane of the chip, two types of vertical couplers are commonly used: surface coupling networks and solutions by angle transmission at the output of the chip.
    Area coupling networks
    A surface coupling network makes it possible, on the one hand, to adapt the size of the optical mode propagating in the waveguides of the photonic chip to the size of the optical mode propagating in standard monomode fibers, that is to say that is, a diameter of 9.2 μm, and, on the other hand, to pass from a guided propagation in the plane of the photonic chip to a propagation in free space almost vertical to the plane of the chip. This is obtained by etching a network in the layer comprising the waveguides. Such a component is for example described in: "Apodized Waveguide Grating Couplers for Efficient Coupling to Optical Fibers", IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 22, NO. 15, AUGUST 1, 2010, by Xia Chen and alter.
    In silicon technology, this component thus makes it possible to couple the light of a waveguide in the plane of the photonic chip to a cleaved single-mode fiber making an angle with the vertical, usually about 8 °. The losses of this component are from 1 to 4 dB optical when the geometric alignment between the surface coupling network and the single-mode fiber is optimal. The network-fiber alignment tolerance, characterized as the radial misalignment with respect to the optimal alignment which generates 1 dB of additional losses, is approximately 2 pm.
    In order to increase the alignment tolerance between a surface coupling network and an optical fiber and thus make alignment operations less complex and in particular achievable according to passive alignment techniques less costly, it has been proposed in the article. de S. Bernabé et al., On-Board Silicon Photonics-Based Transceivers With 1-Tb / s Capacity, in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, n ° 7, July 2016, to use a system of two lenses composed of a first lens secured to the photonic chip (which makes it possible to widen and collimate the beam at the input / output of the chip) and d 'a second lens secured to the optical fiber. The first lens must be aligned with the photonic chip very precisely, then must be secured to it. The alignment tolerance between the chip + first lens assembly and the second lens + fiber assembly is then increased to +/- 10 to 20 μm. In order to widen and collimate a light beam of wavelength λ and mode size Do = 2 * wo = 9.2pm at the output of the surface coupling network, the first lens must have a focal length in the air equal to Fair = Di. (π. wo / (2A)), Di being the size of the widened beam at the output of the first lens. Aiming at a mode size Di of 100 μm, a silica glass lens must have a thickness of approximately 860 μm. If this system makes it possible to soften the alignment constraints between the chip + first lens assembly and the fiber + second lens assembly, it has the drawback of transferring the alignment constraints between the first lens and the photonic chip to accuracy less than
    Ιμιτι. Furthermore, if the fact of extracting a collimated beam of enlarged size makes it possible to increase the alignment tolerance of the chip with an optomechanical interface piece facing the face of the chip, the angular reception tolerance is reduced .
    Solutions by angle transmission at the chip output
    In JLT 2016, VOL. 34, NO. 2, JANUARY 15, 2016, Suzuki et al. have proposed using a faceting of the 45 ° waveguide covered with a total mirror to allow a light beam to be returned perpendicularly to the rear face of the photonic chip. This vertical coupler is hereinafter called a coupler by "faceting of the waveguide". At the rear face, the beam being very divergent or unsuitable for the mode size of the fiber, it is proposed to integrate a lens on the rear face of the chip. In this implementation, the thickness traversed by the beam, between the faceted guide and the lens on the rear face, is approximately ΙΟΟμιτι which represents the potential focal length of the lens. This lens has a surface whose thickness varies continuously. The profile of this surface is thus qualified as analog. The manufacture of such an analog profile by etching uses a lithography technique by creep of resin or by so-called "gray tone" lithography which has the drawback of being difficult to calibrate in order to obtain the desired analog shapes. Such lenses must also be covered with anti-reflective layers, due to Fresnel reflections at the interface between the lens (index = 3.5) and air (index = 1). However, anti-reflective treatments are particularly fragile in hot / humid conditions (85 ° C / 85% humidity), which requires the use of airtight packaging.
    Another example of integration of a lens with a photonic chip on the beam path from / to a vertical coupler is given in US patent 8,515,217 B2.
    In a first variant of this patent, the lens is positioned on the front face of the chip, facing a surface coupling network which emits in the direction of the front face. By being integrated on the front face, the lens thus has a focal length potentially equal to the distance between the lens and the surface coupling network.
    In order for this lens to be integrated into the photonic chip and not to be related to the alignment stress described above, the lens must be produced in the encapsulation layer crossed by the beam on the coupler / lens path, which is usually only a few microns. However, a thickness of more than 400 μm of SiO 2 would be necessary to pass from a mode size at the output of the coupler.
    9.2 pm at a mode size at output of the 55 pm lens. This variant therefore does not make it possible to provide a beam of enlarged mode size. Furthermore, the fabrication of the front face lens has the drawback of requiring additional manufacturing steps after fabrication of the photonic chip, above the photonic chip, while the top of the photonic chip generally contains lines of metal. interconnection of photonic components with external electronic circuits.
    In a second variant of this patent, the lens is positioned on the rear face, facing a waveguide ending in an inclined facet covered with a mirror (hereinafter referred to as "faceted waveguide"), and directing the beam towards the rear face of the chip. This implementation and its limitations have been described above.
    In a third variant of this patent, the lens is positioned in the layer comprising the waveguides. No practical implementation of this variant is nevertheless described, and in particular no implementation making it possible to widen the mode size of the beam at the output of a vertical coupler.
    The lenses used in US Patent 8,515,217 B2 are so-called Fresnel analog lenses. A Fresnel lens replaces the curved surface of a conventional lens with a series of concentric rings of prismatic sections different from one ring to another. The thickness of a Fresnel lens is therefore reduced compared to a conventional lens, but its manufacture remains difficult. It requires a sawtooth analog structure, making it possible to define peaks of variable inclinations, generally carried out by the “Gray tone” lithography technique. Such a Fresnel lens also remains sensitive to Fresnel reflections. Finally, such a lens is sensitive to the polarization of light due to the rings. Indeed, the electric field of the optical wave can take any orientation in the plane of the chip and the indices seen by the wave, at the wavelength scale, differ according to the orientation of the electric field.
    STATEMENT OF THE INVENTION
    The object of the invention is to provide a photonic chip with means capable of collimating and widening an optical beam at the output of the photonic chip (and conversely to focus and adapt an optical beam at the input of the photonic chip to a vertical coupling structure of the photonic chip). And the invention seeks to simplify the manufacture of such a chip, in particular to overcome the manufacturing drawbacks mentioned above (analog profile, anti-reflection treatment).
    The invention also aims to solve the problem of sensitivity of the angular alignment between the chip from which is extracted a collimated beam of enlarged size and the opto-mechanical interface piece facing the face of the chip.
    To this end, the invention provides a photonic chip comprising a light guide layer supported by a substrate and covered by an encapsulation layer, the photonic chip having a front face on the side of the encapsulation layer and a rear face. on the substrate side. The light guide layer includes a light guide structure optically coupled to a vertical coupler configured to receive light from the waveguide and form a beam of light directed to one of the front and rear faces.
    The photonic chip further comprising a collimation structure formed at least partially in the light guide layer, as well as an arrangement of one or more reflecting structures each on one of the front and rear faces, said arrangement being produced so as to ensure the propagation of light between the vertical coupler and the collimation structure along an optical path having at least one folding.
    The folding of the optical path lengthens the focal length of the collimation structure in such a way that it can satisfactorily widen the diameter of the optical beam. Furthermore, the collimation structure integrated at least in part into the light guide layer may have a digital profile which can be obtained by means of standard manufacturing processes used for the structuring of the components of the light guide layer. .
    Some preferred but non-limiting aspects of this photonic chip are the following:
    the collimation structure comprises a plurality of trenches formed in the light guide layer, the trenches delimiting a set of patterns and each pattern having, in a direction orthogonal to the front and rear faces, an invariable thickness;
    the patterns are all the same thickness;
    the thickness of a pattern is at least equal to the thickness of the light guide layer;
    the patterns form a periodic two-dimensional network and in which the dimensions of the patterns are modulated from one period to another;
    the light guide layer is formed from a core refractive index material ne, and the trenches are left in the air or filled with a filling material with a refractive index nr lower than the refractive index made of core material;
    the collimation structure is configured to extract the light passing through it from the vertical coupler according to the normal to the front or rear face of the chip;
    the vertical coupler is a surface coupling network or a faceted waveguide type coupler;
    the substrate is made of silicon, the light guide layer rests on a layer of dielectric material, and an antireflection layer is interposed between the substrate and the layer of dielectric material.
    The invention extends to a method of manufacturing such a photonic chip.
    BRIEF DESCRIPTION OF THE DRAWINGS
    Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the accompanying drawings on which ones :
    - Figures 1 to 4 are schematic layers of photonic chips according to different embodiments of the invention;
    - Figures 5a, 5b and 5c are diagrams of lenses produced by etching according to etching modes called respectively digital (Figure 5a) and analog (Figures 5b and 5c) in the description of the invention;
    - Figures 6a and 6b illustrate different alternative embodiments of a collimation structure which can be integrated into a chip according to the invention;
    - Figures 7a and 7b illustrate the dimensioning of a symmetrical collimation structure that can be integrated into a chip according to the invention;
    - Figures 8a and 8b illustrate the dimensioning of an asymmetric collimation structure that can be integrated into a chip according to the invention;
    - Figures 9a and 9b provide examples of sizing of a Fresnel type collimation structure, the structure of Figure 9a does not straighten the light beam at the chip output and the structure of Figure 9b straighten the light beam at output of chip.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    Referring to Figures 1-4, the invention relates to a photonic chip 1 which comprises a light guide layer 12 supported by a substrate 10 and covered by an encapsulation layer 13. The light guide layer has a thickness generally between lOOnm and 3pm. The light guide layer may be made of silicon, InP, GaAs, Ge, or one or more semiconductor materials of the III-V or IV type.
    A buried oxide layer 11 can be interposed between the light guide layer 12 and the substrate 10. The substrate can be made of silicon, indium phosphide or gallium arsenide. The encapsulation layer 13 can be a layer of dielectric material, for example of silicon oxide, of silicon nitride, of polymer based on BCB (benzocyclobutene).
    The photonic chip 1 has a front face F1 on the side of the encapsulation layer 13 and a rear face F2 on the side of the substrate 10. The light guide layer comprises a light guide structure 121 coupled to a vertical coupler 122 configured to receive light from the light guide structure and form therefrom a beam of light directed towards one of the front and rear faces.
    By vertical coupler is meant a coupler making it possible to pass from a guided propagation in the plane of the chip (plane (xy) in FIG. 1) to a vertical or quasi-vertical propagation, typically forming an angle less than 90 °, and preferably between 0 and 45 °, with the normal to the front and rear faces of the chip (this normal extending in the direction z in FIG. 1), for example an angle Θ1 of 8 ° in a layer of encapsulation 13 in SiO 2 . The vertical coupler can be a surface coupling network ("grating coupler"). The vertical coupler can also be a faceted waveguide type coupler.
    The light guide structure 121 comprises the various photonic components, passive or active, up to the vertical coupler 122. It notably includes a waveguide, here shown with the vertical coupler 122 in a longitudinal section, the light propagating in Figure 1 in the direction x.
    The encapsulation layer 13 generally comprises metal levels of electrical interconnection of the photonic chip. This layer is thus made up of dielectric materials and etched lines of metal. An electronic chip intended to drive or read the active photonic components of the photonic chip (modulators, photo-detectors) is generally transferred to the front face of the photonic chip.
    In the rest of the document, the calculation examples are given for a light guide structure 121 made of silicon, a buried oxide layer 11 made of SiO 2 , and a substrate 10 made of silicon.
    To obtain at the output of the chip, from a surface coupling network 122 of mode size Do = 9.2 pm, a collimated and widened beam with a diameter of 80 pm, a silica glass lens must have a thickness of approximately 660 pm. It follows that the lens cannot be integrated on the front face F1 of the photonic chip because the optical path between the surface coupling network 122 and the front face F1 of the chip is only a few microns of silica (it roughly corresponds to the thickness of the encapsulation layer 13, for example 3 μm).
    An integration of the lens on the rear face F2 of the chip, with a vertical coupler 122 configured to direct the light beam received from the waveguide towards the rear face, is also not possible. In such a scenario, the length of the optical path between the vertical coupler 122 and the rear face F2 of the chip can be approximated as being the thickness of the substrate 10. For substrates of Si, InP or GaAs, the optical index at the wavelength 1.31 μm is approximately 3.5, and the necessary thickness of material to obtain a collimated widened beam with a diameter of 80 μm is of the order of 1550 μm. However, the thickness of the substrate is typically 775pm +/- 25pm for a silicon substrate 300 mm in diameter, 625pm +/- 25pm for an InP substrate of 75mm in diameter, and 450pm for a substrate of GaAs substrate of 75mm in diameter. The thickness of the substrate 10 is therefore generally insufficient to allow the beam diameter to be widened satisfactorily.
    To overcome these difficulties of integrating the lens on the front or rear face of the photonic chip, and still with reference to FIGS. 1 to 4, the invention proposes a photonic chip which is provided with an arrangement of one or more structures reflecting 151, 152 each on one of the front and rear faces. This arrangement is made so as to ensure the propagation of light between the vertical coupler 122 and a collimating structure of light 14 formed at least partially in the light guide layer 12, this propagation taking place along a path optical having at least one folding in the substrate.
    More particularly, this arrangement comprises a reflecting structure 152 on the rear face. In such a way that the light extraction takes place through the front face (FIGS. 1, 2 and 3) or through the rear face (FIG. 4), the optical path comprises at least one double passage through the substrate 10 By thus lengthening the focal length, the collimation structure 14 makes it possible to satisfactorily widen the diameter of the optical beam.
    In one embodiment, a reflective structure of said arrangement is a metal layer deposited on one of the front and rear faces, for example a layer of gold, silver or aluminum. In an alternative embodiment, a reflective structure of said arrangement is a distributed Bragg reflector (DBR for “Distributed Bragg Reflector”) formed of a stack of layers deposited on one of the front and rear faces.
    A reflective structure is formed locally on one of the front and rear faces of the photonic chip. Alternatively, a reflecting structure can be formed on the whole of one of the front and rear faces of the photonic chip, for example on the whole of the rear face as shown in the exemplary embodiment of FIG. 2.
    The description which follows takes more particularly the example of the transmission of light from the guide structure of the photonic chip towards the external device (light extraction), the collimation structure forming a light output port. The principles presented are however perfectly identical for a transmission of light from the external device towards the guide structure of the photonic chip (light injection), the collimation structure forming a light input port. Thus, the vertical coupler 122 is not only configured to receive light from the light guiding structure and form therefrom a beam of light directed towards the front face F1 or the rear face F2 and reflected by the or the reflecting structures until reaching and passing through the collimation structure 14, but also configured to receive from the front face or the rear face a beam of light having passed through the collimation structure and having been reflected on the reflecting structure or structures and transfer this beam to the light guide structure 121.
    There are shown in Figures 1, 2 and 3 different examples of a first embodiment in which the light is extracted / injected from / to the photonic chip through the front face F1.
    In the example of FIG. 1, the vertical coupler 122 is configured to receive the light from the light guiding structure 121 and form from this a beam of light directed towards the front face Fl with an angle Θ1 with respect to the vertical. In this example, the arrangement of one or more reflecting structures comprises a first reflecting structure 151 on the front face F1 and a second reflecting structure 152 on the rear face F2. The beam at the outlet of the vertical coupler 122 is reflected by the first reflecting structure 151 towards the second reflecting structure 152 and then from the second reflecting structure 152 towards the collimation structure 14. In this example, the optical path of the vertical coupler to the collimation structure can be approximated to 2 x T10, where T10 represents the thickness of the substrate 10.
    In the examples of FIGS. 2 and 3, the vertical coupler 122 is configured to receive light from the light guiding structure 121 and form therefrom a beam of light directed towards the rear face Fl with an angle Θ1 with respect to the vertical. In this example, the arrangement of one or more reflecting structures comprises a single reflecting structure 152 on the rear face F2 (a full plate structure in the context of FIG. 2, a structure located in the framework of FIG. 3). The beam at the outlet of the vertical coupler 122 is reflected by this single reflecting structure 152 in the direction of the collimation structure 14. In the buried oxide layer 11 made of SiO 2 , the angle Θ1 is for example 8 °. In the silicon substrate 10, the angle Θ2 is then approximately 3 °. The optical path, CO, from the vertical coupler to the collimation structure is strictly written as CO = 2 x Tll / cos (Θ1) + 2 x T10 / cos (Θ2), with T10 the thickness of the substrate and Tll l ' thickness of the buried oxide layer 11. This optical path can be approximated as 2 xTIO with less than 0.5% error. By using a vertical coupler 122 of the surface coupling network type, and with a silicon substrate 10 of thickness T10 = 775 μm traversed twice, the diameter of the beam at the outlet of the collimation structure can be widened up to approximately 80 pm.
    FIG. 4 shows an example of a second embodiment in which the light is extracted / injected from / towards the photonic chip through the rear face F2. In this example, the vertical coupler 122 is configured to receive light from the light guide structure 121 and form therefrom a beam of light directed towards the rear face Fl with an angle Θ1 in the SiO2 relative to vertically. The arrangement of one or more reflecting structures comprises a first reflecting structure 152 on the rear face F2 and a second reflecting structure 151 on the front face F1. The beam at the outlet of the vertical coupler 122 is reflected by the first reflecting structure 152 in direction of the second reflecting structure 151 then of the second reflecting structure 151 in the direction of the collimation structure 14.
    In one possible embodiment, the light guide layer rests on a layer of dielectric material, and an antireflection layer is interposed between the substrate and the layer of dielectric material. Fresnel losses are effectively observed during the crossing of the interface between the dielectric layer 11 and the substrate 10: they are 0.8 dB with a layer 11 of SiO 2 and a substrate 10 of silicon. An anti-reflective layer arranged between the dielectric layer 11 and the substrate 10 makes it possible to limit these losses. The antireflection layer is for example a layer of silicon nitride, of thickness λ / 4 where λ corresponds to the wavelength of the light beam. It is also possible to adopt, for the material of layer 11, not SiO 2 but a silicon nitride or a stack of a sublayer of SiO2 and a sublayer of silicon nitride. The losses during the crossing of the interface between the layer 11 and the substrate 10 are thus less than 0.5dB at the wavelength 1.31pm
    In the context of the invention, the collimation structure 14 is formed, at least in part, in the light guide layer 12. The invention therefore does not have recourse to a collimation structure carried over or integrated at the level from the front face or from the rear face of the photonic chip, which makes it possible to overcome the manufacturing constraints and limitations mentioned above.
    In particular, the collimation structure 14 can be formed during the “front end” manufacturing steps of the photonic components (waveguide, surface coupling network, PN modulator, etc.) by etching the surface layer 12 of a substrate SOI. With particular reference to FIG. 5a, the collimation structure 14 can thus comprise a plurality of trenches Tl, T2, T3 formed in the light guide layer 12, the trenches delimiting a set of patterns Ml, M2 and each pattern having , in a direction orthogonal to the front and rear faces, an invariable thickness. In a preferred embodiment, the patterns all have the same thickness and the trenches pass through the thickness of the light guide layer 12. The invention however extends to patterns having different thicknesses, and more particularly to patterns distributed in a first set of patterns having a first thickness and a second set of patterns having a second thickness. The first thickness may be greater than the second thickness, and the patterns of the first set may be wider patterns than the patterns of the second set.
    The thickness of the patterns is typically defined by an engraving depth of the trenches. The thickness of a pattern may be less, equal to or even greater than the thickness of the waveguide 121 of the light guide layer (equal to the thickness of the waveguide in FIGS. 1 and 2, greater than the thickness of the waveguide in Figures 3 and 4). In FIG. 4, the thickness h of the patterns corresponds to the thickness of the light guide layer 12 (the waveguide having a thickness thinner than that of the light guide layer 12) while in FIG. 3, the thickness h of the patterns is greater than the thickness of the light guide layer
    12. In the alternative embodiment of FIG. 3, the patterns consist of the material of the light guide layer and the material of an additional layer added to the light guide layer. This additional layer is for example in deposited amorphous silicon or in crystalline silicon, or in any other material with a high index by contrast with that of air or of the material coming to fill the trenches.
    The collimation structure can thus be manufactured by means of standard manufacturing steps (lithography / engraving), that is to say giving rise to “digital” structures (FIG. 5a, where a digital 1 corresponds to an engraving d '' a trench and a digital 0 corresponds to an absence of etching defining a pattern of invariable thickness) as opposed to state-of-the-art collimation structures which require an "analog" structuring making it possible to define patterns d variable thickness, for example a spherical diopter (Figure 5b) or peaks of variable inclinations (Figure 5c). Such analog structuring is generally obtained by a technique of lithography by creep of the resin or by so-called "gray tone" lithography which has the drawback of being difficult to calibrate in order to obtain the desired analog shapes.
    The invention thus makes it possible to benefit from a large focal length due to the folding of the optical path between the vertical coupler and the collimation structure (this focal length is at most about twice the thickness of the substrate 10). It also makes it possible to produce the collimation structure before the metal layers of the photonic chip are formed, this structure being produced at the level of the light guide layer, that is to say at the level of the components of the photonic chip.
    Using the reference (xyz) in Figure 1 and with reference to Figure 6a, each trench has a depth in the direction orthogonal to the front and rear faces (direction z). The trenches separate patterns of invariable thickness which can form a two-dimensional network. As represented in FIGS. 6b, 7b and 8b, the patterns can form a matrix network of studs of section (in the plane (xy)) square or rectangular (FIG. 6c), or circular (FIGS. 7b and 8b). These latter forms, unlike rings, allow insensitivity to polarization. Indeed the electric field of the optical wave can take any orientation in the plane (xy) and the indices seen by the wave, on the wavelength scale, are identical whatever the orientation of the electric field. .
    The structuring of the core layer 1 consists in forming therein a plurality of trenches T1-T4 with a refractive index lower than the refractive index of the patterns. In this way, the collimation structure forms a pseudo-gradient refractive index structure capable of collimating outward an incident curved wavefront from the vertical coupler (and vice versa to generate a curved phase shift d 'an incident plane wavefront from the outside). More particularly, the light guide layer is formed from a core material of refractive index ne in which the patterns are formed, and the trenches are left in the air or filled with a filling material with an index of refraction nr lower than the refractive index ne of the core material, for example in SiO 2 . The difference between the refractive indices of the heart and the trenches is preferably at least equal to 0.2.
    By pseudo-index gradient, it is understood in the context of the invention that the collimation structure does not include a true profile of variation of refractive index of the core material as is the case of structures called "graded- index ”, but that it has the same properties. Thus during its passage through the collimation structure, the light meets the equivalent of a lens.
    The trenches can be arranged periodically, the width of the trenches separating two contiguous patterns being modulated from one trench to another. In this way, the material filling factor of the core layer (which defines the local refractive index) changes along the collimation structure.
    Taking the example of a matrix network of cylindrical pads, this network includes a set of square elementary cells of the same size, there is one pad per cell and the surface of the pads is modulated from one cell to another. The filling factor can then be expressed as the ratio between the surface of a pad and the surface of the elementary cell. With a 500nm square elementary cell, the stud diameter can vary between 20nm and 480nm.
    It will be noted that compared to an analog lens (classic or Fresnel), the proposed structure has lower reflections. Indeed, the average index is greatly reduced.
    In a possible embodiment of the invention, the collimation structure is configured to extract the light passing through it from the vertical coupler along the normal to the front or rear face of the chip. We have previously seen that in certain configurations the vertical coupler makes it possible to pass from a guided propagation in the plane of the chip to a quasi-vertical propagation forming an angle with the normal to the front and rear faces of the chip. In the context of this embodiment, the collimation structure makes it possible to straighten the beam so that the beam leaving the front or rear face of the photonic chip is perpendicular to the front and rear faces of the chip (FIGS. 8a and 8b discussed below).
    Using the invention to extract a collimated beam of enlarged size makes it possible to increase the alignment tolerance along the x, y axes of the chip with an opto-mechanical interface piece placed on one face of the chip. . But the angular reception tolerance is reduced. By coming to straighten the beam so that it presents an angle of 90 ° with the face of the chip, the coupling with the interface part is facilitated. Thus, the part can be placed on the flat surface of the chip, strictly perpendicular to it. The problem of angular sensitivity of the alignment is thus completely resolved, since the opto-mechanical part, in contact with the face F1 of the chip, is strictly perpendicular to the chip, without possible angular spacing with respect to the z axis.
    FIGS. 7a-7b illustrate the dimensioning of a symmetrical collimation structure and disposed vertically of the vertical coupler 122 represented by the point Cv on the z axis (case where Θ1 = Θ2 = 0). FIGS. 8a-8b illustrate the dimensioning of an asymmetrical collimated structure offset by X = Th x tan Θ2 relative to the vertical coupler 122 and making it possible to straighten the collimated beam extracted from the coupler 122. Not shown here, it is of course possible to extract a non-vertical collimated beam (Θ2 * 0) without straightening it: a symmetrical collimation structure is then used, its center being offset by X = Th x tan Θ2 relative to the vertical coupler 122. These collimation structures can be integrated into a chip according to the invention, in accordance with the embodiment of a two-dimensional network of cylindrical pads insensitive to polarization.
    The collimation structure is configured to generate a curved phase shift of an incident plane wavefront from the outside of the chip, phase shift such that the rays are, after crossing the collimation structure, all in phase at the focal point of the structure of the collimation, the focal point being the vertical coupler (assimilated to a point with regard to the focal distance Th which corresponds overall to twice the thickness of the substrate 10). Conversely, the collimation structure generates a plane wavefront from a divergent beam coming from the vertical coupler. Figures 7a and 8a are views of the patterns in a section parallel to the plane (xz) while Figures 7b and 8b are views of the patterns in a section parallel to the plane (xy).
    The diameter of the studs is calculated according to the methodology presented below.
    In the example of FIGS. 7a and 7b where the focal point is on the median axis z of the collimation structure, and of filling the trenches with SiO 2 , this configuration results in:
    Let h (x, y) = n (0) - n ° ^ F + x + yn ° F , where n (x, y) represents the average index of the lens at position (x, y), related to silicon filling factor, h the thickness of the silicon patterns, Th corresponds to twice the thickness of the substrate (for example 2 x 775pm for an SOI substrate 300mm in diameter), λ the central wavelength of the beam luminous and n Q the index of the material making up the substrate 10.
    The average index n (x) is linked to the silicon filling factor f S iÇx by:
    h (x) = fst (x) * "fi + (1 - / siO)) * n sio2> with n si and nsi02 es respective indices of Silicon and SiO2.
    We deduce the evolution of the silicon filling factor:
    If we consider that the collimation structure is similar to a pseudoperiodic network, of pseudoperiod P (position of the centers of the pads) and whose variable diameter of the pads W Si (x, y), the patterns have a diameter defined according to a series W If (n, p), satisfying, for ne [-N; N] and pe [-N; N]:
    / 17TV / si (0) 2 * n2. + ( 4 / J 2_ relVsi ( - 0) 2) t n2. o J F 2 + ( n p) 2 + (pp) 2_ Λ
    U --------------------- ~ n ° ~ ----- h ------) -4îo 2
    W if (n, p) = 2P.
    π (4ί-4ίο 2 ) (D
    In the example of FIGS. 8a and 8b the focal point of the collimation structure is offset from the median axis z by a distance X = Th x tan Θ2. The collimation structure is calculated as follows:
    - n (x, y) h + —r'n.QyjF 2 + (x - Ύ) 2 + y 2 = - iï (0) h + —n o y F 2 + X 2 λ λ λ λ c -4 . λ / F 2 + (xX) 2 + y 2 -Vf 2 + X 2
    Let, n (x) = n (0) - n 0 ---------------------.
    Knowing that: n (x) = JfsiW * "fi + (1 - / s; O)) * n sio 2
    We can deduce :
    fsiW (nli - n-sioz)
    If we consider that the collimation structure is similar to a pseudoperiodic network, of pseudoperiod P (position of the centers of the pads) and whose variable diameter of the pads W Si (x, y), the patterns have a diameter defined according to a series W If (n, p), satisfying, for ne [-N; N] and pe [-N; N]:
    W if (n, p ') = 2P.
    / lnW if (0) 2 tn ^ + (4P 2 -nWsi (0) 2 y n ^ io Jp 2 + (nP — X) 2 + (pP) 2 - Jf 2 + X 2
    U --------------------- ~ n ° ~ --------- h ---------) -4 i02 “ ---------------------- ^ 2_ ~ 2 .---------------------- ( 2)
    For a collimation structure without straightening, it is the central motif which has the largest width, so we can fix l // If (0) = P - cd_min, with cd_min the minimum width of a technically feasible trench by engraving. Such a collimation structure is symmetrical.
    For a collimation structure ensuring the straightening of the beam (case of FIG. 8b), the position of the largest pattern can be found by deriving equation (2) with respect to n: this is the pattern of abscissa X which is the largest (the one directly above the focal point). This collimation structure is therefore asymmetrical.
    For this asymmetric collimation structure, we can rewrite the equations, not according to V / 5i (0), but according to W Sl (X):
    2π zx 2π ---------------- 2π z 2π - n (x, y) / i + - n 0A / F 2 + (x - Ύ) 2 + y 2 = - n (X, 0) / i + - n 0 F AA AA
    Let: n (x, y) = n (X, 0) + y [F - ^ / F 2 + (x - X) 2 + y 2 ] * 3
    πΐν <^ (0) 2 + η + [F - jF 2 + (xX) 2 + y 2 ] l 2 - n SiO 2 uW si (0) ^ si Ηρ2 + ( „ Ρ _ χ) 2 + (ρΡ) 2_ ^ 1
    -------------- no 1 ------------------ 1
    -n 2 · rl SiO 2
    When X <D / 2 with D the width of the collimation structure along the x axis, the largest pattern is that of abscissa X: W if _ max = W Sl (X) = P - cd_min.
    We can deduce :
    4P 2
    -n 2 · rl SiO 2 (3)
    It is also possible to determine the minimum diameter W if _ min of a pattern, which is the diameter of the pattern furthest from the abscissa X. We have:
    ^ Si-min
    r ί2 π (Ρ - cd_min) 2 *% + (4P 2 - π (Ρ - cd_min) 2 ) * ng t02 [ F 2 + (N + Z) 2 + (NP) 2 - pj - η 2 · Sl0 2 J 4P 2 n ° h AT π (. η 1ι ~ η 1ι θ2 )
    = cd_min
    This last equation makes it possible to determine the minimum etching thickness h making it possible to design a technically feasible collimation structure, that is to say not exceeding cd_min and P-cd_min in diameter of patterns, for a lens width D given along the x axis:
    2P Jf 2 + (np + x) 2 + (np) 2 -f h = n 0 _, —--- (4) π (Ρ-εά_τηίη) 2 * η ^ + (4Ρ 2 -π (Ρ -εά_τηίη) 2 ) * η ^ θ2 -l ^ cdmin 2 * Çn ^ in ^ iO2 J + 4P 2 n ^ iO2
    On the other hand, if X> D / 2, then the largest pattern is that which is closest to the abscissa X. Taking the case X> 0 where the largest pattern is that of index N (for X <0, just return the collimation structure). We rewrite the equations with respect to this pattern of index N:
    2π zs 2π ---------------- 2 π zs 2π ------------— n (x, y) h + —n oy j F 2 + (x - Ύ) 2 + y 2 = - n (NP) h + —n oy j F 2 + (NP - X) 2 λ λ λ λ
    This ultimately gives:
    h
    2 ttWsî (NP) 2 * n 2 t + (4P 2 - xWsi (/ VP) 2 ) * _ [^ / F 2 + (nP - X) 2 + (pP) 2 - yjF 2 + (NP - X) 2 ] J 4P 2 n ° h 4
    By imposing the largest dimension on the motif of index N, we have:
    W if (n, p) =
    Ιπ (Ρ-οά_τηΪ7ΐ) 2 * η ^ + (4Ρ 2 -π (Ρ-οά_7ηΐτι) 2 ) * η ^ θ2 | Jf 2 + (uP X) 2 + (pP) 2 Jp 2 + (NP X) 2 n SiO 2 y] 4P 2 n ° H π ( η εί ~ η είο 2 )
    (3a)
    The stud of smaller dimension is then of index (-N, ± N):
    ^ Si-min = 2P.
    y π (Ρ - cd_min) 2 * + (4P 2 - π (P - cd_min) 2 ) * η 2 ί0
    J ------------------- ------------------ 4Ρ2 "" ο
    4P 2 [Vf 2 + (wp + x) 2 + (wp) 2 - V F2 + ( NP ~ Ό 2 ] h
    - cd_min π ( η 1ί - nlioj
    Which gives us the value of h in this case:
    2P Jf 2 + (NP + X) 2 + (NP) 2 -Jf 2 + (NP-X) 2
    The procedure for designing the collimation structure can be as follows:
    1) Taking into account P and cd_min, the necessary thickness of the collimation structure is determined according to equations (4) or (4bis), depending on whether X <D / 2 or X> D / 2.
    2) We then deduce, with the thickness h previously found, the exact profile of the collimation structure according to equations (3) or (3bis), depending on whether X <D / 2 or X> D / 2.
    In an alternative embodiment, the collimation structure does not form the equivalent of a simple lens but the equivalent of a Fresnel lens. According to this approach, a smaller thickness h is imposed, and larger index gradients are authorized to compensate for this small thickness, these gradients being repeated by 2π phase modulos to cover the entire width of the collimation structure.
    According to this approach:
    2π z 2π ---------------- 2π zs 2π —n (x, y) / i + - n 0A / F 2 + (x - Ύ) 2 + y 2 = - n (X) h + - n 0 F [2n] AA AA
    Let n (x, y) = n (X) - y [^ / F 2 + (x - Ύ) 2 + y 2 - F] + m ^, meZ +
    Let fât - n li 02 )
    Is :
    W if (n, p) =
    4P 2
    -n 2 · fL SiO 2
    -------- (5)
    The term m adds an increment to the width to prevent it from going below cd_min. However, this increment must not make pass the width beyond P-cd_min to have the modulo 2π of phase, or below cd_min respectively. This places constraints on the minimum thickness of the 5 Fresnel hmin lens, so that it is technically feasible. Suppose that one of the patterns has a width of cd_min (lower limit). This pattern has an index (ri, p ') which checks:
    cdjni ^ nÇnh - nl i0 J + 4P 2 . nl io .
    4P 2 h
    An addition of λ / h in the square of the right term must generate a width less than P-cd_min in equation (5), that is:
    We therefore deduce that there is a constraint between the wavelength and the thickness, for a given technology (P, cdmin), so that the Fresnel lens is achievable.
    [Ρπ (Ρ - 2cd min ') (nl i - - 4P 2 n ^ iOz ]. H 2 - βΡ 2 ^ hmin therefore corresponds to the 2 nd root of the 2 nd degree equation, that is:
    The period P cannot exceed λ / 2 so that the structuring is
    behaves like a medium of average index. By imposing this constraint, we can simplify expression (6), and end up with:
    cd_min 2 7r (nfi - η | ίΟζ) + λ 2 .η | ίθ2 + ^ π (η ^ - η | ίθ2 ) (λ - 2cd min ) π (Λ - 4cd min ) (n ^ - - 4λη ^ Οζ
    An example of sizing of the collimation structure is as follows. A surface coupling network is used as a vertical coupler (Do = 9.2pm), produced in silicon photonic technology, in an SOI substrate. One also fixes a mode size wi = Di / 2 (Di = D) at the output of the collimation structure, for example Di = 80pm. We seek a thickness of the patterns, cylindrical, in a two-dimensional network with constant mesh P, the smallest possible. We set the minimum diameter of a pattern at 80nm, and we consider a pseudo-period of the etched structures P = 500nm. We use an SOI substrate with a thickness of 775pm, so Th = 1550pm. With an exit angle of the surface coupling network 01 in SiO2 equal to 8 °, 02 in silicon is equal to 3.3 ° (nsi x sin (02) = n S iO2 x sin (01) with n Si = 3.5 and n S iO2 = 1.45). This results in a focal length in the substrate of about 750pm. The center of the collimation structure is offset from the center of the vertical coupler by X = 2 x Th x tan (02) ~ 90pm which must be greater than Di / 2, which is the case
    With the preceding equations, the minimum thickness of the patterns of the collimation structure is calculated in the case where it is of the simple lens type or of the Fresnel lens type. In the selected digital application, the minimum thickness is
    1.1 pm for the Fresnel lens case and several pm for the simple lens case. Then the diameters of the patterns to be engraved are calculated to form the collimation structure by considering V / 5i _ min = 0.08 pm.
    FIG. 9a shows an example of the dimensioning of a two-dimensional collimation structure which does not straighten the light beam at the output of the chip, and in FIG. 9b an example of the dimensioning of a collimation structure which straightens the light beam at the output. of chip. These figures represent more particularly the diameter Dp of the cylindrical studs in the digital application described above. The thickness of the patterns is 1.1 µm.
    These FIGS. 9a and 9b relate to structures of the Fresnel lens type. The diameter of the studs defines the local average index and these figures therefore also illustrate the pseudo-index gradient of the collimation structure. One can also compare the variation profile of the diameter of the studs of the collimation structure of the invention with the geometric profile of analog lenses.
    The invention is not limited to the photonic chip previously described, but also extends to its manufacturing method, and in particular to a method of manufacturing several chips collectively on the same plate. This method comprises the formation of a collimation structure 14 at least partially in the light guide layer 12, and the formation of an arrangement of one or more reflecting structures 151, 152 each on one of the front faces and rear, said arrangement being made so as to ensure the propagation of light between the vertical coupler and the collimation structure along an optical path having at least one folding.
    An exemplary embodiment of this method is as follows. The process begins with the provision of an SOI substrate having a buried oxide layer 11 interposed between a surface silicon layer 12 and a silicon substrate 10. The process continues with the manufacture of photonic components (waveguide 121 , vertical coupler 122, PN modulator, etc.) and patterns of the collimation structure 14 by localized partial or total etching of the surface silicon layer 12
    The next step is to manufacture the encapsulation layer 13. This layer may include the metal levels of electrical interconnections of the photonic chip. It may or may not come to fill the trenches of the collimation structure. The reflective structure 152 is then formed on the rear face, for example by depositing a metallic layer. This operation can however be carried out at another time, for example at the very beginning of the process.
    权利要求:
    Claims (10)
    [1" id="c-fr-0001]
    1. Photonic chip (1) comprising a light guide layer (12) supported by a substrate (10) and covered by an encapsulation layer (13), the photonic chip having a front face (Fl) on the side of the encapsulation layer (13) and a rear face (F2) on the substrate side (10), the light guide layer including a light guide structure (121) optically coupled to a vertical coupler (122) configured to receive light from the waveguide and form a beam of light directed to one of the front and rear faces, the photonic chip further comprising a collimation structure (14) formed at least in part in the layer for guiding the light (12), the photonic chip being characterized in that it comprises an arrangement of one or more reflecting structures (151, 152) each on one of the front and rear faces, said arrangement being made of so as to ensure the spread of the light between the vertical coupler and the collimation structure along an optical path having at least one folding.
    [2" id="c-fr-0002]
    2. A photonic chip according to claim 1, in which the collimation structure (14) comprises a plurality of trenches (Tl, T2, T3) formed in the light guide layer, the trenches delimiting a set of patterns (Ml, M2, M3) and each pattern having, in a direction orthogonal to the front and rear faces, an invariable thickness.
    [3" id="c-fr-0003]
    3. The photonic chip according to claim 2, in which the patterns all have the same thickness.
    [4" id="c-fr-0004]
    4. Photonic chip according to one of claims 2 and 3, wherein the thickness of a pattern is at least equal to the thickness of the light guide layer.
    [5" id="c-fr-0005]
    5. Photonic chip according to one of claims 2 to 4, in which the patterns form a periodic two-dimensional network and in which the dimensions of the patterns are modulated from one period to another.
    [6" id="c-fr-0006]
    6. Photonic chip according to one of claims 2 to 5, in which the light guide layer is formed in a material of refractive index core ne, and the trenches are left in the air or filled with a filling material with a refractive index nr lower than the refractive index ne of the core material.
    [7" id="c-fr-0007]
    7. Photonic chip according to one of claims 1 to 6, in which the collimation structure (14) is configured to extract the light passing through it from the vertical coupler according to the normal to the front or rear face of the chip.
    [8" id="c-fr-0008]
    8. Photonic chip according to one of claims 1 to 7, in which the vertical coupler (122) is a surface coupling network or a coupler of faceted waveguide type.
    [9" id="c-fr-0009]
    9. Photonic chip according to one of claims 1 to 8, in which the substrate (10) is made of silicon, the light guide layer (12) rests on a layer of dielectric material (11), and an antireflection layer is interposed between the substrate (10) and the layer of dielectric material (11).
    [10" id="c-fr-0010]
    10. Method for manufacturing a photonic chip (1) comprising a light guide layer (12) supported by a substrate (10) and covered by an encapsulation layer (13), the photonic chip having a front face (F1) on the side of the encapsulation layer (13) and a rear face (F2) on the side of the substrate (10), the light guide layer including a light guide structure (121) optically coupled to a vertical coupler (122) configured to receive light from the waveguide and form a beam of light directed to one of the front and rear faces, the method comprising forming a collimation structure (14) at the less partially in the light guide layer (12), and the formation of an arrangement of one or more reflecting structures (151,152) each on one of the front and rear faces, said arrangement being made so as to ensure the propagation of light between the vertical coupler and the collimation structure along an optical path having at least one folding.
    S.63266
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    法律状态:
    2018-12-31| PLFP| Fee payment|Year of fee payment: 2 |
    2019-06-07| PLSC| Publication of the preliminary search report|Effective date: 20190607 |
    2019-12-31| PLFP| Fee payment|Year of fee payment: 3 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 4 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1761723|2017-12-06|
    FR1761723A|FR3074587B1|2017-12-06|2017-12-06|PHOTONIC CHIP WITH OPTICAL PATH FOLDING AND INTEGRATED COLLIMATION STRUCTURE|FR1761723A| FR3074587B1|2017-12-06|2017-12-06|PHOTONIC CHIP WITH OPTICAL PATH FOLDING AND INTEGRATED COLLIMATION STRUCTURE|
    US16/202,682| US10459163B2|2017-12-06|2018-11-28|Photonic chip with folding of optical path and integrated collimation structure|
    EP18210428.1A| EP3495861A1|2017-12-06|2018-12-05|Photonic chip with bending optical path and integrated collimation structure|
    JP2018228068A| JP2019101444A|2017-12-06|2018-12-05|Photonic chip with folding of optical path and integrated collimation structure|
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