• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a ceramic module for integrated power semiconductor packaging and a related preparation method. The ceramic module comprises a ceramic substrate (10) and an integrated metal retaining layer (20). The use of the integrated metal retaining layer (20) on the upper surface of the ceramic substrate (10) and the formation of cavities (21) around the chip attachment areas (40) seal the semiconductor chip. conductive. The use of a heat dissipation layer (33) on the lower surface of the ceramic substrate (10) makes it possible to rapidly convey the heat generated by the semiconductor chip to the outside. The product has a simple manufacturing process and a high product consistency.
    公开号:FR3069101A1
    申请号:FR1870829
    申请日:2018-07-12
    公开日:2019-01-18
    发明作者:Zhaohui Wu；Wei Kang；Xiaoquan Guo；Jun Zhang
    申请人:Dongguan China Advanced Ceramic Tech Co Ltd；
    IPC主号:
    专利说明:

    Description
    Title of the invention: CERAMIC MODULE FOR INTEGRATED PACKAGING OF POWER SEMICONDUCTOR AND ASSOCIATED PREPARATION METHOD FRAMEWORK OF THE INVENTION Technical field [0001] The present invention relates to the field of power semiconductor packaging technology, and in particular a ceramic module for the integrated packaging of power semiconductors and an associated preparation process.
    PRIOR ART [0002] In integrated circuits and power electronics applications, semiconductor power devices for photoelectric conversion and power conversion have been widely used in various fields such as high power light emitting diodes , lasers, motor control, wind power generation, and UPS devices. In recent years, the miniaturization of power semiconductor modules has become a trend in response to the space and weight requirements of power electronic systems.
    It is necessary, in the process of conditioning power semiconductor modules, to solve the problem of low power, low integration and insufficient functionality of a single chip, to package several highly integrated, high performance and high reliability in a module via a serial and parallel connection to obtain an integrated multi-chip packaging.
    The integrated multi-chip packaging will increase the current density flowing in the module, and the energy consumption of the chip will also increase. It is therefore necessary to increase the thermal conductivity of the module. In addition, as the operating voltage increases, the insulation performance of the module must be improved. It is therefore necessary to choose a wiring material with low resistivity and an insulating material with low dielectric constant and high thermal conductivity as the packaging medium. A ceramic module corresponds well to the requirements.
    In the packaging of a power semiconductor, a ceramic module (or a ceramic base) is an important support substrate for semiconductor chips and other microelectronic devices, ensuring the functions of forming a sealed chamber , mechanical support protection, electrical interconnection (insulation), thermal conduction, heat dissipation, and auxiliary light. The ceramic modules used for conditioning power semiconductors include HTCC / LTCC and DBC ceramic substrates.
    HTCC is also called multilayer ceramic co-fired at high temperature. LTCC is also called multilayer ceramic co-fired at low temperature. This technology uses thick film printing technology to complete the fabrication of circuits. Therefore, the surface of the circuit is frosted (Ra about 1 to 3 µm), and the alignment is not precise. On the other hand, multi-layer ceramic laminates, high temperature sintering and other processes mean that the ceramic modules are imprecise in size and have a large curvature. In addition, the ceramic material used in this process has a complex formulation and low thermal conductivity, it also requires a special molding die, a long manufacturing cycle and has a high cost.
    A DBC ceramic substrate is also called a direct bond ceramic substrate. This technology uses a high temperature bond to sinter the copper foil on the top and bottom surfaces of the ceramic. The circuit is formed by etching according to the circuit design. This process renders the DBC ceramic substrate incapable of obtaining a concave sealed chamber on its surface, so that it cannot carry out hermetic vacuum packaging and cannot prepare vertical interconnecting holes to interconnect. upper and lower circuits. Thus, serial and parallel connection and multi-chip cabling are difficult. The above problems have considerably restricted the application of such ceramic substrates in power semiconductor packages.
    DESCRIPTION OF THE INVENTION In view of the defects in the state of the art, the main object of the present invention is to provide a ceramic module for the integrated packaging of power semiconductors and an associated preparation process, capable of effectively solving the problems of imprecise size, strong curvature, poor heat dissipation, absence of recessed hermetic cavity and other disadvantages for the multi-chip integration of the conventional ceramic substrate.
    In order to achieve the above object, the present invention adopts the following technical solutions:
    One aspect of the present invention relates to a ceramic module for integrated packaging of power semiconductors. The ceramic module includes a ceramic substrate and an integrated metal retaining layer. A bottom surface of the ceramic substrate has a conductive circuit layer, an insulating layer, and a heat dissipation layer. The insulating layer completely covers the conductive circuit layer. The heat dissipation layer is located on an area outside the conductive circuit layer and spaced from the conductive circuit layer. The heat dissipation layer has a thickness not less than a total thickness of the conductive circuit layer and the insulating layer. An upper surface of the ceramic substrate has a positive electrode pad, a negative electrode pad, and a plurality of chip attachment areas. The chip fixing areas each have a connecting layer and a chip fixing layer. The connecting layer and the chip fixing layer are spaced from each other. The ceramic substrate has vertical vias. The vertical vias are electrically connected between the chip fixing areas and the conductive circuit layer and between the conductive circuit layer and the positive electrode pad and the negative electrode pad, respectively. The integrated metal retaining layer is disposed on the upper surface of the ceramic substrate. The integrated metal retaining layer surrounds a periphery of a single or the plurality of chip attachment areas and is spaced from the chip attachment areas. The integrated metal retaining layer has a thickness greater than that of the chip fixing zones.
    Another aspect of the present invention relates to a method for preparing a ceramic module for the integrated packaging of power semiconductors. The preparation process includes the following steps:
    (1) providing a ceramic substrate and perforating the ceramic substrate;
    (2) metallizing the upper and lower surfaces of the ceramic substrate;
    (3) sticking a dry film, exposing, developing and galvanizing the ceramic substrate with the metallized upper and lower surfaces to form a positive electrode pad, a negative electrode pad, a connection layer, a fixing layer of chips, an integrated metal retaining bottom layer, a conductive circuit layer, a bottom heat dissipation layer, and vertical vias;
    (4) sticking a dry film, exposing, developing and galvanizing the upper and lower surfaces of the ceramic substrate again, so that the integrated metal retaining lower layer and the lower heat dissipation layer are each galvanized and thickened to obtain an integrated metal retaining layer and a heat dissipation layer;
    (5) removing the films and etching the ceramic substrate; and (6) applying an insulating material to the bottom surface of the ceramic substrate to form an insulating layer.
    An additional aspect of the present invention relates to a process for preparing a ceramic module for the integrated packaging of power semiconductor. The preparation process includes the following steps:
    (1) providing a ceramic substrate and perforating the ceramic substrate;
    (2) metallizing the upper and lower surfaces of the ceramic substrate;
    (3) sticking a dry film, exposing, developing and galvanizing the ceramic substrate with the metallized upper and lower surfaces to form a positive electrode pad, a negative electrode pad, a connection layer, a fixing layer of chips, an integrated metal retaining bottom layer, a conductive circuit layer, a bottom heat dissipation layer, and vertical vias;
    (4) sticking a dry film, exposing, developing and galvanizing the upper and lower surfaces of the ceramic substrate again, so that the integrated metal retaining lower layer and the lower heat dissipation layer are each galvanized and thickened to obtain an integrated metal retaining layer and a heat dissipation layer;
    (5) sticking a dry film, exposing, developing and galvanizing the top surface of the ceramic substrate again, so that part of the integrated metal retaining layer is galvanized and thickened to obtain a stepped surface and a layer of staircase;
    (6) removing the films and etching the ceramic substrate; and (7) applying an insulating material to the bottom surface of the ceramic substrate to form an insulating layer.
    Compared with the state of the art, the present invention has obvious advantages and beneficial effects. These can be determined more precisely from the above technical solutions:
    The use of the metal retaining layer integrated on the upper surface of the ceramic substrate and the formation of cavities around the chip fixing zones make it possible to hermetically seal the semiconductor chip. The use of the heat dissipation layer on the lower surface of the ceramic substrate makes it possible to rapidly convey the heat generated by the semiconductor chip to the outside to improve the heat dissipation performance. The use of the conductive circuit layer and vertical interconnection holes allows a serial and parallel multi-chip connection to be made on the lower surface of the ceramic substrate. The present invention makes it possible to produce an integrated multi-chip packaging of power semiconductors having the advantages of good thermoelectric separation, of high air tightness, of low thermal resistance, of a compact structure, etc. . The manufacturing process is simple and the consistency of the product is high.
    Brief description of the drawings [fig. 1]: perspective view according to a preferred embodiment of the present invention;
    [Fig.2]: bottom view according to the preferred embodiment of the present invention; and [fig.3]: partial sectional view according to the preferred embodiment of the present invention.
    DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION Please refer to Figures 1 to 3, illustrating a specific structure of a preferred embodiment of the present invention, comprising a ceramic substrate 10 and a layer integrated metal retainer 20.
    The lower surface of the ceramic substrate 10 comprises a conductive circuit layer 31, an insulating layer 32, and a heat dissipation layer 33. The insulating layer 32 completely covers the conductive circuit layer 31. The heat dissipation layer 32 is located on the area outside the conductive circuit layer 31 and spaced from the conductive circuit layer 31. The thickness of the heat dissipation layer 33 is not less than the total thickness of the layer conductive circuit 31 and insulating layer 32. In this embodiment, both the conductive circuit layer 31 and the heat dissipation layer 33 are made of galvanized copper material. The thickness of the heat dissipation layer 33 is greater than the thickness of the conductive circuit layer 31. The insulating layer 32 is made of white or green ink. The thickness of the insulating layer 32 is less than the thickness of the heat dissipation layer 33.
    The upper surface of the ceramic substrate 10 comprises a positive electrode pad 34, a negative electrode pad 35, and a plurality of chip fixing zones 40. Each of the chip fixing zones 40 has a layer connection 41 and a chip fixing layer 42. The connection layer 41 and the chip fixing layer 42 are spaced from each other. In this embodiment, the positive electrode pad 34 and the negative electrode pad 35 are located on the periphery of the upper surface of the ceramic substrate 10, and are spaced from the integrated metal retaining layer 20. The plurality chip attachment areas 40 are arranged in an assembly.
    The ceramic substrate 10 has vertical interconnection holes 36. The vertical interconnection holes 36 are electrically connected between the chip fixing areas 40 and the conductive circuit layer 31 and between the conductive circuit layer 31 and the positive electrode pad 34 and the negative electrode pad 35, respectively. In other words, the connection layers 41 and the chip fixing layers 42 are electrically connected to the conductive circuit layer 31 through the corresponding vertical interconnection holes 36, respectively; and the positive electrode pad 34 and the negative electrode pad 35 are respectively connected to the conductive circuit layer 31 through the corresponding vertical interconnection holes 36, thus constituting a circuit structure in series and in parallel. In this embodiment, the vertical interconnection holes 36 are filled with metal or external galvanized copper. In addition, the ceramic substrate 10 is made of aluminum oxide ceramic (A1 2 O 3 ), aluminum nitride ceramic (AIN), silicon nitride ceramic (Si 3 N 4 ) or carbide ceramic. but not limited to silicon (SiC). Aluminum oxide ceramic is inexpensive. Aluminum nitride ceramic has a good heat dissipation effect. Ceramic with silicon nitride has a high resistance. Silicon carbide ceramic has a moderate price, with good heat dissipation.
    The integrated metal retaining layer 20 is disposed on the upper surface of the ceramic substrate 10. The integrated metal retaining layer 20 surrounds the periphery of a single or the plurality of chip fixing areas 40 and is spaced chip fixing areas 40. The thickness of the integrated metal retaining layer 20 is greater than the thickness of the chip fixing areas 40. In this embodiment, the integrated metal retaining layer 20 is made of galvanized copper material. In addition, the integrated metal retaining layer 20 has a plurality of cavities 21, and the plurality of cavities 21 are also arranged in an assembly. The chip attachment areas 40 are located in the corresponding cavities 21, respectively. In other words, the peripheral edge of the cavity 21 is set back to form a stepped surface 202.
    The present invention also relates to a method for preparing a ceramic module for the integrated packaging of power semiconductor, comprising the following steps:
    (1) providing a ceramic substrate 10 and perforating the ceramic substrate 10;
    (2) metallizing the upper and lower surfaces of the ceramic substrate 10;
    (3) sticking a dry film, exposing, developing and galvanizing the ceramic substrate 10 with the metallized upper and lower surfaces to form a positive electrode pad 34, a negative electrode pad 35, a connection layer 41, a chip fixing layer 42, an integrated metal retaining bottom layer 201, a conductive circuit layer 31, a bottom heat dissipation layer 301, and vertical through holes 36;
    (4) sticking a dry film, exposing, developing and galvanizing the upper and lower surfaces of the ceramic substrate 10 again, so that the integrated metal retaining lower layer 201 and the lower heat dissipation layer 301 are each galvanized and thickened to obtain an integrated metal retaining layer 20 and a heat dissipation layer 33;
    (5) removing the films and etching the ceramic substrate (10); and (6) applying an insulating material on the lower surface of the ceramic substrate 10 to form an insulating layer 32.
    The method further comprises step (7): plating of gold / silver (not shown) on the surface of each metal layer of the ceramic substrate (10), namely, the surfaces of the pad d positive electrode 34, the negative electrode pad 35, the connection layer 41, the chip fixing layer 42, the integrated metal retaining layer 20 and the heat dissipation layer 33 are plated with gold / money.
    The present invention also relates to another process for preparing a ceramic module for integrated packaging of power semiconductors, comprising the following steps:
    (1) providing a ceramic substrate 10 and perforating the ceramic substrate 10;
    (2) metallizing the upper and lower surfaces of the ceramic substrate 10;
    (3) sticking a dry film, exposing, developing and galvanizing the ceramic substrate 10 with the metallized upper and lower surfaces to form a positive electrode pad 34, a negative electrode pad 35, a connection layer 41, a chip fixing layer 42, an integrated metal retaining bottom layer 201, a conductive circuit layer 31, a bottom heat dissipation layer 301, and vertical through holes 36;
    (4) sticking a dry film, exposing, developing and galvanizing the upper and lower surfaces of the ceramic substrate 10 again, so that the integrated metal retaining lower layer 201 and the lower heat dissipation layer 301 are each galvanized and thickened to obtain an integrated metal retaining layer 20 and a heat dissipation layer 33;
    (5) sticking a dry film, exposing, developing and galvanizing the upper surface of the ceramic substrate 10 again, so that part of the integrated metal retaining layer 20 is galvanized and thickened to obtain a stepped surface 202 and a step layer 203;
    (6) removing the films and etching the ceramic substrate (10); and (7) applying an insulating material on the lower surface of the ceramic substrate 10 to form an insulating layer 32.
    The method further comprises step (8): plating of gold / silver (not shown) on the surface of each metal layer of the ceramic substrate (10), namely, the surfaces of the pad d positive electrode 34, the negative electrode pad 35, the connection layer 41, the chip fixing layer 42, the integrated metal retaining layer 20 and the heat dissipation layer 33 are plated with gold / money.
    DESCRIPTION OF ELEMENTS IN THE DRAWINGS 10 ceramic substrate integrated metal retaining layer cavity
    201 integrated metal retaining bottom layer
    202 stepped area
    203 staircase layer conductive circuit layer insulating layer heat dissipation layer positive electrode pad negative electrode pad vertical via hole
    301 bottom heat dissipation layer chip fixing areas connection layer chip fixing layer
    权利要求:
    Claims (6)
    [1" id="c-fr-0001]
    [Claim 1] [Claim 2] [Claim 3]
    claims
    Ceramic module for integrated packaging of power semiconductors, characterized in that it comprises a ceramic substrate (10) and an integrated metallic retaining layer (20); a lower surface of the ceramic substrate (10) comprising a conductive circuit layer (31), an insulating layer (32) and a heat dissipation layer (33), the insulating layer (32) completely covering the conductive circuit layer ( 31), the heat dissipation layer (32) being located on an area outside the conductive circuit layer (31) and spaced from the conductive circuit layer (31), the heat dissipation layer (33) having a thickness not less than a total thickness of the conductive circuit layer (31) and the insulating layer (32); an upper surface of the ceramic substrate (10) having a positive electrode pad (34), a negative electrode pad (35) and a plurality of chip fixing areas (40), the chip fixing areas ( 40) each having a connecting layer (41) and a chip fixing layer (42), the connecting layer (41) and the chip fixing layer (42) being spaced from each other; the ceramic substrate (10) having vertical interconnection holes (36), the vertical interconnection holes (36) being electrically connected between the chip fixing zones (40) and the conductive circuit layer (31) and between the conductive circuit layer (31) and the positive electrode pad (34) and the negative electrode pad (35) respectively; the integrated metal retaining layer (20) being disposed on the upper surface of the ceramic substrate (10), the integrated metal retaining layer (20) surrounding a periphery of one or more of the chip fixing areas ( 40) and being spaced from the chip fixing zones (40), the integrated metal retaining layer (20) having a thickness greater than that of the chip fixing zones (40).
    Ceramic module according to claim 1, characterized in that the ceramic substrate (10) is made of aluminum oxide ceramic, aluminum nitride ceramic, silicon nitride ceramic, or silicon carbide ceramic .
    Ceramic module according to claim 1, characterized in that both the conductive circuit layer (31) and the heat dissipation layer (33) are made of galvanized copper material, and [Claim 4] [ Claim 5] [Claim 6] [Claim 7] [Claim 8] the thickness of the heat dissipation layer (33) is greater than the thickness of the conductive circuit layer (31).
    Ceramic module according to claim 1, characterized in that the integrated metal retaining layer (20) is made of galvanized copper material.
    Ceramic module according to claim 1, characterized in that the positive electrode pad (34) and the negative electrode pad (35) are located on a periphery of the upper surface of the ceramic substrate (10) and are spaced from the integrated metal retaining layer (20).
    Ceramic module according to claim 1, characterized in that the vertical interconnection holes (36) are filled with metal or external galvanized copper.
    Process for the preparation of the ceramic module according to claim
    1, characterized in that it comprises the following stages:
    (1) providing the ceramic substrate (10) and perforating the ceramic substrate (10);
    [2" id="c-fr-0002]
    (2) metallizing the upper and lower surfaces of the ceramic substrate (10);
    [3" id="c-fr-0003]
    (3) sticking a dry film, exposing, developing and galvanizing the ceramic substrate (10) with the metallized upper and lower surfaces to form the positive electrode pad (34), the negative electrode pad (35), the connection layer (41), chip fixing layer (42), an integrated metal retaining bottom layer (201), the conductive circuit layer (31), a bottom heat dissipation layer (301), and the vertical via holes (36);
    [4" id="c-fr-0004]
    (4) sticking a dry film, exposing, developing and galvanizing the upper and lower surfaces of the ceramic substrate (10) again, so that the lower integrated metal retaining layer (201) and the lower heat dissipation layer ( 301) are each galvanized and thickened to obtain the integrated metal retaining layer (20) and the heat dissipation layer (33);
    [5" id="c-fr-0005]
    (5) removing the films and etching the ceramic substrate (10); and (6) applying an insulating material to the bottom surface of the ceramic substrate (10) to form the insulating layer (32).
    Preparation process according to claim 7, characterized in that it further comprises the step (7): plating of gold / silver on the respective surfaces of the positive electrode pad (34), the pad d negative electrode [Claim 9] [Claim 10] (35), the connection layer (41), the chip fixing layer (42), the integrated metal retaining layer (20) and the heat dissipation layer (33 ).
    Process for the preparation of the ceramic module according to claim
    1, characterized in that it comprises the following stages:
    (1) providing the ceramic substrate (10) and perforating the ceramic substrate (10);
    (2) metallizing the upper and lower surfaces of the ceramic substrate (10);
    (3) sticking a dry film, exposing, developing and galvanizing the ceramic substrate (10) with the metallized upper and lower surfaces to form the positive electrode pad (34), the negative electrode pad (35), the connection layer (41), chip fixing layer (42), an integrated metal retaining bottom layer (201), the conductive circuit layer (31), a bottom heat dissipation layer (301), and the vertical via holes (36);
    (4) sticking a dry film, exposing, developing and galvanizing the upper and lower surfaces of the ceramic substrate (10) again, so that the lower integrated metal retaining layer (201) and the lower heat dissipation layer ( 301) are each galvanized and thickened to obtain the integrated metal retaining layer (20) and the heat dissipation layer (33);
    (5) sticking a dry film, exposing, developing and galvanizing the upper surface of the ceramic substrate (10) again, so that part of the integrated metal retaining layer (20) is galvanized and thickened to obtain a surface stepped (202) and a stepped layer (203);
    [6" id="c-fr-0006]
    (6) removing the films and etching the ceramic substrate (10); and (7) applying an insulating material to the bottom surface of the ceramic substrate (10) to form the insulating layer (32).
    Preparation process according to claim 9, characterized in that it further comprises the step (8): plating of gold / silver on the respective surfaces of the positive electrode pad (34), the pad d negative electrode (35), the connection layer (41), the chip fixing layer (42), the integrated metal retaining layer (20) and the heat dissipation layer (33).
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    法律状态:
    2020-07-06| PLFP| Fee payment|Year of fee payment: 3 |
    2021-03-26| TP| Transmission of property|Owner name: XI'AN BAIXIN CHUANGDA ELECTRONIC TECHNOLOGY CO, CN Effective date: 20210218 |
    2021-07-23| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    CN201710571008.7A|CN107369741A|2017-07-13|2017-07-13|LED support module with integrated metal box dam and preparation method thereof|
    CN1710571008|2017-07-13|
    CN201711176148.0A|CN108109986A|2017-07-13|2017-11-22|A kind of power semiconductor integrated form encapsulation ceramic module and preparation method thereof|
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