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    • 专利摘要:
    A semiconductor-on-insulator substrate (100) having at least: a support layer (102); a superficial layer (104) of semiconductor; - a buried dielectric layer (106) disposed between the support layer and the surface layer; a layer (108) for trapping electrical charges placed between the buried dielectric layer and the support layer, and comprising at least one polycrystalline semiconductor material and / or a phase-change material; wherein the electric charge trapping layer has at least one first region (110) and at least one second region (112) disposed adjacent to one another in the plane of the electric charge trapping layer, the the first region being in an at least partially recrystallized state and having a lower electrical resistivity than the material of the second region.
    公开号:FR3067517A1
    申请号:FR1755314
    申请日:2017-06-13
    公开日:2018-12-14
    发明作者:Yann Lamy；Lamine Benaissa；Etienne Navarro
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    TECHNICAL AREA AND PRIOR ART
    The invention relates to the field of substrates RFSOI (Silicon on insulator Radio Frequency, or "Radio-Frequency Silicon On Insulator" in English) and FDSOI (Silicon on insulator completely deserted, or "Fully Depleted Silicon On Insulator" in English), as well as that of semiconductor devices produced from such substrates.
    There are two distinct types of SOI substrates used for different electronic applications:
    - RFSOI substrates used for Radio Frequency (RF) applications such as Front End modules;
    - FDSOI substrates used for high performance and low consumption digital applications, and allowing the production of FDSOI type components.
    These two types of SOI substrates have specific characteristics adapted for one or the other of these two distinct applications.
    Thus, an FDSOI substrate comprises a fine silicon surface layer (for example of thickness equal to 10 nm), a buried dielectric layer, or BOX, fine (for example of thickness equal to 20 nm), and support layer, or layer massive, of lightly doped silicon (for example with a resistivity between approximately 0.1 and 1 Ohm.cm) placed under the BOX to allow a rear polarization of the FDSOI transistors produced in this substrate. The mobility in the channel of such an FDSOI transistor can therefore be controlled from the rear face of the substrate which forms a rear gate of the transistor, thanks to a weakly resistive lateral contact accessible from the front face of the substrate and which is connected to the portion of doped silicon located under the BOX of the transistor. This rear bias makes it possible to modulate the performance (in particular the speed) and / or the consumption of the transistors produced, in particular their threshold voltage. This however requires having good electrical conduction between the front face contact and the doped area formed under the BOX of the transistor.
    On the contrary, an RFSOI substrate comprises a highly resistive support layer (for example with a resistivity greater than about 0.5 kO.cm, or even greater than 1 kO.cm) in order to limit losses in the RF or passive components produced on or in such a substrate.
    A major problem encountered for RF applications is the presence of a parasitic conduction layer formed by parasitic free charges generated by the presence of fixed charges in the BOX of the substrate. This is particularly detrimental to the linearity of RF signals which have significant powers (0 to 30 dBm), and creates crosstalk.
    To solve this problem, it is possible to have a layer of trapping of electric charges, called “trap rich” layer, just under the BOX in order to capture the free charges and thus considerably reduce, even cancel, the formation of the parasitic conductive layer. . This charge trapping layer is formed, typically by PECVD, LPCVD deposition or by epitaxy, on the support layer just before the RFSOI substrate manufacturing process. The RF components are then fabricated on the RFSOI substrate as on a conventional SOI substrate.
    Advantageously, the charge trapping layer is formed by a deposit of polysilicon. Compared to other techniques, polysilicon achieves a high density of traps ("trap" in English), a high resistivity (between about 5 and 10 kOhm.cm), and good thermal stability at high temperature (up to at around 1100 ° C) compatible with the implementation of a CMOS process, while offering the possibility of depositing or growing a silicon oxide to passivate the layer and thus make possible the direct bonding of this oxide layer during the manufacture of this substrate.
    An example of a method for producing an RFSOI substrate comprising a layer for trapping electrical charges is described in document EP 1 665 367 A1.
    Document FR 2 973 158 A1 also describes a technique for stabilizing the grains of the charge trapping layer by inserting a thin dielectric layer between the charge trapping layer and the support layer to prevent or delay the unwanted recrystallization of the layer. charge trapping which is responsible for the lower efficiency of this layer.
    In all cases, the charge trapping layer of an RFSOI substrate is formed uniformly on the substrate and is designed to be thermally stable.
    With the next technological nodes (22 nm and less), and the emergence of the Internet of Things (loT, or “Internet Of Things” in English) and 5G (fifth generation of standards for mobile telephony), it It would be very interesting to have an efficient SOI substrate both for active devices of the FDSOI type and for passive devices and RF devices.
    However, the presence of a very resistive charge trapping layer, useful for passive or RF components, is incompatible with a rear polarization of FDSOI transistors and which requires conduction between the isolation zones and under the BOX in order to drive tensioned by the rear face of the rear grids of the FDSOI transistors.
    In addition, a shaping of the charge trapping layer which would consist of forming this layer only at the locations provided for the RF or passive components during the manufacture of the SOI substrate is not industrially feasible since this supposes that the Founder or the manufacturer of integrated circuit give the manufacturer of the substrate which will be used for the manufacture of integrated circuits the detail and the plan of the circuits which will be carried out.
    STATEMENT OF THE INVENTION
    An object of the present invention is to provide a new substrate of the semiconductor on insulator type having the advantages of an RFSOI substrate comprising a layer for trapping electrical charges, while being compatible with the technology.
    FDSOI and in particular with a rear polarization of the FDSOI components, in particular of FDSOI transistors, produced on this substrate.
    For this, the invention provides a substrate of the semiconductor on insulator type, comprising at least:
    - a support layer;
    - a surface layer of semiconductor;
    - a buried dielectric layer disposed between the support layer and the surface layer;
    an electric charge trapping layer disposed between the buried dielectric layer and the support layer, and comprising at least one polycrystalline semiconductor material and / or a phase change material;
    wherein the electric charge trapping layer has at least a first region and at least a second region arranged side by side in the plane of the electric charge trapping layer, the material of the first region being in an at least partially recrystallized state and having an electrical resistivity lower than that of the material of the second region.
    This substrate comprises a layer for trapping electrical charges, the structure of which makes it possible to associate the benefits of an RFSOI substrate and those of an FDSOI substrate within the same substrate, via the production of distinct regions within the layer. trapping electrical charges, these distinct regions having different properties depending on whether they are intended to be part of an RFSOI region of the substrate or an FDSOI region of the substrate.
    The use of a polycrystalline semiconductor and / or of a phase change material to form the layer for trapping electrical charges makes it possible to achieve a local adjustment, for example via the use of a laser, of the properties of this layer, and thus delimit different regions within this layer according to the FDSOI or RFSOI properties sought for each region.
    Indeed, in the trapping layer of electrical charges, the traps are mainly formed at the grain boundaries, where they are associated with the dangling bonds of the material. Depletion regions and potential barriers are formed around the grains to compensate for the charges trapped at the grain boundaries. To increase the density of traps and therefore the efficiency of the charge trapping layer, the surface of the grain boundaries must be maximized, which involves reducing the grain size. For example, polysilicon grains of size between approximately 100 nm and 150 nm make it possible to find the nominal resistivity of the silicon which is of the order of 5 kOhm.cm.
    The uniformity of the grain size, the columnar structure and the morphology of the grains within the charge trapping layer, along its thickness, strongly influence the efficiency of reduction of the parasitic currents. The thickness of the charge trapping layer also plays an important role.
    In addition, the resistivity of the charge trapping layer and its property of reduction of parasitic conduction decrease as the grain size increases. By locally heating the first region or regions of the electric charge trapping layer, recrystallization of the material within this or these first regions occurs, causing an increase in the grain size of the material within this or these first regions . This reduces the electrical resistivity of this recrystallized material and makes this first region or regions suitable for FDSOI technology, while keeping the other region or regions of the substrate compatible with RFSOI technology.
    This local adjustment can correspond to a significant heating of the material of the first region, modifying the structure of the grains which compose it and lowering its resistivity.
    The part of the substrate including the first region of the layer for trapping electrical charges and the portions of the other layers of the substrate located on this first region form a part of the substrate suitable for producing FDSOI components. That including the second region of the layer for trapping electrical charges and the portions of the other layers of the substrate located on this second region form a part of the substrate suitable for producing RF and / or passive components.
    The substrate therefore comprises a layer for trapping electrical charges which can be inactivated or locally modulated as a function of the characteristics sought within different regions of the substrate, in particular the regions intended to receive active zones of FDSOI components. The regions on which passive and / or RF components (inductance, transmission lines, etc.) are intended to be produced are arranged opposite a functional "trap rich" region, that is to say in which the material of the electric charge trapping layer is in a non-recrystallized state.
    This substrate therefore comprises, under the buried dielectric layer, very resistive regions without parasitic conduction zone at the place where the layer for trapping electrical charges is functional (material not recrystallized), as well as regions which are electrically less resistant to place where the properties of the trapping layer of electric charges have been modified, allowing the realization of a rear polarization of the active components produced in these regions.
    The recrystallization of the material of the first region of the layer for trapping electrical charges is carried out such that the structure of the grains of this material is modified (increase in the size of the grains), causing the resistivity of the material of this first region to decrease. Recrystallization can be carried out until the recrystallized material from the first region is monocrystalline.
    Thanks to the lower electrical resistivity of the material of the first region of the electric charge trapping layer, this material can be used to form a rear polarization grid of FDSOI components produced at this first region.
    The plane of the layer for trapping electrical charges corresponds to the main plane of this layer and which is parallel to the interfaces between the different layers of the substrate.
    The layer for trapping electrical charges can comprise at least one of the following materials: polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, phase change material.
    The layer for trapping electrical charges is advantageously sensitive in absorption to lighting (that is to say capable of absorbing the electrons from this lighting) using at least one wavelength at which the material of the support layer and / or the material of the surface layer is transparent, for example a wavelength of the infrared range. This is the case when polycrystalline germanium and / or polycrystalline SiGe and / or a phase change material is used to form the electric charge trapping layer and silicon is used to form the support layer and / or the surface layer, the lighting used emitting one or more wavelengths of the infrared range.
    Advantageously, the material of the surface layer has a melting temperature higher than the recrystallization temperature of the trapping layer of electric charges in order to have a good selectivity of the heating when this heating of the trapping layer of electric charges is made through the surface layer. This is the case when the surface layer comprises monocrystalline silicon which has a high melting temperature (approximately 1415 ° C.) and when the trapping layer of electrical charges comprises polycrystalline silicon (recrystallization temperature comprised between approximately 800 ° C. and 900 ° C), polycrystalline Ge, polycrystalline SiGe, or a phase change material. This can also be applied between the material of the layer for trapping electrical charges and that of the support layer when the lighting is produced through the support layer.
    A phase change material has the advantage of having a reversibility of its crystalline state, and can pass quickly from the crystalline state to the amorphous state or vice versa.
    A thickness of each of the grains of the material of the first region may be equal to, or close to, the thickness of the layer for trapping electrical charges, which makes it possible to obtain good electrical conductivity of the material of the first region.
    The electrical charge trapping layer may include a phase change material which is in the crystalline state in the first region and in the amorphous state in the second region.
    The substrate may further comprise a thermal absorption layer disposed between the layer for trapping electrical charges and the support layer. In this case, the main function of the thermal absorption layer is to absorb radiation used to heat and recrystallize the material of the first region of the electric charge trapping layer.
    In that case :
    the layer for trapping electrical charges can comprise polycrystalline silicon, and
    - The thermal absorption layer may include polycrystalline germanium or polycrystalline silicon-germanium or a phase change material.
    When the thermal absorption layer comprises polycrystalline germanium or polycrystalline silicon-germanium or a phase change material, the material of this layer which receives the thermal radiation is also at least partially recrystallized.
    The invention also relates to a semiconductor device comprising at least:
    - a substrate as described above;
    a first isolation trench crossing at least the surface layer, the buried dielectric layer and the layer for trapping electrical charges of the substrate and separating the first and second regions of the layer for trapping electrical charges of the substrate one of the 'other;
    - an FDSOI component produced in a first portion of the surface layer of the substrate which is superimposed on the first region of the layer for trapping electrical charges of the substrate;
    a passive and / or RF component produced in and / or on a second portion of the surface layer of the substrate which is superimposed on the second region of the layer for trapping electrical charges of the substrate.
    The device can also include:
    a doped well formed in a portion of the support layer of the substrate and disposed against the first region of the layer for trapping electrical charges of the substrate;
    a second insulation trench crossing at least the surface layer, the buried dielectric layer and the layer for trapping electrical charges of the substrate and separating first and second parts of the first region of the layer for trapping electrical charges of the substrate which are electrically connected to each other by the doped well, the first part of the first region of the layer for trapping electrical charges of the substrate forming a rear polarization plane, or rear grid, of the FDSOI component;
    an electrical contact passing through the surface layer and the buried dielectric layer, in contact with the second part of the first region of the layer for trapping electrical charges of the substrate.
    The electrical contact makes it possible to apply an electrical potential to the first part of the first region of the electric charge trapping layer via the doped well and the second part of the first region of the electric charge trapping layer.
    The invention also relates to a method for producing a substrate of the semiconductor on insulator type, comprising the production of a stack comprising:
    - a support layer;
    - a surface layer of semiconductor;
    - a buried dielectric layer disposed between the support layer and the surface layer;
    an electric charge trapping layer disposed between the buried dielectric layer and the support layer, and comprising at least one polycrystalline semiconductor material and / or a phase change material;
    and further comprising the realization, in the trapping layer of electrical charges, of at least a first region and of at least a second region arranged one next to the other in the plane of the trapping layer of electrical charges, during which the material of the first region is at least partially recrystallized such that its electrical resistivity is lower than that of the material of the second region.
    The realization of the first region may include the implementation of a local annealing by laser of the material of the first region.
    The laser emits light whose wavelength is absorbed by the trapping layer of electrical charges. The effect of the laser is to perform a significant annealing close to the melting temperature of the material of the electric charge trapping layer and to increase the grain size of this material. This increase in grain size of the material of the electric charge trapping layer decreases the density of traps at the interface with the buried dielectric layer. This makes it possible, for example, to reduce or even destroy the effect of trapping electrical charges at the place where the FDSOI components will be manufactured, while also guaranteeing good resistivity and very good linearity in the areas of the dedicated substrate. for RF.
    The surface layer of the substrate can comprise monocrystalline silicon, and, during the local annealing by laser of the material of the first region, the laser can be focused on the first region of the layer for trapping electrical charges through the surface layer and the buried dielectric layer of the substrate.
    The wavelength of the light emitted by the laser can be chosen such that this light is not absorbed by the silicon of the surface layer, for example in the infrared range.
    As a variant, during the local annealing by laser of the material of the first region, the laser can be focused on the first region of the layer for trapping electrical charges at least through the support layer of the substrate.
    In this case, the buried dielectric layer can serve as a thermal barrier so as not to heat the surface layer.
    According to another variant, the substrate can further comprise a thermal absorption layer disposed between the trapping layer of electrical charges and the support layer, and the laser can be focused on a region of the thermal absorption layer superimposed on the first region of the layer for trapping electrical charges and at least through the support layer of the substrate.
    The invention also relates to a method for producing a semiconductor device comprising at least:
    - the implementation of a process for producing a substrate of the semiconductor on insulator type as described above;
    the production, through at least the surface layer, the buried dielectric layer and the layer for trapping electrical charges of the substrate, of at least a first isolation trench between the first and second regions of the layer for trapping charges substrate electrics;
    the production of at least one FDSOI component in a first portion of the surface layer of the substrate which is superimposed on the first region of the layer for trapping electrical charges of the substrate;
    the production of at least one passive and / or RF component in and / or on a second portion of the surface layer of the substrate which is superimposed on the second region of the layer for trapping electrical charges of the substrate.
    In this process, the components, that is to say the FDSOI component (s) and the passive and / or RF component (s), can be produced before or after having produced, in the layer for trapping electrical charges, the first and second regions. When the components are produced before the first and second regions of the electric charge trapping layer are produced, the recrystallization (for example exposure to laser radiation) of the material of the first region or regions is carried out through the rear face of the substrate so as not to damage the components.
    The method can also include:
    - The realization of a second insulation trench crossing at least the surface layer, the buried dielectric layer and the layer of trapping of electric charges of the substrate and separating from the first and second parts of the first region of the layer of trapping of charges substrate electrics;
    an implantation of dopants in a portion of the support layer of the substrate which is disposed against the first region of the layer for trapping electrical charges of the substrate, forming a doped well electrically connecting together the first and second parts of the first region of the electrical charge trapping layer of the substrate;
    - The realization of an electrical contact crossing the surface layer and the buried dielectric layer, in contact with the second part of the first region of the layer of trapping of electric charges of the substrate, and allowing the control of a rear polarization plane of the FDSOI component formed by the first part of the first region of the electrical charge trapping layer of the substrate.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings in which:
    - Figure 1 shows a semiconductor type substrate on insulator, object of the present invention, according to a first embodiment;
    - Figures 2A and 2B show the steps of a method for producing a substrate of the semiconductor on insulator type, object of the present invention, according to the first embodiment;
    - Figures 3 and 4 show a semiconductor on insulator type substrate, object of the present invention, respectively according to a second and a third embodiment;
    FIGS. 5A to 5D represent the steps of a method for producing a semiconductor device, object of the present invention, comprising FDSOI components and RF and / or passive components produced on the same substrate also object of the present invention.
    Identical, similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    Reference is first made to FIG. 1 which schematically represents a substrate 100 of the semiconductor on insulator type according to a first embodiment.
    The substrate 100 includes a support layer 102 serving as a mechanical holding layer. So that this layer 102 is compatible with the production of passive and / or RF components, that is to say that it is compatible with RFSOI technology, this layer 102 comprises a material known as “high resistivity”, it that is to say, the electrical resistivity of which is greater than approximately 0.5 kO.cm, and preferably greater than approximately 1 kQ.cm or even even greater than approximately 3 kQ.cm. In the first embodiment described here, the layer 102 comprises silicon. The electrical resistivity of this silicon is for example equal to approximately 5 kQ.cm. The thickness of layer 102 is several hundred microns.
    The substrate 100 also includes a surface layer 104 of semiconductor. Electronic components are intended to be produced on and / or in this layer 104. In the first embodiment described here, the layer 104 comprises monocrystalline silicon. The substrate 100 is therefore a substrate of silicon on insulator type, or SOI. The thickness of layer 104 is for example between approximately 10 nm and 20 nm.
    The substrate 100 also comprises a buried dielectric layer 106, or BOX, disposed between the layers 102 and 104. This layer 106 comprises for example SiO 2 and has a thickness of between approximately 10 nm and 100 nm, and advantageously between approximately 10 nm and 25 nm.
    The substrate 100 also comprises a layer 108 for trapping electrical charges, or so-called “trap rich” layer, disposed between the layers 102 and 106. The layer 108 has a thickness of between approximately 200 nm and 500 nm.
    In the first embodiment, the layer 108 comprises a polycrystalline semiconductor material. This polycrystalline semiconductor can correspond to polycrystalline silicon, or polycrystalline germanium, or else polycrystalline SiGe.
    The layer 108 is not homogeneous because it comprises at least a first region 110 and at least a second region 112 arranged one next to the other in the plane of the layer 108 (that is to say the side by side in a plane parallel to the plane (X, Y) shown in Figure 1). These regions 110, 112 each occupy the entire thickness of the layer 108, that is to say have a thickness equal to that of the layer 108.
    The first region or regions 110 comprise the polycrystalline semiconductor mentioned above but which has undergone at least partial recrystallization. The second region or regions 112 comprise this same polycrystalline semiconductor but which has not undergone this recrystallization step. The electrical resistivity of the material of the first regions 110 is lower than that of the material of the second regions 112.
    The recrystallization undergone by the material of the first region or regions 110 increases the grain size of this material, reducing or eliminating the capacity for trapping electrical charges of the material of this or these first region (s) 110 and reducing the electrical resistivity of this material. In the first region (s) 110, the grains of the material of layer 108 have a thickness equal to the thickness of layer 108.
    As a variant of the first embodiment described above, the layer 108 for trapping electrical charges can comprise not a polycrystalline semiconductor material, but a phase change material. In this case, this material is in the crystalline state in the first region (s) 110 and in the amorphous state in the second region (s) 112.
    Such a phase change material corresponds for example to a material from the chalcogenide family, for example Ge x Sb Y Te with 0 <X <1, 0 <Y <letX + Y = l.
    A phase change material can be deposited with conventional microelectronics tools, for example by PVD, PECVD deposition, in the amorphous or crystalline phase and with a thickness of between approximately 100 nm and several microns.
    In the amorphous state, phase change materials have a very high resistivity, of the order of 1 MQ.cm. In the crystalline state, these materials are electrically conductive and have a very low resistivity, of the order of a few mQ.cm.
    These phase change materials can pass from the amorphous to the crystalline state in a reversible manner as a function of the annealing profile (duration and intensity) applied to them. The transition from the amorphous state to the crystalline state generally takes place between about 500 ° C and 700 ° C.
    A process for producing the substrate 100 is described in connection with FIGS. 2A and 2B.
    A stack of layers 102, 108, 106 and 104 is first produced, as shown in FIG. 2A. These layers can be formed by implementing several successive deposition steps.
    An at least partial recrystallization of the material of the layer 108 is then implemented at the level of the part or parts of the layer 108 intended to form the first region or regions 110. This recrystallization here corresponds to a local annealing implemented using a laser whose beam is shown in FIG. 2B and referenced 114. In the example of FIG. 2B, this annealing is carried out through a front face 116 of the substrate 100, that is to say that the beam laser passes through layers 104 and 106 before reaching layer 108. As a variant, the recrystallization of the material of the first region or regions 110 can be carried out through a rear face 118 of the substrate 100, the laser beam 114 passing through the support layer 102 before reaching the material of layer 108.
    The laser used can correspond to a pulsed laser, which makes it possible to locally increase the power to reach the temperatures required for recrystallization of the material of layer 108. The laser emission device used has for example the following properties:
    - wavelength: 1.035 pm,
    - output power: 40 W,
    - energy: 40 pJ (at 1MHz),
    - frequency: 1 MHz,
    - beam diameter at 1 meter: 2.7 mm +/- 0.3.
    The laser is for example used here such that the beam entering the layers of the substrate 100 has a diameter of between approximately 0.5 mm and 2 mm, which makes it possible to obtain good resolution of the regions 110, 112 therebetween. Advantageously, the wavelength of the laser beam used can be between approximately 1.3 μm and 1.4 μm, the difference in absorption between the Ge and the Si of such a wavelength being very significant. .
    By way of example, a layer 108 of Ge having a thickness equal to 200 nm placed under a layer 106 of SiO 2 with a thickness equal to 25 nm and under a layer 104 of Si with a thickness equal to 20 nm can temperature of approximately 900 ° C., ie a temperature close to the melting point of germanium and allowing partial recrystallization of germanium from layer 108, using a laser pulse of 500 pJ with a duration of 1.45 ns generated by the transmitting device described above. With such a laser pulse, the layer 104 does not exceed a temperature of 500 ° C., therefore not altering the silicon of the layer 104, in particular thanks to the thermal barrier formed by the layer 106 between the layers 104 and 108.
    In this first embodiment, the layer for trapping electrical charges 108 has both properties for trapping electrical charges, and is also sensitive to the laser used for recrystallization of the material of the first regions 110.
    Polycrystalline germanium has the advantage of strongly absorbing the wavelengths of the infrared range (wavelength greater than about lpm). Thus, a laser emitting infrared light can be used to produce the different regions 110, 112 within the layer 108, these wavelengths being little or not absorbed by the silicon which can form the layer 104. C this is also the case when a phase change material is used to form the layer 108 and the layer 104 comprises silicon.
    Furthermore, germanium has a direct gap, which promotes the absorption of a light excitation and a lower melting temperature than silicon, which promotes the phase change of layer 108 when it contains germanium.
    The charge trapping effect obtained with polycrystalline germanium is on the other hand less significant than when polycrystalline silicon is used.
    Polycrystalline SiGe can thus be used in layer 108 in order to stabilize the material, to create conditions more favorable to the growth of the material of layer 108 and to increase the resistivity of the final material obtained (in comparison with germanium).
    Ge and / or SiGe and / or polycrystalline Si can be deposited in existing frames of microelectronics of PECVD, LPCVD or epitaxy type.
    As a variant of the method described above, it is possible to simultaneously use several laser beams focused at a same point on the layer 108 to recrystallize the material of the first regions 110. Thus, when these beams pass through the front face 116 of the substrate 100 and that they pass through different portions of layer 104, this limits heating of layer 104. This variant can also be applied when the beams enter the device 100 through the rear face 118 formed by layer 102.
    FIG. 3 represents the substrate 100 according to a second embodiment.
    In this second embodiment, the substrate 100 comprises, in addition to the layers 102, 104, 106 and 108 previously described in connection with the first embodiment, a thermal absorption layer 120 disposed between the layer
    108 for trapping electrical charges and the support layer 102. The material of the layer 120 is chosen such that it is sensitive to the wavelength of the laser used to recrystallize the material of the first regions 110. The layer 120 is in contact thermally with layer 108. In addition, layer 120 is preferably very electrically insulating, or at least semiconductor with reduced electronic mobility, so as not to add electrical conductivity under layer 106. Layer 120 is also compatible with the front end processes of microelectronics which will be used to produce the components on the substrate 100. Finally, the layer 120 is thick enough to capture the thermal energy necessary for recrystallization of the material of the layer 108, for example between about 30 nm and 3 pm.
    Advantageously, the layer 108 comprises polycrystalline silicon, and the layer 120 comprises polycrystalline germanium or polycrystalline SiGe or a material with phase change.
    In this second embodiment, the functions of thermal absorption and trapping of electrical charges are dissociated and distributed over the two layers 108 and 120. Thus, the material of layer 108 can be chosen for these excellent charge trapping properties. electrical without necessarily being very absorbent with respect to the radiation used for recrystallization, and that of the layer 120 is chosen to be very sensitive to heating. This second embodiment makes it possible to optimize the effect of the annealing carried out by laser by increasing the absorption of the laser radiation.
    As a variant, the layer 120 may correspond to a stack of several layers.
    FIG. 4 represents the substrate 100 according to a third embodiment.
    In this third embodiment, the substrate 100 comprises, in addition to the layers 102, 104, 106, 108 and 120 previously described, a buffer layer 122. This buffer layer 122 makes it possible to limit or on the contrary to amplify the recrystallization of the material layer 108. This buffer layer 122 comprises for example an oxide or a nitride of a semiconductor. This layer 122 can be produced as described in document FR 2 973 158. It is also possible that the buffer layer 122 is used in the substrate 100 without the thermal layer 120.
    Whatever the embodiment of the substrate 100, this substrate 100 is intended to be used to produce a semiconductor device 200 comprising both FDSOI components and passive and / or RF components.
    A method of producing such a device 200 from the substrate 100 is described below in connection with FIGS. 5A to 5D. The substrate 100 used in this method corresponds to the substrate 100 according to the first embodiment described above. Alternatively, it is however possible to use the substrate according to one of the other embodiments previously described.
    When the substrate 100 comprises several first regions 110 and / or several second regions 112, the steps described below can be implemented for several or each of the first regions 110 and / or second regions 112
    As shown in FIG. 5A, first isolation trenches 202 are formed through the surface layer 104, the buried dielectric layer 106 and the charge trapping layer 108. These first trenches 202 make it possible to electrically separate, within the charge trapping layer 108, the first region 110 with respect to the second region 112.
    One or more second insulation trenches 204 are also made through the layers 104, 106 and 108 in order to electrically isolate, within the first region 110 crossed by this or these second trenches 204, a first part 206 opposite - screw of a second part 208 of the first region 110.
    An implantation of dopants is then carried out in a portion 210 of the layer 102 which is arranged against the first region 110 of the layer 108, under the latter. In FIG. 5B, the dopant implantation beams are symbolized by arrows referenced 212. The portion 210 of semiconductor having undergone this implantation of dopants forms a doped well electrically connecting the first and second parts 206, 208 of the first region 110.
    Components 214 of the FDSOI type, in particular FDSOI transistors, are produced in a first portion of the surface layer 104 which is superimposed on the first region 110 of the layer 108, and in particular in a first portion 216 of the surface layer which is superimposed to the first part 206 of the first region 110 and which is well suited to the production of FDSOI components thanks to the previous recrystallization of the first region 110. These components 214 are connected to electrical interconnection levels formed within dielectric layers intermetal 218 (Figure 5C).
    At least one electrical contact 219 is made through the parts of the layers 104 and 106 lying above the second part 208 of the first region 110. This electrical contact 219 provides electrical access to the first part 206 of the first region 110, via the doped portion 210 and the second part 208 of the first region 110, and to apply the desired electrical potential to this first part 206 of the first region 110 which forms a rear bias plane of the FDSOI transistors 214.
    Finally, as shown in FIG. 5D, passive and / or RF components 220 are produced on and / or in a second portion 222 of the surface layer 104 located above the second region 112 forming an RFSOI part of the substrate 100. In FIG. 5D, these components 220 correspond to a back-end inductance or to RF lines produced above the part of the intermetal dielectric layers 218 located on the second portion 222.
    In the method described above in connection with FIGS. 5A-5D, the recrystallization of the material of the first regions 110 is carried out before the various components are produced on the substrate 100. As a variant, it is possible that this recrystallization is carried out after having produced the various components on the substrate 100. In this case, recrystallization is carried out from the rear face of the substrate 100, that is to say using one or more laser beams passing through the rear face of the layer 102, in order to do not damage the components already present on the front face of the substrate 100.
    权利要求:
    Claims (14)
    [1" id="c-fr-0001]
    1. Substrate (100) of semiconductor type on insulator, comprising at least:
    - a support layer (102);
    - a surface layer (104) of semiconductor;
    - a buried dielectric layer (106) disposed between the support layer (102) and the surface layer (104);
    - a layer (108) for trapping electrical charges disposed between the buried dielectric layer (106) and the support layer (102), and comprising at least one polycrystalline semiconductor material and / or a phase change material;
    wherein the electric charge trapping layer (108) comprises at least a first region (110) and at least a second region (112) arranged one next to the other in the plane of the layer (108) of trapping of electric charges, the material of the first region (110) being in an at least partially recrystallized state and having an electrical resistivity lower than that of the material of the second region (112).
    [2" id="c-fr-0002]
    2. The substrate (100) according to claim 1, in which the layer (108) for trapping electrical charges comprises at least one of the following materials: polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, phase change material.
    [3" id="c-fr-0003]
    3. Substrate (100) according to one of the preceding claims, in which the layer (108) for trapping electrical charges comprises a phase change material which is in the crystalline state in the first region (110) and the amorphous state in the second region (112).
    [4" id="c-fr-0004]
    4. Substrate (100) according to one of the preceding claims, further comprising a thermal absorption layer (120) disposed between the layer (108) for trapping electrical charges and the support layer (102).
    [5" id="c-fr-0005]
    5. Substrate (100) according to claim 4, in which:
    the layer (108) for trapping electrical charges comprises polycrystalline silicon, and
    - The thermal absorption layer (120) comprises polycrystalline germanium or polycrystalline silicon-germanium or a phase change material.
    [6" id="c-fr-0006]
    6. Semiconductor device (200) comprising at least:
    - a substrate (100) according to one of claims 1 to 5;
    - a first isolation trench (202) crossing at least the surface layer (104), the buried dielectric layer (106) and the layer (108) for trapping electrical charges of the substrate (100) and separating the first and second regions (110, 112) of the layer (108) for trapping electrical charges of the substrate (100) from one another;
    - an FDSOI component (214) produced in a first portion (216) of the surface layer (104) of the substrate (100) which is superimposed on the first region (110) of the layer (108) for trapping electrical charges of the substrate (100);
    - a passive and / or RF component (220) produced in and / or on a second portion (222) of the surface layer (104) of the substrate (100) which is superimposed on the second region (112) of the layer (108 ) trapping electrical charges of the substrate (100).
    [7" id="c-fr-0007]
    7. Semiconductor device (200) according to claim 6, further comprising:
    - A doped well formed in a portion (210) of the support layer (102) of the substrate (100) and disposed against the first region (110) of the layer (108) for trapping electrical charges of the substrate (100);
    - a second insulation trench (204) crossing at least the surface layer (104), the buried dielectric layer (106) and the layer (108) for trapping electrical charges of the substrate (100) and separating first and second parts (206, 208) of the first region (110) of the layer (108) for trapping electrical charges of the substrate (100) which are electrically connected to each other by the doped well, the first part (206) the first region (110) of the layer (108) for trapping electrical charges of the substrate (100) forming a rear polarization plane of the FDSOI component (214);
    - an electrical contact (219) passing through the surface layer (104) and the buried dielectric layer (106), in contact with the second part (208) of the first region (110) of the layer (108) for trapping electrical charges of the substrate (100).
    [8" id="c-fr-0008]
    8. Method for producing a semiconductor on insulator type substrate (100), comprising making a stack comprising:
    - a support layer (102);
    - a surface layer (104) of semiconductor;
    - a buried dielectric layer (106) disposed between the support layer (102) and the surface layer (104);
    - a layer (108) for trapping electrical charges disposed between the buried dielectric layer (106) and the support layer (102), and comprising at least one polycrystalline semiconductor material and / or a phase change material;
    and further comprising the realization, in the layer (108) of trapping electrical charges, of at least a first region (110) and at least a second region (112) arranged one next to the other in the plane of the layer (108) for trapping electrical charges, during which the material of the first region (110) is at least partially recrystallized such that its electrical resistivity is lower than that of the material of the second region (112 ).
    [9" id="c-fr-0009]
    9. The method of claim 8, wherein the production of the first region (110) comprises the implementation of a local annealing by laser of the material of the first region (110).
    [10" id="c-fr-0010]
    10. The method of claim 9, wherein the surface layer (104) of the substrate (100) comprises monocrystalline silicon, and wherein, during the local annealing by laser of the material of the first region (110), the laser is focused on the first region (110) of the layer (108) for trapping electrical charges through the surface layer (104) and the buried dielectric layer (106) of the substrate (100).
    [11" id="c-fr-0011]
    11. The method of claim 9, wherein, during the local laser annealing of the material of the first region (110), the laser is focused on the first region (110) of the layer (108) for trapping electrical charges at less through the support layer (102) of the substrate (100).
    [12" id="c-fr-0012]
    12. The method of claim 11, wherein the substrate (100) further comprises a thermal absorption layer (120) disposed between the layer (108) for trapping electrical charges and the support layer (102), and in which the laser is focused on a region of the thermal absorption layer (120) superimposed on the first region (110) of the layer (108) for trapping electrical charges and at least through the support layer (102) of the substrate ( 100).
    [13" id="c-fr-0013]
    13. Method for producing a semiconductor device (200) comprising at least:
    - the implementation of a process for producing a substrate (100) of semiconductor on insulator type according to one of claims 8 to 12;
    the production, through at least the surface layer (104), the buried dielectric layer (106) and the layer (108) for trapping electrical charges of the substrate (100), of at least a first isolation trench ( 202) between the first and second regions (110, 112) of the layer (108) for trapping electrical charges of the substrate (100);
    - The production of at least one FDSOI component (214) in a first portion (216) of the surface layer (104) of the substrate (100) which is superimposed on the first region (110) of the trapping layer (108) electrical charges of the substrate (100);
    - The production of at least one passive and / or RF component (220) in and / or on a second portion (222) of the surface layer (104) of the substrate (100) which is superimposed on the second region (112) of the layer (108) for trapping electrical charges of the substrate (100).
    [14" id="c-fr-0014]
    14. The method according to claim 13, further comprising:
    - The production of a second insulation trench (204) crossing at least the surface layer (104), the buried dielectric layer (106) and the layer (108) for trapping electrical charges of the substrate (100) and separating first and second parts (206, 208) of the first region (110) of the electric charge trapping layer (108) of the substrate (100);
    an implantation of dopants in a portion (210) of the support layer (102) of the substrate (100) which is disposed against the first region (110) of the layer (108) for trapping electrical charges of the substrate (100), forming a doped well electrically connecting together the first and second parts (206, 208) of the first region (110) of the layer (108) for trapping electrical charges of the substrate (100);
    - Making an electrical contact (219) passing through the surface layer (104) and the buried dielectric layer (106), in contact with the second part (208) of the first region (110) of the layer (108) of trapping of electrical charges of the substrate (100), and allowing the control of a rear polarization plane of the FDSOI component (214) formed by the first part (206) of the first region (110) of the trapping layer (108) electric charges of the substrate (100).
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    引用文献:
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    法律状态:
    2018-12-14| PLSC| Publication of the preliminary search report|Effective date: 20181214 |
    2020-06-30| PLFP| Fee payment|Year of fee payment: 4 |
    2021-06-30| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1755314|2017-06-13|
    FR1755314A|FR3067517B1|2017-06-13|2017-06-13|SUBSTRATE SOI COMPATIBLE WITH RFSOI AND FDSOI TECHNOLOGIES|FR1755314A| FR3067517B1|2017-06-13|2017-06-13|SUBSTRATE SOI COMPATIBLE WITH RFSOI AND FDSOI TECHNOLOGIES|
    US16/003,199| US10586810B2|2017-06-13|2018-06-08|SOI substrate compatible with the RFSOI and FDSOI technologies|
    US16/774,143| US11171158B2|2017-06-13|2020-01-28|SOI substrate compatible with the RFSOI and FDSOI technologies|
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