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    • 专利摘要:
    Process for producing a display device (1000), comprising at least the implementation of the following steps: - production of a matrix of LEDs (100) each comprising electrodes accessible from a rear face of the matrix of LEDs and light emitting surfaces from a front face of the LED array; - Securing, on the back side of the LED matrix, a stack of layers comprising at least one semiconductor layer, a gate dielectric layer and a layer of gate conductive material; - Production, from the stack of layers, of an electronic control circuit electrically coupled to the electrodes of the LEDs, comprising the production of FET transistors whose active areas (216) are formed in the semiconductor layer and whose the grids (224) are formed in the gate dielectric and gate conductive material layers.
    公开号:FR3065322A1
    申请号:FR1753334
    申请日:2017-04-18
    公开日:2018-10-19
    发明作者:Ivan-Christophe Robin；Hubert Bono；Maud Vinet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Holder (s): COMMISSIONER OF ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.
    Extension request (s)
    Agent (s): BREVALEX Limited liability company.
    54) METHOD FOR PRODUCING A LED MATRIX DISPLAY DEVICE.
    FR 3 065 322 - A1 (5 /) Method for producing a display device (1000), comprising at least the implementation of the following steps:
    - Realization of an LED array (100) each comprising electrodes accessible from a rear face of the LED array and light emission surfaces from a front face of the LED array;
    - Fastening, on the rear face of the LED array, of a stack of layers comprising at least one layer of semiconductor, a layer of gate dielectric and a layer of grid conductive material;
    - production, from the stack of layers, of an electronic control circuit electrically coupled to the electrodes of the LEDs, comprising the production of FET transistors, of which active zones (216) are formed in the semiconductor layer and of which the grids (224) are formed in the layers of gate dielectric and gate conductive material.
    1000
    308
    i
    METHOD FOR PRODUCING A LED MATRIX DISPLAY DEVICE
    DESCRIPTION
    TECHNICAL AREA AND PRIOR ART
    The invention relates to the field of LED display devices ("Light-Emitting Diode", or light-emitting diode), and in particular that of microLED micro-screens (pLEDs).
    For the manufacture of a high-luminance micro-screen, one approach consists in using a matrix of LEDs produced from GaN, InGaN, InGaP or even InGaAlP, each having dimensions, in a plane substantially parallel to the emission surface of the LEDs, of the order of 10 μm. Each of the LEDs is individually addressed by an electronic control circuit to which the matrix of LEDs is coupled.
    In general, the electronic control circuit integrates FET transistors (field effect transistors, for example of the MOSFET type) produced in an active layer of semiconductor such as silicon. Such an electronic control circuit includes, for example, for the control of each of the LEDs, one or two FET transistors controlled via matrix addressing.
    In the case of LEDs made from nitride, the supply voltage required for the transistors is approximately 5 V. The resistance in the on state required for these transistors is low, generally less than approximately 10 kO for a surface of around 1 pm 2 . A low dispersion (of the order of less than 1%) on the threshold voltage Vt of the transistors is also required. Such performance may also be required for other types of transistors.
    To fulfill these criteria, the transistors of the electronic control circuit are generally produced in an active layer of monocrystalline silicon. The conventional processes for producing the transistors include steps involving significant thermal budgets, which can reach, for example, temperatures of the order of 1000 ° C. However, the LED array cannot withstand such temperatures.
    To respond to this problem and not expose the LED array to such temperatures, a coupling between an electronic control circuit already produced and the LED array also produced can be carried out by transferring in an aligned manner and hybridizing the electronic circuit of control on the LED array, via the use of micro-tubes.
    Although this solution avoids exposing the LED array to excessively high temperatures, the electronic components of the electronic control circuit associated with each pixel of the LED array must be aligned with the LED of this pixel with an accuracy of less than approximately 1 pm. This transfer is therefore complex to implement because of the very numerous connections (for example of the order of 10 6 ) to align and to carry out during this transfer between the LED array and the electronic control circuit. In addition, it is very difficult to produce micro-tubes with such small dimensions.
    Finally, the different coefficients of thermal expansion of the materials to be hybridized represent an important constraint to be managed during this hybridization. In fact, because the hybridization is carried out at a temperature for example greater than about 100 ° C., the differences in coefficient of thermal expansion between the materials accentuate the alignment offset, in particular at the periphery of these elements. In addition, there appears on cooling a thermal stress which can go as far as the rupture of all of the substrates.
    STATEMENT OF THE INVENTION
    An object of the present invention is to provide a method for producing an LED matrix display device which does not have the drawbacks of the methods of the prior art, that is to say avoiding the exposure of the LED array at too high temperatures while eliminating the alignment and connection problems encountered during postponement and hybridization of the electronic control circuit on the LED array via micro-tubes and / or in the presence of materials with different coefficients of thermal expansion.
    For this, the present invention proposes a method for producing a display device, comprising at least the implementation of the following steps:
    - production of an LED array each comprising electrodes accessible from a rear face of the LED array and light emission surfaces from a front face of the LED array;
    - Fastening, on the rear face of the LED array, of a stack of layers comprising at least one layer of semiconductor, a layer of gate dielectric and a layer of grid conductive material;
    - production, from the stack of layers, of an electronic control circuit electrically coupled to the electrodes of the LEDs, comprising the production of FET transistors comprising active areas and gates, the active areas being formed in the semi layer -conductor and the grids being formed in the layers of grid dielectric and of grid conductive material.
    Because the materials used to make the gates of the transistors of the electronic control circuit (that is to say the layers of gate dielectric and of gate conductive material) are already present in the stack of layers transferred to the matrix of LEDs, this matrix of LEDs is not exposed to the significant temperatures encountered during the deposition of these materials, such as for example the formation of the gate dielectric by oxidation which involves temperatures higher than approximately 700 ° C or 800 ° C.
    In addition, this method overcomes the alignment constraints because in this method using several substrates (at least a first substrate for producing the LED array and a second substrate on which the stack of layers used to produce the electronic control circuit) integrated sequentially, the electronic control circuit is produced after having transferred the stack of layers used to produce it on the rear face of the LED array. Thus, the alignment can be carried out easily at the time of the lithography of the transistors and not at the time of the joining of the stack of layers with the matrix of LEDs. The precision of the steps implemented to position and produce the FET transistors on the rear face of the LEDs thanks to the lithography implemented is for example of the order of 5 nm for advanced lithography of the DUV type (deep UV). This lithographic precision is much higher than the precision that can be achieved with a method comprising a joining implemented after having individually produced the LED arrays and the control circuits (precision greater than 1 μm).
    This excellent alignment obtained between the LED array and the electronic control circuit also makes it possible to produce the electronic control circuit with very high densities of transistors, for example at least eight transistors per LED when the electronic control circuit does not comprise any capacitances, or at least four transistors for LEDs addressed by PWM (“Puise Width Modulation”, or pulse width modulation).
    The fact of producing the electronic control circuit after having transferred the stacking of layers to the rear face of the LED array reduces the problems linked to the connection between materials having different coefficients of thermal expansion.
    In addition, the fact that the LED electrodes are accessible from the rear face of the matrix and that the emission surfaces of the LEDs are located on the front face of the matrix makes it possible to have no masking of the light emission of the LEDs by the electrodes
    The expression “gate dielectric layer” designates at least one layer of at least one material capable of forming the gate dielectrics of the transistors F ET.
    The expression “layer of gate conductive material” designates at least one layer of at least one material capable of forming the gate conductors of the FET transistors.
    According to a first variant, the gate dielectric material can correspond to a dielectric material with high permittivity, also called “high-k” dielectric (relative dielectric permittivity greater than that of SiO 2 , ie greater than 3.9). , such as HfO 2 , for example, and the gate conductive material may correspond to a metal.
    According to a second variant, the gate dielectric material can correspond to an oxide such as SiO 2 and the gate conductive material can correspond to polysilicon.
    The realization of the LED array can include the implementation of the following steps, for each of the LEDs:
    - Production of a mesa structure comprising at least first and second semiconductor portions of different dopings and forming a p-n junction;
    - production of a first electrode arranged on the mesa structure and electrically connected to the first portion of semiconductor;
    - Production of a second electrode placed next to the mesa structure and electrically connected to the second portion of semiconductor by means of at least part of the lateral faces of the second portion of semiconductor.
    The first portion of semiconductor may correspond to that located on the side of the rear face of the LED array
    The second electrode can be electrically isolated from the first semiconductor portion by dielectric portions covering at least the lateral flanks of the first semiconductor portion. This location of the electrical insulation portions only on the lateral flanks of the mesa structure of each LED makes it possible to improve the ratio between the active surface of the LEDs (surface occupied by the pn junctions) and the total surface on which the LEDs are produced. , and therefore to increase the integration of these LEDs given the small footprint of the electrical insulation portions of this structure which are strictly vertical (parallel to the lateral sides of the mesa structures of the LEDs. In addition, this strong integration of the portions d electrical insulation also has the advantage of minimizing the current densities obtained in the electrodes of the LEDs, and therefore of reducing the heating by Joule effect within the display device.
    This structure also makes it possible to have very good electrical contact between the second electrode and the p-n junctions of the LEDs, and thus optimizes the access resistances on the side of this second electrode.
    The expression “mesa structure” designates the fact that the LEDs are produced in the form of a stack of a semiconductor of a first type of conductivity, for example of type n, and of a semiconductor d a second type of conductivity, opposite to the first type of conductivity, for example of the p type, a junction zone being present between these two semiconductors, and that this stack is etched over at least part of its height in the form of 'islands to make the semiconductor of the first type of conductivity accessible. These islets are called mesas.
    The semiconductor layer used to produce the active areas of the transistors of the electronic control circuit may comprise SiGe with a germanium content of between approximately 10% and 50%. This germanium content can advantageously be between approximately 30% and 40%, for example equal to approximately 34%, which makes it possible to have a good compromise between the recrystallization speed during recrystallization of the source and drain of the transistors and the simplicity of the production process. This advantageous germanium content also makes it possible to reduce the maximum temperature reached during the manufacturing process of the control circuit because the temperature at which recrystallization annealing of the source and drain of the transistors is carried out is reduced when the percentage of Ge in the channel is important.
    The joining of the stack of layers on the rear face of the matrix of LEDs may include the implementation of a direct bonding between a first layer of oxide forming part of the stack of layers and a second layer of oxide arranged on the rear face of the LED array. With such direct bonding between the stack of layers and the LED array, heterogeneous cold integration of the layers of the gate stack of the transistors is achieved since it can be implemented at a temperature between room temperature and about 400 ° C, unlike the processes of the prior art which requires the implementation of an electronic circuit - LEDs matrix connection at higher temperatures and which then poses problems due to the materials with coefficients of thermal expansion different who are in contact with each other.
    Direct bonding between the stack of layers and the LED array can be achieved other than by oxide-oxide bonding, for example via layers of SiO 2 planarized by chemical mechanical polishing.
    During direct oxide-oxide bonding, the method may also comprise, before the stacking of layers (serving for the production of the electronic control circuit) on the rear face of the LED array, stacking layers by implementing the following steps:
    - Production of the gate dielectric layer on the semiconductor layer which corresponds to the surface layer of a substrate of the semiconductor on insulator type, for example SOI (“Silicon On Insulator”, or silicon on insulator);
    - Production of the layer of gate conductive material on the layer of gate dielectric;
    - Realization of a hard mask layer on the layer of grid conductive material;
    - Production of a mechanical holding layer on the hard mask layer;
    - Removal of a thick, or massive, layer of semiconductor from the semiconductor on insulator type substrate;
    and in which a buried dielectric layer, or BOX (“Buried Oxide”) of the substrate of semiconductor type on insulator can form the first oxide layer intended for the implementation of direct bonding.
    The semiconductor layer of the stack of layers can comprise a crystalline semiconductor, and the active zones of the FET transistors can be formed in the semiconductor layer at least via the implementation of an ion implantation in parts of the active zones of the FET transistors intended to form the source and drain of the FET transistors, making the semiconductor of said parts partially amorphous, then of a solid phase recrystallization annealing of the active zones of the FET transistors.
    The ion implantation is implemented here such that part of the thickness of the parts of implanted active zones remains crystalline and forms, during recrystallization annealing, a seed for recrystallization of the source and drain of the FET transistors. For this, the energy and the dose used during the ion implantation can be adapted so that there remains a portion of crystalline semiconductor within the source and drain at the end of this implantation.
    Recrystallization annealing can be carried out at a temperature between about 450 ° C and 600 ° C.
    By producing the source and drain by partial amorphization followed by recrystallization annealing, the electronic control circuit is obtained without implementing techniques involving significant thermal budgets.
    Recrystallization annealing can be carried out conventionally in an oven. Alternatively, recrystallization annealing can be carried out by exposing the source and drain of the FET transistors to a laser source, which makes it possible to confine the heat provided by the laser source in the layers used to produce these sources and drain.
    The production of the FET transistors may include the implementation of the following steps:
    - lithography and etching of the gate dielectric layers and of the gate conductive material and of the semiconductor layer such that the remaining portions of the semiconductor layer form the active zones of the FET transistors;
    - Lithography and etching of the gate dielectric and gate conductive material layers such that remaining portions of the gate dielectric and gate conductive material layers form the gates of the FET transistors;
    - production of spacers against the side walls of the grids of the FET transistors;
    and the parts of the active areas of the FET transistors intended to form the source and drain of the FET transistors correspond to parts of the active areas of the FET transistors not covered by the gates and the spacers.
    The production of the electronic control circuit may further include, after the production of the FET transistors, the production of electrical contacts electrically connected to the FET transistors (in particular to the gate, source and drain contacts) and / or to the electrodes of the LEDs. These electrical contacts can be made within one or more metal levels formed on the rear face of the LED array.
    The method may also include, between the joining of the stack of layers on the rear face of the LED array and the production of the electronic control circuit, the implementation of the following steps:
    - Making cavities through one face of a cover layer, each cavity being intended to be placed opposite one of the LEDs;
    - deposition of a reflective material at least against internal side walls of the cavities;
    - Securing said face of the cover layer against the front face of the array of LEDs such that each cavity is arranged facing at least one of the LEDs;
    and the method can also comprise, after the realization of the electronic control circuit, a step of thinning the cover layer eliminating bottom walls of the cavities of the cover layer located opposite the light emission surfaces of the LEDs.
    Thus, reflective elements are formed between the light emission surfaces of neighboring LEDs making it possible to limit crosstalk, or “crosstalk”, between these LEDs.
    In this case, the method uses three separate substrates sequentially integrated to produce the display device.
    The method may further include, after the step of thinning the cover layer, a step of making phosphors between the remaining portions of the cover layer, against the front face of the LED array and facing the surfaces of LED emission. Thus, it is possible to adjust and / or modify the range of wavelengths ίο of the light emitted by the LEDs. These phosphors can be different from one LED to another.
    As a variant, the method may further comprise, between the joining of the stack of layers on the rear face of the LED array and the production of the electronic control circuit, the production of an optical filtering structure capable of filtering at at least part of the wavelengths intended to be emitted by at least part of the LEDs, on the front face of the LED array and facing the light emission surfaces of said part of the LEDs.
    In this case, the production of the optical filtering structure may include at least the implementation of the following steps:
    - depositing a layer of a first filtering material on the front face of the LED array;
    - Etching the layer of the first filter material such that the remaining portions of the first filter material are arranged facing the light emission surfaces of a portion of the LEDs, called first LEDs;
    - Production of first portions of transparent dielectric material between the remaining portions of the first filter material;
    depositing a second layer of filtering material on the remaining portions of the first filtering material and on the first portions of transparent dielectric material;
    - Etching of the second layer of filtering material such that the remaining portions of the second filtering material are arranged facing the emission surfaces of other LEDs, called second LEDs;
    - Production of second portions of transparent dielectric material between the remaining portions of the second filtering material;
    and the method may further comprise depositing an optically transparent mechanical retaining layer against the optical filtering structure prior to the production of the electronic control circuit.
    Thus, it is possible to produce, on the front face of the matrix of LEDs, portions of filtering material modifying the range of wavelengths emitted by the LEDs. These filtering materials can be different from one LED to another. In addition, the number of different filtering materials formed in the optical filtering structure may be different from two (in the case of the example given above), and more generally be greater than or equal to 1.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given for purely indicative and in no way limiting, with reference to the appended drawings in which:
    - Figures IA - IG represent the steps implemented for the production of an LED array of a display device, object of the present invention, according to a particular embodiment;
    - Figures 2A - 2C show the steps implemented for the production and transfer of a stack of layers on an LED array of a display device, object of the present invention, according to a particular embodiment;
    - Figures 3A - 3D show the steps implemented for the production and securing of a cover layer against a matrix of LEDs of a display device, object of the present invention, according to a particular embodiment;
    - Figures 4A - 4D show the steps implemented to form the FET transistors of the electronic control circuit of a display device, object of the present invention, according to a particular embodiment;
    - Figure 4E shows an embodiment of a part of an electronic circuit for controlling a display device, object of the present invention, according to a particular embodiment;
    - Figures 4F and 4G show steps implemented during the production of phosphors of a display device, object of the present invention, according to a particular embodiment;
    - Figures 5A - 5D show the steps implemented to form an optical filtering structure of a display device, object of the present invention, according to a particular embodiment.
    Identical, similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    We first refer to Figures IA to IG which represent the steps implemented to produce an array of LEDs 100, which here correspond to microLEDs, intended to be used for the production of a display device 1000 for example of the micro-display type. This matrix of LEDs 100 is intended to form a matrix of pixels of the display device 1000. In these figures, a single LED 100 is shown entirely.
    The LEDs 100 are produced from layers formed on a substrate 102, comprising for example silicon, AI 2 O 3 or sapphire, and intended to serve as a support for the growth of these layers. As shown in FIG. IA, these layers formed on the substrate 102 correspond to a layer of n-doped semiconductor 104, for example GaN. This layer 104 comprises a first n-type part 106 and a second n-doped part 108. As a variant, these two parts 106, 108 of the layer 104 may correspond to two layers of different materials, with for example the first part 106 comprising GaN and the second part 108 comprising InGaN. According to another variant, whether the two parts 106, 108 correspond to two layers of different materials or to a single layer of the same material, the doping levels of the two parts 106, 108 may or may not be similar.
    The first part 106 of the layer 104 corresponds for example to a buffer layer comprising an unintentionally doped semiconductor, the role of which is to allow growth thereon of semiconductor with good crystalline quality. The concentration of donors in the first part 106 is for example of the order of 10 17 donors / cm 3 . The second part 108 of the layer 104 corresponds for example to a portion of intentionally doped n-type semiconductor with a concentration of donors for example between approximately 10 18 and 10 2 ° donors / cm 3 .
    The thickness of layer 104 is for example between approximately nm and 10 μm.
    The layers formed on the substrate 102 also comprise, on the layer 104, several layers 110 intended to form the emissive active areas of the LEDs 100. The layers 110 correspond to one or more emissive layers each forming a quantum well, comprising for example 1 'InGaN, and each being arranged between two barrier layers comprising for example GaN. The layers 110, that is to say the emissive layer or layers and the barrier layers, comprise intrinsic semiconductor materials, that is to say unintentionally doped (of concentration in residual donors n n id for example equal to approximately 10 17 donors / cm 3 , or between approximately 10 15 and 10 18 donors / cm 3 ). The thickness of the or each of the emissive layers is for example equal to approximately 3 nm and more generally between approximately 0.5 nm and 10 nm, and the thickness of each of the barrier layers is for example between approximately 1 nm and 25 nm. The number of quantum wells formed by the layers 110 is for example between approximately 1 and 50.
    A p 112 doped semiconductor layer is disposed on the layers 110 and is intended to form, with the layer 104, the pn junctions of the LEDs 100. Like the layer 104, the semiconductor of the layer 112 is for example GaN. The p doping of the layer 112 corresponds for example to a concentration of acceptors of between approximately 10 17 and 10 20 acceptors / cm 3 . The thickness of the layer 112 is for example between approximately 20 nm and 10 μm.
    An electrically conductive layer 114 is then formed on the layer 112, and is intended to form part of the contact electrodes of the p regions of the LEDs 100, that is to say the anodes. The layer 114 is optically reflective, that is to say is capable of reflecting a major part (for example at least 80%) of the light arriving thereon and which corresponds to the light emitted from the active emissive areas of the LEDs 100 and which is intended to be emitted by the LEDs 100. The layer 114 comprises for example aluminum and / or silver, or more generally any electrically conductive and optically reflective material, and its thickness is for example between approximately 50 nm and 1 pm.
    A layer 116 intended to serve for producing a hard mask is then formed on the layer 114 (FIG. 1B). A first etching is implemented through part of the thickness of the layer 116, defining locations 118 for the anodes of the LEDs 100.
    Lithography and etching are then implemented in order to structure the layer 116 according to the desired hard mask pattern 122, making it possible then to form by etching, in the layer 114, portions 120 each intended to form a part of the electrode of contact of the region p of one of the LEDs 100 (figure IC). The pattern of this engraving corresponds to that of a mesa structure, that is to say a stack in the form of an island, which each of the LEDs 100 is intended to form. Each mesa structure of each LED 100 has for example a section, in a plane parallel to the face of the layer 112 on which the portions 120 rest, in the form of a disc. Each of the mesa structures can therefore form a cylindrical island. Each of the portions 120 is covered by a portion of the hard mask 122 in which one of the locations 118 is present. The material of the hard mask 122 (and therefore of the layer 116) is advantageously a dielectric carrying out a passivation of the portions 120, such as for example SiO 2 .
    This etching according to the pattern of the hard mask 122, and therefore according to the pattern of the mesa structures of the LEDs 100, is then extended in the layers 112, 110 and part of the thickness of the layer 104, forming for each LED 100 a remaining portion 124 of p-doped semiconductor, one or more active emissive zones 126 and a portion 128 of n-doped semiconductor. This etching is for example of the RIE ICP chlorinated type, that is to say a reactive ion etching. This etching is stopped at a depth level located in the layer 104, that is to say such that a portion of this layer 104 is kept vertically in line with each of the etched zones of the stack. When the layer 104 is formed from the two parts 106 and 108, the portion of the layer 104 which is kept at each of the engraved zones of the stack comprises at least one portion of the part 106. In the example of the figure 1D, this etching is stopped at a level located in the part 108 of the layer 104 such that the part 106 and part of the thickness of the part 108 are not engraved. The thickness of the etched material of the layer 104 is for example between approximately 200 nm and 5 μm, and depends on the initial thickness of the layer 104. As a variant, this etching can be stopped at the upper face of the part 106, that is to say through the entire thickness of the part 108 and such that the part 106 is not engraved. According to another variant, this etching can be stopped at a level located in the part 106 such that only part of the thickness of the part 106 is not engraved.
    The choice of the depth of this etching depends on the choice of the height of the lateral flanks of the mesa structure intended to be covered by dielectric portions 130 then formed against the lateral flanks of the etched parts of the layers of the stack (see FIG. 1D) . These dielectric portions 130 therefore cover here only the lateral flanks of the portions 122, 120, 124 and 128 and the emissive active areas 126.
    The dielectric portions 130 are for example produced by first depositing a passivation layer, comprising for example SiN, with a conformal thickness for example of between approximately 3 nm and 100 nm, on the portions 122, along the side walls mesas structures (formed by the elements 122, 120, 124, 126 and 128), as well as on the non-etched parts of the layer 104. An anisotropic etching, for example a dry etching, is then implemented such that only the parts of this layer covering the lateral flanks of the mesas structures is preserved and forms the dielectric portions 130.
    The etching of the layer 104 is then extended through the remaining thickness of this layer, according to the pattern defined by the portions 122 and by the dielectric portions 130 and forming, for each of the LEDs 100, a remaining portion 132 of the layer 104 disposed under the portion 128 and under the dielectric portions 130. Unlike the portion 128 whose lateral flanks are covered by the dielectric portions 130, those of the portion 132 are not covered by the dielectric portions 130. This etching is for example of type RIE ICP chlorinated. This etching is stopped on the front face of the substrate 102.
    This etching forms spaces 134 between the mesas structures adjacent to the LEDs 100 and which are intended for producing the cathodes of the LEDs 100. The distance between two mesa structures of neighboring LEDs 100 is for example greater than or equal to approximately 50 nm. The minimum distance between two neighboring mesa LED structures 100 is defined by the minimum resolution of the lithography used.
    As shown in FIGS. 1E, the first etching previously implemented through part of the thickness of the layer 116 and defining the locations 118 is extended through the rest of the thickness of the portions of the hard mask 122 so that the locations 118 form accesses to the conductive portions 120. These accesses are here produced in two etching steps so that the lithography defining the locations 118 is carried out on a flat surface, which makes it possible to achieve the desired resolution. These locations 118 are intended for producing the anodes of the LEDs 100.
    An electrically conductive layer 136 is then deposited in the spaces 134, on the mesa structures, against the lateral flanks of these mesa structures and finally in the locations 118. This layer 136 is in particular intended to form a contact layer for the cathodes of the LEDs 100, at the level of the lateral flanks of the portions 132. The layer 136 preferably corresponds to a stack of several materials: titanium, aluminum, as well as a growth layer for the subsequent deposition of the conductive material (s) of the anodes and cathodes of the LEDs 100, this growth layer corresponding for example to a Ti / TiN / Cu stack.
    The LEDs 100 are completed by depositing, for example electrochemical, a conductive material such as copper, to a thickness such that the spaces 134 are filled with this material. This material also fills the locations 118 of the anodes. A chemical mechanical planarization of this material, as well as parts of the layer 136 located on the portions 122, is then implemented with stop on the hard mask 122, thus forming, for each LED 100, an anode 138 and a cathode 140. The anodes 138 are electrically isolated from the cathodes 140 by virtue of the portions of the hard mask 122 surrounding each of the anodes 138. The cathodes 140 are electrically connected to the portions 132 whose lateral sides are not covered by the dielectric portions 130.
    The LEDs 100 can be produced as they are in a common cathode configuration, that is to say of which the cathodes are electrically connected to each other. As a variant, the LEDs 100 may each comprise a cathode 140 which is not electrically connected to the cathodes 140 of the other LEDs 100.
    A diffusion barrier, formed by a layer of Ti and a layer of TiN, is produced on the anodes 138 and the cathodes 140 by deposition, lithography and etching.
    The whole of the upper face of the assembly produced, which corresponds to a rear face 141 of the matrix of LEDs 100 at the level of which the electrodes 138 and 140 of the LEDs 100 are accessible, is covered by a bonding oxide 142 intended to the subsequent joining of the LED array 100 with an electronic control circuit.
    In parallel with the production of the LED matrix 100, the transfer of a stack of layers, intended for the production of components of the electronic control circuit which will be coupled to the LEDs 100, on the LED matrix 100 is prepared.
    For this, a substrate 200 of the semiconductor on insulator type is used (see FIG. 2A). This substrate 200 comprises a thick, or massive, layer 202 of semiconductor, for example of silicon, on which is disposed a buried dielectric layer 204 (BOX), comprising for example SiO 2 . Layer 204 is covered with a surface layer 206 of semiconductor, here comprising silicon. The thickness of the layer 206 is for example between approximately 5 nm and 50 nm, and advantageously greater than approximately 30 nm in order to avoid the implementation of subsequent epitaxy recoveries which may require significant temperatures or a technological cost. additional.
    Advantageously, the layer 206 comprises SiGe with a germanium content of between approximately 10% and 50%, advantageously 34%, allowing a good compromise between the speed of recrystallization by SPER (recrystallization by epitaxy in solid phase, which will be put later) and the simplicity of the manufacturing process.
    Layer 206 corresponds to the active layer, that is to say the layer in which the active areas of the electronic components of the electronic control circuit which will be coupled to the matrix of LEDs 100 will be produced.
    If the transistors of this circuit are in unipolar technology, an implantation Vt is possible in full plate at the start of the production process In this case, before depositing the gate stack described below, the substrate 200 can receive an ion implantation and undergo a full plate annealing to adjust the threshold voltage of the transistors of the control circuit which will be produced from this substrate. This can in particular be used to obtain a compromise between leaks and performance in these transistors.
    A layer of gate dielectric 208, that is to say intended to form the gate dielectrics of the FET transistors of the electronic control circuit, is formed on layer 206. This layer 208 comprises for example oxide which can be obtained by oxidation of layer 206, in this case with the material of the gate dielectrics which corresponds for example to SiO 2 , or by deposition of high temperature oxide HTO (“High Temperature Oxide”). As a variant, the layer 208 can be produced by depositing a dielectric material with high permittivity ("high-k") such as HfO 2 .
    The production of this layer 208 is followed by the deposition of a layer of gate conductive material 210 intended to form the gate conductors of the FET transistors. When the layer 208 comprises a semiconductor oxide, the material of the layer 210 corresponds for example to polysilicon. Alternatively, when the material of layer 208 is a high permittivity dielectric, the material of layer 210 may be a stack of metal such as TiN, TaN, or even TiAIN, etc., and of polysilicon. The polysilicon of layer 210 can be doped.
    A hard mask layer 212 is then deposited on the layer 210. The material of the layer 212 corresponds for example to a nitride or a semiconductor oxide, and its thickness is for example between approximately 10 nm and 100 nm.
    A mechanical retaining layer 214, forming a temporary handle, is deposited on the layer 212 (FIG. 2B). This handle provides mechanical retention of the stack of layers produced, which makes it possible to remove the thick layer 202 and access the buried dielectric layer 204 from the rear face of this stack.
    The assembly thus produced is transferred to the rear face 141 of the matrix of LEDs 100 previously produced, direct bonding of the oxide-oxide type being carried out between the buried dielectric layer 204 and the layer 142 (FIG. 2C).
    After the implementation of this assembly, the substrate 102 is removed, for example by laser removal ("laser lift-off") using the layer 214 as a mechanical holding element of the assembly obtained. A front face 143 of the matrix of LEDs 100 is then accessible.
    In parallel with the implementation of the steps described above, a structure intended to form covers for the LEDs 100 is produced.
    As shown in FIG. 3A, a cover layer 300, corresponding for example to a semiconductor substrate, such as silicon, is subjected to lithography and etching in part of its thickness to form cavities 302 which are intended to be arranged opposite the LEDs 100.
    An optically reflective material (capable of reflecting most of the light, for example more than 80% of the light received) is then deposited on the face of the cover layer 300 at the level of which the cavities 302 have been produced. This optically reflective material is etched in order to keep only portions 304 of this optically reflective material arranged against the side walls of the cavities 302 (FIG. 3B). This etching is for example an anisotropic etching RIE ICP.
    A bonding layer 306, comprising for example semiconductor oxide such as SiO 2 , is then formed over the entire face of the cover layer 300 comprising the cavities 302, as well as in the cavities 302 (bottom wall and side walls formed by the portions 304) (Figure 3C).
    The structure obtained, intended to form covers for the LEDs 100, is then secured to the front face 143 of the array of LEDs 100, on the side opposite to that at which the electrodes 138 and 140 are accessible, such as the cavities 302 are arranged opposite the LEDs 100. The front face 143 of the LED array 100 is previously covered with a bonding layer 144 to which the bonding layer 306 is secured.
    Consolidation annealing can be carried out in order to reinforce this bonding between the matrix of LEDs 100 and the covers.
    The mechanical retaining layer 214 can then be removed (FIG. 3D), the mechanical retaining of the assembly being ensured by the cover structure comprising the cover layer 300.
    The layers 212, 210, 208 and 206 are then etched in order to define, in the layer 206, the active zones 216 of the FET transistors intended to be formed on the matrix of LEDs 100. The remaining portions 218, 220 and 222 of the layers 208 , 210 and 212 are engraved according to the same pattern as that of the active zones. This engraving is stopped on the collage oxide 142 + 204 (FIG. 4A).
    In FIGS. 4A and following, the ratio between the dimensions of the electronic components, in particular of the FET transistors, and those of the LEDs 100 shown does not correspond to the real dimensions of these elements. In addition, in these figures, the production of a single FET transistor is shown. However, for each LED 100, the electronic control circuit produced may include several FET transistors associated with this LED 100.
    As shown in FIG. 4B, another lithography and another engraving are used to form, in the portions 218, 220 and 222, the grids of the electronic components. Grids 224 each comprising a grid dielectric 226 and a conductive portion of grid 228 are thus produced. The grids 224 are covered with a remaining portion 230 of the hard mask layer 212 used for etching the grids 224.
    Spacers 232 are then produced around the grids 224 and the portions 230, by deposition and etching. The spacers 232 are for example made from one or more dielectric materials deposited at low temperature such as SiCO, SiCBNoudu BN.
    The source and drain regions of the transistors are then produced in the parts 234 of the active zones 216 not covered by the gates 224 and by the spacers 232. To produce these source and drain regions, an ion implantation dimensioned so as to partially making the semiconductor of these parts 234 of the active areas 216 amorphous is implemented. This amorphization is partial because part of the crystalline semiconductor of these parts 234 is preserved, for example in the form of a recrystallization seed with a thickness of the order of 5 nm and placed on the side of the bonding oxide. 142 + 204. For the production of NMOS transistors, it is possible to implant Sb ions for example with an energy of between approximately 5 keV and 10 keV and a dose of between approximately 5.10 14 at / cm 2 and 5.10 15 at / cm 2 . For the production of PMOS transistors, it is possible to implant Ge ions (for example with an energy of the order of 5 keV with a dose of the order of 5.10 14 at / cm 2 ) before implanting dopants (for example boron with an energy of the order of 3 keV and a dose of 8.10 14 at / cm 2 ).
    The implantation conditions can be determined by using, for example, a Monte-Carlo type particulate simulator to size the thickness of the amorphous semiconductor layer.
    A solid phase recrystallization annealing is then carried out at temperatures between approximately 450 ° C. and 600 ° C., forming the sources and drains 236 of the FET transistors. Advantageously, this temperature is as low as possible.
    This annealing can be carried out in an oven, or by using a laser source locally heating the source and drain regions.
    A dielectric layer 238 of PMD (“Pre Metal Dielectric”) type, comprising for example semiconductor oxide, is then deposited on the electronic components produced, then planarized. Electrical contacts 240, connected in particular to the sources and drains 236 previously produced as well as to the grids 224 and to the electrodes of the LEDs 100, are then produced through the dielectric layer 238, and possibly the dielectric layers 142 + 204 for the contacts 240 connected LEDs 100 electrodes, by etching and filling of electrically conductive material (Figure 4D). When the assembly formed by the dielectric layers 142 + 204 has a thickness greater than or equal to approximately 150 nm and / or if the transistors of the electronic control circuit are produced with small dimensions such as for example those adapted to technological nodes less than 65 nm, the electrical contacts 240 can be produced in two stages: a first lithography and etching step forming the locations of the electrical contacts 240 associated with the source, drain and gate of the transistors, and a second etching step forming the locations of the electrical contacts 240 associated with LEDs 100. These locations are then filled simultaneously to form all of the electrical contacts 240.
    The electronic control circuit of the LED array 100 is completed by forming, above the layer 238, one or more metallic levels of interconnections (not visible in FIGS. 4D and following).
    The electronic control circuit can correspond to any type of electronic control circuit capable of controlling the light emission of the LEDs 100. An example of a control circuit 242 is shown in FIG. 4E. As a variant, the control circuit 242 may not include capacitors, and in this case includes additional transistors forming memory points.
    The cover layer 300 is then thinned until it reaches the cavities 302 and thus open these cavities 302 and allow the LEDs 100 to emit light (FIG. 4F). Portions of the cover layer 300 are kept next to the open cavities 302, which makes it possible to limit the phenomenon of crosstalk, or “crosstalk”, between neighboring pixels.
    The spaces formed by the open cavities 302 can be filled with phosphors 308 arranged against the output faces of the LEDs 100 and making it possible to modify the wavelengths emitted by the LEDs 100.
    According to a particular embodiment, the channels of the FET transistors produced can have channels (produced from layer 206) formed of SiGe containing 34% germanium, of thickness equal to approximately 17 nm, which makes it possible to produce these transistors. FET without having to carry out an epitaxial recovery and therefore ensuring that the FET transistors are produced without ever exceeding a temperature of approximately 400 ° C. (temperature reached during recrystallization annealing in solid phase, for approximately 47h to 400 ° C in the particular embodiment described here). In order to ensure good electrostatic control and to benefit from a slope below the threshold of around 60 mV / dec, the minimum gate length of these FET transistors can be around 85 nm. The ON current of the transistor will then be around 110 pA / pm, and its OFF current will be around 5.10 10 A / pm.
    As a variant, the channels of the FET transistors can be thinned so as to be able to reduce the gate length while benefiting from good electrostatic control of the transistor. This thickness of the channels can be equal to approximately 10 nm, which makes it possible to have a gate length of the order of 50 nm (in this case l 0N of the order of 200 pA / pm and I O ff of around 1 nA / pm). In this case, an epitaxy of the sources and drains can be carried out at a temperature of approximately 450 ° C. Activation of the dopants can then be carried out by implementing a partial amorphization as described above, then a recrystallization annealing in solid phase SPER of 450 ° C. for a duration of approximately lhlO.
    As a variant of the embodiment described above, the active layer 206 in which the channels of the FET transistors of the electronic control circuit are produced may comprise silicon. This variant allows the production of NMOS and PMOS transistors without the constraints of producing NMOS transistor channels in SiGe. On the other hand, the PMOS transistors have in this case poorer performance, the recrystallization rates by SPER are lower and the epitaxial resumptions are carried out at temperatures of at least 500 ° C.
    The thicknesses of the channels of the FET transistors produced can be less than 17 nm. In this case, to have good control of the short channel effects, the grids can have lengths of at least 5 times the thickness of the channels. Depending on the desired current in the transistors, the length of the gates of the transistors can therefore be adjusted. In addition, it may be necessary to carry out an epitaxy of the source and drain after having etched the grid and produced the spacers, for example when the channel has a thickness equal to approximately 10 nm.
    FIGS. 5A to 5D represent the steps implemented according to another embodiment of the display device 1000. In this other embodiment, an optical filtering structure 400 is produced on the front face 143 of the array of LEDs 100 .
    The steps previously described in connection with Figures IA to 2C are first implemented.
    As shown in FIG. 5A, the substrate 102 is removed, for example by laser removal (“laser lift-off”) using the layer 214 as a mechanical holding element for the assembly obtained. The front face 143 of the array of LEDs 100 is then accessible.
    A layer 402 comprising a first filtering material is formed against the front face 143 of the array of LEDs 100. This layer 402 is supported by a growth substrate 404 used for producing the layer 402 (FIG. 5B). In the embodiment described here, this layer 402 comprises a first filtering material capable of allowing the wavelengths corresponding to the green color to pass, that is to say between approximately 490 nm and 573 nm.
    The growth substrate 404 is then removed and then the layer 402 is etched so as to keep the remaining portions 406 of this layer 402 only opposite the LEDs 100, for example called first LEDs, intended to emit green light.
    A first transparent dielectric layer, comprising for example oxide, is then deposited then planarized in order to fill the spaces between these portions 406. Portions 408 of transparent dielectric material are thus formed opposite the LEDs 100 which are not intended to emit a green light.
    A layer 410 comprising a second filtering material is formed against the portions 406 and 408. Here again, this layer 410 is supported by a growth substrate 412 (FIG. 5C). In the embodiment described here, this layer 410 comprises a second filtering material capable of allowing the wavelengths corresponding to the red color to pass, that is to say between approximately 600 nm and 700 nm.
    The growth substrate 412 is then removed and then the layer 410 is etched in order to keep the remaining portions 414 of this layer 410 only opposite the LEDs 100, for example called second LEDs, intended to emit red light.
    A second transparent dielectric layer, comprising for example oxide, is then deposited then planarized in order to fill the spaces between these portions 414. Portions 416 of transparent dielectric material are thus formed opposite the LEDs 100 which are not intended to emit a red light.
    The optical filtering structure 400 according to this embodiment therefore comprises the portions 406, 408, 414 and 416. As a variant, it is possible that the optical filtering structure 400 comprises a single level of portions of filtering material, for example only the portions 406 and 408. According to another variant, the optical filtering structure 400 may comprise more than two levels of portions of filtering material, for example three. For example, it is possible that the optical filter structure is produced using three different filter materials, for example allowing only the wavelengths corresponding to the colors red, green or blue to pass, the portions of these filter materials being arranged facing the LEDs 100 by forming a Bayer matrix or any other filtering configuration.
    When the optical filter structure 400 is completed, an optically transparent mechanical retaining layer 418 is deposited on the optical filter structure 400 (FIG. 5D). This layer 418 provides mechanical support making it possible to remove the layer 214. This layer 418 is advantageously a glass substrate because it is completely thermally compatible with the temperatures reached during the implementation of the subsequent steps to complete the production of the device. display 100. In addition, the glass has a coefficient of thermal expansion similar to that of silicon
    The display device 1000 is then completed by producing the electronic control circuit, and in particular the FET transistors, on the rear face of the array of LEDs 100, as previously described in connection with FIGS. 4A to 4D.
    权利要求:
    Claims (14)
    [1" id="c-fr-0001]
    1. Method for producing a display device (1000), comprising at least the implementation of the following steps:
    - production of an LED array (100) each comprising electrodes (120,138, 140) accessible from a rear face (141) of the LED array (100) and light emission surfaces from a front face (143) the array of LEDs (100);
    - joining, on the rear face (141) of the LED array (100), of a stack of layers comprising at least one semiconductor layer (206), a layer of gate dielectric (208) and a layer gate conductive material (210);
    - production, from the stack of layers, of an electronic control circuit (242) electrically coupled to the electrodes (120, 138, 140) of the LEDs (100), comprising the production of FET transistors comprising active areas ( 216) and grids (224), the active areas (216) being formed in the semiconductor layer (206) and the grids (224) being formed in the layers of gate dielectric (208) and conductive material grid (210).
    [2" id="c-fr-0002]
    2. Method according to claim 1, in which the production of the LED array (100) comprises the implementation of the following steps, for each of the LEDs (100):
    - Production of a mesa structure comprising at least first and second semiconductor portions (124, 128, 132) of different dopings and forming a p-n junction;
    - Production of a first electrode (120, 138) disposed on the mesa structure and electrically connected to the first portion of semiconductor (124);
    - production of a second electrode (140) disposed next to the mesa structure and electrically connected to the second portion of semiconductor (128, 132) via at least part of the side faces of the second portion semiconductor (132).
    [3" id="c-fr-0003]
    3. Method according to one of the preceding claims, wherein the semiconductor layer (206) comprises SiGe with a germanium content of between about 10% and 50%.
    [4" id="c-fr-0004]
    4. Method according to one of the preceding claims, wherein the joining of the stack of layers on the rear face (141) of the LED array (100) involves the implementation of direct bonding between a first layer of oxide (204) forming part of the stack of layers and a second layer of oxide (142) disposed on the rear face (141) of the array of LEDs (100).
    [5" id="c-fr-0005]
    5. Method according to claim 4, further comprising, before the stacking of layers on the rear face (141) of the LED array (100) is secured, the stacking of layers by the implementation following steps:
    - Realization of the gate dielectric layer (208) on the semiconductor layer (206) which corresponds to the surface layer of a semiconductor on insulator type substrate;
    - Making the layer of gate conductive material (210) on the layer of gate dielectric (208);
    - Realization of a hard mask layer (212) on the layer of grid conductive material (210);
    - Production of a mechanical holding layer (214) on the hard mask layer (212);
    - removing a thick semiconductor layer (202) from the semiconductor-on-insulator type substrate;
    and wherein a buried dielectric layer (204) of the semiconductor on insulator type substrate forms the first oxide layer.
    [6" id="c-fr-0006]
    6. Method according to one of the preceding claims, in which the semiconductor layer (206) of the stack of layers comprises a crystalline semiconductor, and in which the active zones (216) of the FET transistors are formed in the layer semiconductor (206) at least via the implementation of a
    5 ion implantation in parts (234) of the active zones (216) of the FET transistors intended to form the source and drain (236) of the FET transistors, rendering the semiconductor of said parts (234) partially amorphous, then of an annealing for solid phase recrystallization of the active zones (216) of the FET transistors.
    10
    [7" id="c-fr-0007]
    7. The method of claim 6, wherein the recrystallization annealing is carried out at a temperature between about 450 ° C and 600 ° C.
    [8" id="c-fr-0008]
    8. Method according to one of claims 6 or 7, wherein the
    15 recrystallization annealing is carried out by exposing the source and drain (216) of the FET transistors to a laser source.
    [9" id="c-fr-0009]
    9. Method according to one of claims 6 to 8, in which the production of the FET transistors comprises the implementation of the following steps:
    2 0 - lithography and etching of the gate dielectric layers (208) and of the gate conductive material (210) and of the semiconductor layer (206) such that remaining portions of the semiconductor layer form the zones active (216) FET transistors;
    - lithography and etching of the gate dielectric layers (208) and
    2 5 of gate conductive material (210) such that remaining portions (226, 228) of the layers of gate dielectric (208) and of gate conductive material (210) form the gates (224) of the FET transistors;
    - Producing spacers (232) against the side walls of the gates (224) of the FET transistors;
    and in which the parts (234) of the active zones (216) of the FET transistors intended to form the source and drain (236) of the FET transistors correspond to parts of the active zones (216) of the FET transistors not covered by the gates (224 ) and the spacers (232).
    [10" id="c-fr-0010]
    10. Method according to one of the preceding claims, in which the production of the electronic control circuit (242) further comprises, after the production of the FET transistors, the production of electrical contacts (240) electrically connected to the FET transistors and / or to the electrodes (120,138,140) of the LEDs (100).
    [11" id="c-fr-0011]
    11. Method according to one of the preceding claims, further comprising, between the joining of the stack of layers on the rear face (141) of the LED array (100) and the production of the electronic control circuit (242) , the implementation of the following steps:
    - Producing cavities (302) through one face of a cover layer (300), each cavity (302) being intended to be placed opposite one of the LEDs (100);
    - depositing a reflective material (304) at least against the interior side walls of the cavities (302);
    - Securing said face of the cover layer (300) against the front face (143) of the LED array (100) such that each cavity (302) is arranged facing at least one of the LEDs (100);
    and further comprising, after completion of the electronic control circuit (242), a step of thinning the cover layer (300) removing bottom walls of the cavities (302) of the cover layer (300) lying opposite light emission surfaces of the LEDs (100).
    [12" id="c-fr-0012]
    12. The method of claim 11, further comprising, after the step of thinning the cover layer (300), a step of making phosphors (308) between the remaining portions of the cover layer (300), against the front face (143) of the LED array (100) and opposite the emission surfaces of the LEDs (100).
    [13" id="c-fr-0013]
    13. Method according to one of claims 1 to 10, further comprising, between the joining of the stack of layers on the rear face (141) of the
    5 matrix of LEDs (100) and the production of the electronic control circuit, the production of an optical filter structure (400) capable of filtering at least part of the wavelengths intended to be emitted by at least part of the LEDs (100), on the front face (143) of the LED array (100) and facing the light emission surfaces of said part of the LEDs (100).
    [14" id="c-fr-0014]
    14. The method as claimed in claim 13, in which the production of the optical filtering structure (400) comprises at least the implementation of the following steps:
    - depositing a layer (402) of a first filtering material on the front face (143) of the LED array (100);
    - Etching the layer (402) of the first filtering material such that the remaining portions (406) of the first filtering material are arranged facing the light emission surfaces of a portion of the LEDs (100), called first LEDs;
    making first portions (408) of transparent dielectric material between the remaining portions (406) of the first filter material;
    - depositing a second layer (410) of filtering material on the remaining portions (406) of the first filtering material and on the first portions (408) of transparent dielectric material;
    - etching the second layer (410) of filtering material such that the remaining portions (414) of the second filtering material are arranged facing the emission surfaces of other LEDs (100), called second LEDs;
    - Making second portions (416) of transparent dielectric material between the remaining portions (414) of the second filter material;
    and further comprising depositing an optically transparent mechanical retaining layer (418) against the optical filtering structure (400) prior to the production of the electronic control circuit.
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    同族专利:
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    US20180301479A1|2018-10-18|
    US10468436B2|2019-11-05|
    EP3392918A1|2018-10-24|
    FR3065322B1|2019-06-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20150325598A1|2012-12-14|2015-11-12|Osram Opto Semiconductors Gmbh|Display device and method for producing a display device|
    US20160268488A1|2013-10-29|2016-09-15|Osram Opto Semiconductors Gmbh|Wavelength conversion element, method of making, and light-emitting semiconductor component having same|
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    EP3916788A1|2020-05-29|2021-12-01|Commissariat à l'Energie Atomique et aux Energies Alternatives|Method for manufacturing an optoelectronic device comprising a plurality of diodes|TWI626738B|2017-04-06|2018-06-11|宏碁股份有限公司|Display device and method of manufacturing the same|JP2020154096A|2019-03-19|2020-09-24|株式会社ジャパンディスプレイ|Display device|
    FR3102613A1|2019-10-28|2021-04-30|Commissariat A L'energie Atomique Et Aux Energies Alternatives|PROCESS FOR MAKING A PHOTO-EMITTING OR PHOTO-RECEIVING DIODE|
    法律状态:
    2018-04-26| PLFP| Fee payment|Year of fee payment: 2 |
    2018-10-19| PLSC| Search report ready|Effective date: 20181019 |
    2019-04-29| PLFP| Fee payment|Year of fee payment: 3 |
    2020-04-30| PLFP| Fee payment|Year of fee payment: 4 |
    2021-04-29| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
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    FR1753334|2017-04-18|
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    US15/949,566| US10468436B2|2017-04-18|2018-04-10|Method of manufacturing a LED matrix display device|
    EP18167095.1A| EP3392918B1|2017-04-18|2018-04-12|Method of manufacturing a led matrix display device|
    CN201810344227.6A| CN108735663A|2017-04-18|2018-04-17|The method for manufacturing LED matrix display device|
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