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    • 专利摘要:
    The invention relates to a method for manufacturing a coating-gate field effect transistor (41), comprising the steps of: -providing a substrate surmounted by first and second nanowires (12, 14) extending in the same direction longitudinal and having: a medial portion (120, 140), covered by a first material (44); first and second ends (123, 143, 124, 144) formed on either side of the median portion, the periphery of which is covered by respective first and second dielectric spacers (18, 19) in a second different material; first material, said ends having exposed side faces; -dopart a portion of the first and second ends by said side faces; depositing a metal on either side of the nanowires to form first and second metal contacts (51, 52) in electrical contact respectively with the doped portions of the first and second ends of the nanowires.
    公开号:FR3064815A1
    申请号:FR1752741
    申请日:2017-03-31
    公开日:2018-10-05
    发明作者:Remi COQUAND；Emmanuel Augendre；Shay REBOH
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Holder (s): COMMISSIONER OF ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.
    Extension request (s)
    Agent (s): INNOVATION COMPETENCE GROUP.
    y PROCESS FOR MANUFACTURING A COVERED GRID FIELD-EFFECT TRANSISTOR.
    FR 3 064 815 - A1 (5 // The invention relates to a method of manufacturing a field effect transistor with a covering gate (41), comprising the steps of:
    -providing a substrate surmounted by first and second nanowires (12,14) extending in the same longitudinal direction and having:
    a middle part (120, 140), covered by a first material (44);
    first and second ends (123, 143, 124, 144) formed on either side of the middle part, the periphery of which is covered by respective first and second dielectric spacers (18, 19) in a second different material of the first material, said ends having exposed lateral faces;
    doping a part of the first and second ends by said lateral faces;
    depositing a metal on either side of the nanowires to form first and second metal contacts (51, 52) in electrical contact respectively with the doped parts of the first and second ends of the nanowires.
    19
    METHOD FOR MANUFACTURING A COATING GRID FIELD-EFFECT TRANSISTOR
    The invention relates to field effect transistors with a covering grid, and in particular to the manufacturing methods for such transistors.
    The increase in the performance of integrated circuits due to the miniaturization of field effect transistors is faced with a technological and scientific obstacle. One of the issues is the increase in static and dynamic power in integrated circuits. In order to reduce this power consumption, new architectures and new materials which will make it possible to obtain a low operating voltage are today intensively studied.
    In particular, for technological nodes below 50 nm, the electrostatic control of the channel by the gate becomes a predominant operating parameter for the operation of the transistor. To improve this electrostatic control, various technologies of multi-gate transistors are the subject of developments, in particular the transistors with a covering gate.
    A known manufacturing method for a covering gate transistor is as follows. A stack of nanowires is formed, comprising alternating nanowires of silicon and silicon-germanium on a substrate, so as to obtain, for example, SiGe nanowires constrained in compression and relaxed silicon nanowires. A sacrificial grid is formed to cover the middle part of the stack of nanowires. Insulating spacers are also formed on either side of the sacrificial grid, to cover an intermediate middle part of the stack of nanowires. The transistor channels are intended to be formed in this middle part. The nanowires of the stack projecting beyond the spacers are not covered and are removed by etching. Part of the SiGe nanowires placed under the insulating spacers is removed by selective etching, so as to form cavities under these spacers. A dielectric is deposited inside the cavities to form internal spacers, intended to isolate the source and the drain with respect to the gate of the transistor.
    By a silicon-germanium growth step by epitaxy, a source and a drain are formed on either side of the stack. The source and the drain formed by epitaxy are then in contact and in the continuity of the silicon nanowires which have been preserved under the sacrificial grid and the spacers. The source and the drain are then encapsulated in a passivation or encapsulation material. A groove is then formed at the sacrificial grid and the sacrificial grid is removed. The residual stack of nanowires is then discovered. By selective etching, the silicon-germanium nanowires are removed.
    ICG011128 EN Text Depot.docx
    A gate insulator is then deposited on the exposed part of the silicon nanowires, then a gate material is formed on the gate insulator to encapsulate the middle part of these nanowires.
    The passivation / encapsulation material is then removed from the source and the drain. Then siliciding is carried out on the upper face of the source and of the drain. Source and drain contacts are then formed, in particular by a metallic deposit on the silicided face of the source and the drain.
    The coating gate transistor obtained according to this process has drawbacks. Indeed, for small technological nodes, the dimensions of the source and the drain formed by epitaxy are very small, which can lead to the formation of gaps in the source or the drain and / or to a very high contact resistance. high. Furthermore, the higher the number of nanowires in the stack, the more there is a difference in access resistance between the metal contact and the different channels.
    The invention aims to solve one or more of these drawbacks. The invention aims in particular to homogenize the access resistors to the different channels of a covering gate transistor. The invention thus relates to a method for manufacturing a field effect transistor with a covering gate, comprising the steps of:
    -provide a substrate surmounted by first and second nanowires of semiconductor material extending in the same longitudinal direction and arranged vertically from one another, each of these first and second nanowires having:
    -a middle part, covered by a first material;
    first and second ends formed on either side of the middle part in said longitudinal direction, the periphery of which is covered by respective first and second dielectric spacers made of a second material different from the first material, said first and second ends having first and second uncovered side faces respectively;
    -doping part of the first and second ends by means of said first and second side faces;
    - depositing a metal on the other side of the first and second nanowires to form first and second metal contacts in electrical contact respectively with the doped parts of the first and second ends of the first and second nanowires.
    The invention also relates to the following variants. Those skilled in the art will understand that each of the characteristics of the following variants can be combined independently with the above characteristics, without however constituting an intermediate generalization.
    ICG011128 EN Text Depot.docx
    According to a variant, the doping of the first and second ends of said first and second nanowires is carried out by plasma, implantation, diffusion or dilution.
    According to yet another variant, said first material is a grid insulator, said grid insulator being covered by a conductive grid.
    According to another variant, the first and second nanowires are formed from a silicon alloy.
    According to yet another variant, the method further comprises a step of siliciding the first and second lateral faces of said doped parts of the first and second ends of the first and second nanowires.
    Alternatively, said siliciding step comprises depositing a layer of metal on said first and second side faces and annealing the deposited metal.
    According to yet another variant, said first and second lateral faces of said first and second nanowires supplied are set back relative to said first and second spacers respectively.
    According to another variant, the method comprises a step of depositing an amorphous silicon alloy on said first and second lateral faces of said first and second nanowires, then a step of crystallization of said silicon alloy.
    According to yet another variant, the method further comprises a step of depositing a layer of dielectric material on the doped parts of the first and second nanowires, producing said metal deposit forming the first and second metal contacts on said layer of dielectric material.
    According to a variant, the method comprises a step of depositing an amorphous silicon alloy on said first and second lateral faces of said first and second nanowires, then a step of crystallizing said silicon alloy so as to extend said doped parts of the first and second nanowire, then perform said step of depositing the layer of dielectric material.
    According to another variant, the method further comprises a step of siliciding the first and second lateral faces of said doped parts of the first and second ends of the first and second nanowires.
    According to yet another variant, said first and second ends of the first and second nanowires each have a length of between 5 and 10 nm.
    According to another variant, the method comprises a step of depositing a layer of dielectric material on said first and second lateral faces of said doped parts of the first and second nanowires, said deposit of metal being produced on said layer of dielectric material so as to forming said first and second metal contacts in the form of an MIS type contact.
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    According to yet another variant, said first and second nanowires supplied have a thickness at most equal to 15 nm.
    The invention also relates to a field effect transistor with a covering gate, comprising:
    a substrate surmounted by first and second nanowires of semiconductor material extending in the same longitudinal direction and arranged vertically from one another, each of these first and second nanowires having:
    -a middle part, covered by a first material;
    first and second ends formed on either side of the middle part in said longitudinal direction, the periphery of which is covered by respective first and second dielectric spacers made of a second material different from the first material, said first and second ends having respective doped portions having a dopant at a concentration greater than that of their middle portion;
    first and second metal contacts in electrical contact respectively with the doped parts of the first and second ends of the first and second nanowires.
    Other characteristics and advantages of the invention will emerge clearly from the description given below, by way of indication and in no way limitative, with reference to the appended drawings, in which:
    FIGS. 1 to 17 illustrate a transistor during different stages of its manufacturing process, according to an example of a first embodiment of the invention;
    FIGS. 18 to 20 illustrate a transistor during different stages of its manufacturing process, according to an example of a second embodiment of the invention;
    FIGS. 21 to 25 illustrate a transistor during different stages of its manufacturing process, according to an example of a third embodiment of the invention;
    FIGS. 26 to 31 illustrate a transistor during different stages of its manufacturing process, according to an example of a fourth embodiment of the invention;
    FIGS. 32 to 35 illustrate a transistor during different stages of its manufacturing process, according to an example of a fifth embodiment of the invention;
    FIG. 36 illustrates two transistors obtained according to a variant of the second embodiment.
    ICG011128 EN Text Depot.docx
    Figures 1 to 17 illustrate a transistor 1 at different stages of its manufacturing process, according to an example of a first embodiment of the invention. The steps described with reference to FIGS. 1 to 5 are known per se to those skilled in the art and given by way of nonlimiting example for obtaining a superposition of nanowires with a sacrificial grid.
    In the present description, the term nanowire corresponds to an element of elongated shape in a longitudinal direction, whatever the shape of the profile of its cross section. The maximum width of the nanowire can be between 50 and 100 nm. The minimum width of the nanowire can be between 10 and
    100 nm. The height of the nanowire can for example be between 5 and 12 nm. The longitudinal dimension of the nanowire can be between 10 and 150 nm. In this sense, the term nanowire just as well denotes a nanoplate or a nanobar.
    In FIG. 1, there is a substrate, illustrated in perspective. The substrate may for example be of the sSOI type (for strained silicon on insulator) or of the SRB type (for substrate with relaxed buffer layer), in a manner known per se. We could also consider an application to an SOI or solid type substrate (for Bulk in English). The substrate is here of semiconductor on insulator type. The substrate here comprises an insulating layer 100, covered with a semiconductor layer 101. The semiconductor layer 101 is here a relaxed SiGe layer. For an SRB type substrate, the insulating layer 100 will for example be replaced by a relaxed SiGe layer covered with a silicon layer typically comprising a biaxial tension stress.
    In Figure 2, we proceeded to the formation of a superposition of layers 102 to 107 on the layer of SiGe 101. We thus formed an alternation of layers of SiGe 101, 103, 105 and 107, and layers of silicon 102, 104 and 106. Layers 102 to 107 are typically formed by sequential epitaxy deposition steps.
    The thickness of the layers 101, 103, 105 and 107 is for example between 5 and 15 nm, preferably at most 10 nm. This thickness is for example 7 nm. The thickness of the layers 102, 104 and 106 is for example between 5 and 15 nm, preferably at most 10 nm. This thickness is for example 9 nm.
    In FIG. 3, a mask 2 has been formed on the superposition of the layers
    101 to 107, for example by photolithography. In FIG. 4, the layers 101 to 107 were etched, so as to form superpositions or stacks of adjacent nanowires. Each superposition or stack of nanowires comprises a superposition of nanowires 11 to 17. The nanowires 11 to 17 extend in a longitudinal direction, and thus have a length at least twice their width or their thickness. Nanowires 11, 13,
    ICG011128 EN Depot Texte.docx and 17 are here in SiGe, for example
    If (ix) Ge x with 0.2 <x <0.6. We can for example take the value x = 0.3. The nanowires 12, 14 and 16 are here made of silicon. Mask 2 has been removed from the stacks. The width of each stack is for example between 10 and 50 nanometers. The nanowire stacks here comprise 7 superimposed nanowires. A different number of superimposed nanowires can of course be used. The height of the nanowire stacks is for example between and 100 nanometers.
    In FIG. 5, a sacrificial grid 31 has been formed for each of the nanowire stacks. Each sacrificial grid 31 coats the middle part of a respective stack of nanowires. The sacrificial grid 31 comprises for example a protective layer with a thickness of between 1 nm and 3 nm of S1O2 in contact with the nanowires, covered with a layer of Poly Si. The sacrificial grid 31 can also be formed (so nonlimiting) with a single layer of SiO2. The process for forming and shaping each sacrificial grid 31 is known per se. The gate length of a transistor to be formed is defined by the length over which a sacrificial gate 31 coats a respective stack of nanowires.
    The steps for forming internal spacers detailed with reference to FIGS. 6 to 9 are known per se to those skilled in the art. In FIG. 6, lateral spacers 32 and 33 have been formed, on either side of each of the sacrificial grids 31. The spacers 32 each coat an intermediate section of the stack of nanowires on a respective side of its median part and of the sacrificial grid 31. The spacers 33 each coat an intermediate section of the stack of nanowires on the other side of its middle part and of the sacrificial grid 31. The method of forming and shaping each spacer 32 , 33 is known per se. The width of each of the spacers 32 or 33 is for example between 3 and 15 nm. The spacers 32, 33 are for example made of dielectric material. The spacers 32 or 33 are for example formed from SiN, SiOCH, or SiBCN. The ends of the nanowire stacks remain projecting with respect to the spacers 32 or 33 and remain exposed.
    In FIG. 7, the ends of the nanowires 11 to 17 have been removed. The middle part of the nanowires 11 to 17 is kept under the sacrificial grid 31 and the intermediate sections of the nanowires 11 to 17 are kept under the lateral spacers 32 and 33. The projecting ends of the nanowires 11 to 17 are for example etched by an anisotropic etching using the sacrificial grid and the lateral spacers 32 and 33 as etching mask. The sections
    ICG011128 EN Depot Texte.docx intermediés of nanowires 11 to 17 then form the longitudinal ends of nanowires 11 to 17.
    In FIG. 8, cavities have been formed by withdrawal of the longitudinal ends of the SiGe nanowires 11, 13, 15 and 17, initially present under the lateral spacers 32 and 33. Such withdrawal is for example produced by etching selective. The longitudinal ends of the nanowires 12, 14 and 16 placed under the lateral spacers 32 and 33 are preserved. Selective etching of SiGe with respect to Silicon can, for example, be carried out by HCl chemistry, or with an aqueous ammonia / peroxide mixture at 70 ° C.
    In FIG. 9, internal spacers 18 and 19 have been formed in the cavities. To this end, a conformal dielectric deposition can be carried out in the cavities followed by etching. The internal spacers 18 and 19 coat the longitudinal ends of the nanowires 12, 14, and 16. The lateral faces of the nanowires 12, 14 and 16 are uncovered. The spacers 18 and 19 are advantageously made of dielectric with a low dielectric constant. The spacers 18 and 19 are for example made of SiBCN or SiOCH. The internal spacers 18 and 19 are typically formed from a material whose etching is very selective compared to the other materials used for the formation of the transistor (for example polysilicon and TiN for the gate, S1O2 for a passivation / encapsulation material ...). The internal spacers 18 and 19 are for example formed by ALD (for atomic layer deposition, Atomic Layer Deposition in English).
    In FIG. 10, an encapsulation material 34 (for example an oxide) has been deposited, so as to cover the lateral faces of the nanowires 12, 14 and 16 and of the internal spacers 18 and 19. It is possible to carry out a full plate deposition of the encapsulation material 34, then carry out a mechanochemical polishing until discovering the sacrificial grid 31 and the lateral spacers 32 and 33. The use of a paste based on CeO2 has for example selectivity sufficient.
    In FIG. 11, the sacrificial grid 31 is removed, in order to provide a groove 311 and thus access to the middle parts of the nanowires 11 to 17. The removal of the sacrificial grid 31 is for example carried out by selective etching with respect to to the material of the lateral spacers 32 and 33. The removal of the sacrificial grid 31 based on polycrystalline silicon is for example carried out with chemistry based on ammonia (NH4OH), or TMAH or TEAH.
    In FIG. 12, a selective withdrawal of the middle part of the nanowires 11, 13, 15 and 17 is carried out, while preserving the middle part of the nanowires 12, 14 and 16. The step of selective withdrawal of the middle part of the nanowires 11, 13, 15 and 17 can be implemented by a selective etching process. We thus realize a
    ICG011128 EN Depot Texte.docx selective removal of the middle part of nanowires 11, 13, 15 and 17 in SiGe compared to the middle part of nanowires 12, 14 and 16 in Silicon. The respective middle parts 120, 140 and 160 of the nanowires 12, 14 and 16 are thus discovered. The removal of the middle portions of the nanowires 11, 13, 15 and 17 is for example carried out by a selective etching of SiGe, for example a selective etching based on HCl. One can also envisage a selective etching of SiGe rendered amorphous vertically to the throat 311. The middle parts of the SiGe nanowires 11, 13, 15 and 17 give way to a recess 110.
    An access to all the faces of the middle parts 120, 140 and 160 of the nanowires 12, 14 and 16 is thus formed. The middle part of the nanowires 12, 14 and 16 corresponds to the channel zones of the coating gate transistor being formed. The internal spacers 18 and 19, and the lateral spacers 32 and 33 make it possible in particular to protect the longitudinal ends of the nanowires 12, 14 and 16 during this selective etching.
    In FIG. 13, a grid insulator 44 has been formed around the middle parts 120, 140 and 160 of the nanowires 12, 14 and 16. The grid insulator of each nanowire 12, 14 and 16 may for example comprise an interfacial oxide layer in contact with the nanowire, surmounted by an oxide layer coating this interfacial layer. The coating oxide layer can for example be made of HfO2. The methods of forming the gate insulator 44 are known per se to those skilled in the art.
    In FIG. 14, an enveloping grid 41 was formed by filling the recesses surrounding the middle parts 120, 140 and 160 of the nanowires 12, 14 and 16 and the grid insulators 44. The coating grid 41 can by example be produced in a manner known per se by depositing a gate metal and / or by depositing highly doped polysilicon.
    In FIG. 15, the encapsulation material 34 has been removed. The lateral faces of the nanowires 12, 14 and 16 and of the internal spacers 18 and 19 are then uncovered. The nanowire 12 thus has longitudinal ends having lateral faces 123 and 124 uncovered. The nanowire 14 thus has longitudinal ends having lateral faces 143 and 144 exposed. The nanowire 16 thus has longitudinal ends having lateral faces 163 and 164 uncovered. The middle part 120, 140 and 160 of the nanowires 12, 14 and 16 is covered by the grid stack at this stage (the grid stack here comprising the grid insulator 44 and the coating grid 41 detailed previously). A method of removing the encapsulation material 34 is known per se to those skilled in the art. One can for example carry out a selective etching of the encapsulation material 34 in S1O2 with HF or by reactive fluorinated ion etching (for example CHF, C2F6, C4F8).
    ICG011128 EN Text Depot.docx
    In FIG. 16, the longitudinal ends of the nanowires 12, 14 and 16 have been doped. The ends of the nanowires 12, 14 and 16 are doped by means of the uncovered lateral faces (respectively 123124, 143-144, 163-164). The nanowires 12, 14 and 16 thus have respective doped parts 125, 145 and 165 at a first longitudinal end, and respective doped parts 126, 146 and 166 at a second longitudinal end. Doping of the ends of nanowires 12, 14 and 16 is for example carried out by a plasma type doping step. Plasma doping can for example be implemented with As or B. The plasma ionization energy can for example be between 1 and 10 keV. The doping dose can for example be between 0.1 and 10 * 10 14 cm 2 .
    Such doping is advantageously carried out over part of the length (in the longitudinal direction) of the longitudinal ends of the nanowires, that is to say part of the width of the internal spacers 18 and 19. Thus, the doping can be carried out so that the dopants do not reach the middle part of the nanowires 12, 14 and 16 disposed vertically of the coating grid 41. The doped parts 125, 145, 165, 126, 146 and 166 are thus confined in the area of the nanowires 12 , 14 and 16 vertically from the spacers 18 and 19. This does not harm the electrostatic integrity of the channel zones of the transistor 1.
    Plasma doping makes it possible to obtain a uniform distribution of the dopants on each of the side faces, and a uniform distribution of the dopants for all the side faces of the nanowires 12, 14 and 16.
    The doping step may be followed by an activation annealing of the dopants. Such annealing can be carried out with a reduced thermal budget, in order to avoid dopants in the middle part located under the grid stack. Annealing can for example be of the heat peak type (spike anneal in English), with a heat peak at 1050 ° C. Annealing can also be carried out by laser pulses of a duration of the order of a millisecond.
    In FIG. 17, a metal deposition was carried out to form contacts 51 and 52 of source and drain, for example by a full plate deposition. The metal is notably deposited on either side of the nanowires 12, 14 and 16, in order to be in contact with the lateral faces of these nanowires 12, 14 and 16. An electrical contact is thus formed between the contact 51 and the lateral faces 123, 143 and 163. An electrical contact is also formed between the contact 52 and the lateral faces 124, 144 and 164. The metal contacts 51 and 52 are thus in electrical contact with the doped parts 125, 145, 165, 126, 146 and 166 nanowires 12, 14 and 16. Advantageously, a siliciding step is carried out by depositing metal (for example Ni), then annealing to react the Ni with the doped Si to form a silicide. Here, mechanochemical polishing was carried out following the deposition of the metal, in order to provide access to the coating grid 41.
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    The same metallic contact 51 or 52 for the ends of several nanowires makes it possible to obtain substantially the same access resistance, with an access resistance having a much smaller amplitude than with deposition of a semiconductor by epitaxy. The electrical resistances between the different channel zones (corresponding to the middle parts of the nanowires 12, 14 and 16) and the metal contacts 51 or 52 are thus identical. The electrical resistance through the metal contacts 51 and 52 being relatively reduced, the resistance of access to the middle parts of the nanowires 12, 14 and 16 are substantially identical.
    The metal of the metal contacts 51 and 52 can for example be deposited by chemical vapor deposition (CVD). The deposited metal may for example be a successive stack of Ti, TiN and W.
    In this first embodiment, the doping of the longitudinal ends of the nanowires and the formation of the metal contacts 51 and 52 are carried out after the formation of the coating grid 41. However, if the thermal budget used for the formation of the grid stack is relatively reduced, it is also possible to envisage doping the longitudinal ends of the nanowires and the formation of metal contacts 51 and 52 in the presence of internal spacers 18 and 19 but before the formation of the grid stack.
    Figures 18 to 20 illustrate a transistor 1 at different stages of its manufacturing process, according to an example of a second embodiment of the invention. The method according to the second embodiment can repeat the different steps of the method of the first embodiment, implemented up to the configuration illustrated in FIG. 16. The method according to the second embodiment applies to nanowires 12 , 14 and 16 in pure Si or in silicon alloys.
    In FIG. 18, a full metal plate layer 6 has been deposited, for example by chemical vapor deposition. The deposited metal is for example Ni. The metal layer 6 comes into particular contact with the doped parts 125, 145, 165, 126, 146 and 166 of the nanowires 12, 14 and 16.
    In FIG. 19, a silicide has been formed at each end of the nanowires 12, 14 and 16. For this, the silicide is formed by heat treatment (for example heating at 450 ° C. for one minute). The ends of the nanowires then undergo siliciding by reaction with the metal of layer 6. In particular, siliciding of Ni can result in the formation of crystalline NiS2 on Silicon which has a weak Schottky barrier. In the configuration illustrated in FIG. 19, the metal layer 6 has been removed. The removal of the metal layer 6 can for example be carried out by etching with H2SO4. The
    ICG011128 EN Depot Texte.docx ends of nanowires 12, 14 and 16 then have a doped internal part (doped parts 125, 145, 165, 126, 146 and 166), and a siliconized terminal part at their uncovered side faces. The nanowires 12, 14 and 16 thus comprise respective silicided end parts, 127, 128, 147, 148, 167 and 168. The siliciding is implemented so as to keep an internal doped and non-silicided part (doped parts 125, 145 , 165, 126, 146 and 166) between the middle parts of the nanowires 12, 14 and 16 and their siliconized end parts (127, 128, 147, 148, 167 and 168).
    In FIG. 20, a metal deposition was carried out to form contacts 51 and 52 of source and drain. The metal is notably deposited on either side of the nanowires 12, 14 and 16, in order to be in contact with the silicided end portions of the nanowires 12, 14 and 16. An electrical contact is thus formed between the contact 51 and the end portions 127, 147 and 167. An electrical contact is also formed between the contact 52 and the terminal parts 128, 148 and 168. The metal contacts 51 and 52 are thus in electrical contact with the doped ends of the nanowires 12, 14 and 16. We have here proceeded to a mechanochemical polishing following the deposition of the metal, in order to provide access to the coating grid 41.
    The metal of the metal contacts 51 and 52 can for example be deposited by chemical vapor deposition (CVD). The deposited metal can for example be formed by a sequential stacking of Ti, TiN and W.
    The silicide formed between the doped parts and the contacts 51 and 52 makes it possible to reduce the conduction resistance between these contacts and the channel zones.
    Since plasma doping has a maximum implantation density at the surface, the contact resistance between the doped parts and the silicided end parts is reduced.
    Figures 21 to 25 illustrate a transistor 1 at different stages of its manufacturing process, according to an example of a third embodiment of the invention. The method according to the third embodiment can repeat the different stages of the method of the first embodiment, implemented up to the configuration illustrated in FIG. 15. The method according to the third embodiment applies to nanowires 12 , 14 and 16 in pure Silicon or in silicon alloys.
    In FIG. 21, indentations have been formed at the ends of the nanowires 12, 14 and 16. The lateral faces 123, 143 and 163 are thus set back relative to the edge of the internal spacer 18, and positioned at the vertical of this internal spacer 18. The lateral faces 124, 144 and 164 are set back relative to the edge of the internal spacer 19, and positioned vertically on this internal spacer 19. Such a withdrawal can for example be carried out on a
    ICG011128 EN Depot Texte.docx depth between 1 and 3nm. Such removal can for example be carried out by dry etching of the atomic layer etching type (ALE) or of reactive ion etching type (RIE).
    In FIG. 22, the ends of the nanowires 12, 14 and 16 were doped. The ends of the nanowires 12, 14 and 16 are doped by means of the uncovered side faces (respectively 123-124, 143144, 163 -164). The nanowires 12, 14 and 16 thus have respective doped parts 125, 145 and 165 at a first end, and respective doped parts 126, 146 and 166 at a second end. The doping is advantageously carried out so that the dopants do not reach the middle part of the nanowires 12, 14 and 16 disposed vertically of the coating grid 41. The doped parts 125, 145, 165, 126, 146 and 166 are thus confined in the area of nanowires 12, 14 and 16 vertical to spacers 18 and 19.
    The doping of the ends of the nanowires 12, 14 and 16 is for example carried out by a plasma type doping step, for example with the parameters described with reference to the first embodiment. Due to the withdrawal of the lateral faces 123, 143, 163, 124, 144 and 164, the doped parts can be brought closer to the middle part of the nanowires 12, 14 and 16. Doping can be implemented with more plasma energy reduced, to obtain a junction with a more abrupt profile.
    In FIG. 23, a full plate metal layer 6 has been deposited, for example by chemical vapor deposition. The deposited metal is for example Ni. The metal layer 6 is notably deposited in contact with the lateral faces of the nanowires 12, 14 and 16, set back relative to the esspacers 18 and 19. The metal layer 6 is therefore deposited in contact with the doped parts 125, 145, 165, 126, 146 and 166.
    In FIG. 24, a silicide has been formed at each end of the nanowires 12, 14 and 16. The nanowires 12, 14 and 16 thus have silicided end portions 127, 128, 147, 148, 167 and 168 The silicide can be formed with the same parameters as those described for the method of the second embodiment. The unreacted part of the metal layer 6 was also removed. Such removal is for example carried out by anisotropic etching with H2SO4.
    In FIG. 25, a metal deposition was carried out to form contacts 51 and 52 of source and drain. The metal is notably deposited on either side of the nanowires 12, 14 and 16, in order to be in contact with the silicided end portions of the nanowires 12, 14 and 16. An electrical contact is thus formed between the contact 51 and the end portions 127, 147 and 167. An electrical contact is also formed between the contact 52 and the terminal parts 128, 148 and 168. The metal contacts 51 and 52 are thus in electrical contact with the ends
    ICG011128 EN Depot Texte.docx doped with nanowires 12, 14 and 16. Here we proceeded to mechanochemical polishing following the deposition of the metal, in order to provide access to the coating grid 41.
    Such a variant makes it possible to position an abrupt junction of the doped region of the nanowires 12, 14 and 16 near their median parts, forming the channel zones. It is thus possible to use plasma doping with a lower energy, and to obtain a junction with a steeper doping profile. Such a configuration is favorable to a good compromise between short channel effects and low access resistance.
    Figures 26 to 31 illustrate a transistor 1 at different stages of its manufacturing process, according to an example of a fourth embodiment of the invention. The method according to the fourth embodiment can repeat the different steps of the method of the first embodiment, implemented up to the configuration illustrated in FIG. 16 (or up to the configuration illustrated in FIG. 22). The method according to the fourth embodiment is applied to nanowires 12, 14 and 16 made of silicon alloys.
    In FIG. 26, a silicon deposition step was carried out. A silicon layer 7 is deposited and is in particular in contact with the doped parts 125, 145, 165, 126, 146 and 166. The silicon layer 7 can for example be formed by a chemical vapor deposition of amorphous silicon.
    In step 27, a step of crystallization of the silicon layer 7 was carried out. The crystallization step can be carried out by annealing, for example at a temperature of 600 ° C. for 60 seconds. Such an annealing can bring about a diffusion of the dopants of the doped parts 125, 145, 165, 126, 146 and 166 in the layer 7. It is also possible to envisage implementing the method of the fourth embodiment from the configuration illustrated in FIG. 15, and carrying out plasma doping after the stage of crystallization of the silicon layer 7.
    In FIG. 28, a full plate metal layer 6 has been deposited, for example by chemical vapor deposition. The deposited metal is for example Ni. The metal layer 6 is notably deposited on the crystallized silicon layer 7.
    In FIG. 29, a silicide 63 was formed in the external part of the layer 7, and in particular in the alignment of the doped parts 125, 145, 165, 126, 146 and 166 of the nanowires 12, 14 and 16. The silicide 63 extends until contact with these doped parts 125, 145, 165, 126, 146 and 166.
    In FIG. 30, the part of the unreacted metal layer 6 has also been removed. Such removal is for example achieved by an engraving
    ICG011128 EN Text Depot.docx anisotropic with H2SO4. Two siliconized walls 61 and 62 are thus kept in contact with the doped parts of the nanowires 12, 14 and 16.
    In FIG. 31, a metal deposition was carried out to form contacts 51 and 52 of source and drain. The metal is notably deposited on either side of the silicided walls 61 and 62. In this case, a mechanochemical polishing was carried out following the deposition of the metal, in order to provide access to the coating grid 41.
    The thickness of the deposited silicon layer 7 is advantageously greater than the thickness of silicon consumed by the siliciding reaction. For example, for a layer of metal 6 made of Nickel, the thickness of the layer of Silicon 7 deposited must be at least 3.6 times greater than the thickness of the layer of Nickel 6 deposited. The thickness of the non-silicided layer at the end of this step is for example at least 3 nm. It is then possible to have a very large interface surface between the doped parts and the silicided parts, which reduces the electrical resistance of access.
    Such a method proves to be particularly advantageous when the minimum thickness of silicide which can be formed by the siliciding method is greater than the length of the longitudinal ends of the nanowires 12, 14 and 16 present under the spacers 18 and 19. This is is particularly advantageous when the width of the spacers 18 and 19 is reduced.
    According to a variant, it is possible to envisage depositing an amorphous material of a mixture of silicon and metal, on the layer of crystallized silicon 7, in place of the metallization step and the siliciding step. . Such a deposition can be carried out with the desired stoichiometry for the silicide. Such a deposit can be followed by annealing to give it a crystalline configuration, for example at a temperature of 450 ° C. for 60 seconds for NÎSÎ2.
    Figures 32 to 35 illustrate a transistor 1 at different stages of its manufacturing process, according to an example of a fifth embodiment of the invention. The method according to the fifth embodiment can repeat the different steps of the method of the first embodiment, implemented up to the configuration illustrated in FIG. 16.
    In FIG. 32, a dielectric layer 8 has been deposited. The dielectric layer is in particular in contact with the doped parts 125, 145, 165, 126, 146 and 166 of the nanowires 12, 14 and 16.
    For an N-type channel transistor 1, it may be advantageous to deposit a dielectric layer having an alignment of its conduction band with the conduction band of the channel material. We could for example use a dielectric layer 8 in T1O2, for channels based
    ICG011128 EN Text Depot.docx of Si or SiGe. The dielectric layer 8 may for example have a thickness of between 1 and 3 nm, for example 1.5 nm. The process for depositing the dielectric layer 8 is known per se to those skilled in the art.
    In FIG. 33, a full metal plate 9 layer has advantageously been deposited. The metal layer 9 is notably deposited on the dielectric layer 8, in alignment with the nanowires 12, 14 and 16. The deposited metal is intended to present a weak Schottky barrier with respect to the material of the channel zones. The deposited metal may for example be Zr. A contact MIS (for Metal Insulation Semiconductor in English) is thus formed at each longitudinal end of the nanowires 12, 14 and 16.
    In FIG. 34, a layer of metal 5 has been deposited. The metal is notably deposited on either side of the nanowires 12, 14 and 16, in order to be in contact with the metal layer 9. The metal of the layer 5 can for example be Ti, TiN or W. An electrical contact is thus formed between the metal layer 5 and the doped parts 125, 145, 165, 126, 146 and 166.
    In FIG. 35, a mechanochemical polishing was carried out in order to provide access to the coating grid 41, and an etching of the layer 5 was carried out to delimit contacts 51 and 52.
    The formation of MIS contacts makes it possible to benefit from a reduced electrical resistance between the contacts 51 and 52 and the nanowires 12, 14 and 16.
    The use of an intermediate metallic layer 9 made of material with a low Schottky barrier makes it possible to overcome the blocking effects of the Fermi level (which result in effective Schottky barriers higher than expected).
    It is also possible to envisage depositing a layer of amorphous silicon prior to the dielectric layer 8, then proceeding to the crystallization of the deposited amorphous silicon, then depositing the dielectric layer 8 on the crystallized silicon layer.
    When the initial configuration illustrated in FIG. 16 has doped parts obtained by plasma, the maximum concentration of dopants at the longitudinal ends of the nanowires is positioned at the interface with the dielectric material of the MIS contacts formed, which promotes low electrical resistance. of contact.
    FIG. 36 illustrates a sectional view of a structure obtained according to a variant of the method of the second embodiment. In this configuration, common contacts are used between transistors to induce longitudinal stresses in tension or compression in the middle part of their nanowires. In this example, a transistor 1 has been formed having contacts 51 and 52, and a transistor 2 having a contact 53 and sharing contact 52. Contacts 51 to 53 are for example in W. The presence of contact 52 between
    ICG011128 FR Depot Texte.docx transistors 1 and 2 allow for example to develop an intrinsic stress in compression.
    The embodiments described above are based on an initial superposition of layers of silicon and silicon germanium. One can however also consider other types of semiconductor materials in this superposition; One can for example consider making a superposition of nanowires of III-V type materials, for example InAs and InGaAs. The nanowire overlap can include nanowires made of at least three different semiconductor materials. It is then possible to use specific metallizations using a metallic alloy of the semiconductor, for example based on Ni, Pd, Ti, Au or Mo).
    In the embodiments described above, the nanowires have a substantially square cross section. Other cross sections can of course be envisaged, for example ovoid, trapezoidal or rectangular. Nanowires in the form of nanowires can for example be used, and thus have a cross section in which the width is at least equal to 2 times the height.
    In the embodiments described above, the transistor 1 has three nanowires to form as many superimposed channel zones. It is also possible to provide a superposition of any number of suitable nanowires, at least equal to 2.
    ICG011128 EN Text Depot.docx
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    1. Method for manufacturing a field effect transistor with a covering gate (41), characterized in that it comprises the steps of:
    -provide a substrate surmounted by first and second nanowires of semiconductor material (12,14) extending in the same longitudinal direction and arranged vertically from one another, each of these first and second nanowires having:
    a middle part (120, 140), covered by a first material (44); first and second ends (123, 143, 124, 144) formed on either side of the middle part in said longitudinal direction, the periphery of which is covered by respective first and second dielectric spacers (18, 19) in a second material different from the first material, said first and second ends respectively having first and second uncovered side faces;
    -doping part of the first and second ends by means of said first and second side faces;
    - depositing a metal on the other side of the first and second nanowires to form first and second metal contacts (51, 52) in electrical contact respectively with the doped parts of the first and second ends of the first and second nanowires.
    [2" id="c-fr-0002]
    2. Method for manufacturing a field effect transistor with a covering gate (41) according to claim 1, in which the doping of the first and second ends of said first and second nanowires is carried out by plasma, implantation, diffusion or dilution.
    [3" id="c-fr-0003]
    3. Method of manufacturing a field effect transistor with a covering grid (41) according to claim 1 or 2, in which said first material is a gate insulator (44), said gate insulator being covered by a conductive gate. (41).
    [4" id="c-fr-0004]
    4. Method for manufacturing a field effect transistor with a covering gate (41) according to any one of the preceding claims, in which the first and second nanowires (12, 14) are formed from a silicon alloy.
    [5" id="c-fr-0005]
    5. A method of manufacturing a field effect transistor with a covering gate (41) according to claim 4, further comprising a step of siliciding the first and second lateral faces of said doped parts of the first and second ends of the first and second nanowires. (12, 14).
    ICG011128 EN Text Depot.docx
    [6" id="c-fr-0006]
    6. A method of manufacturing a field effect transistor with a covering gate (41) according to claim 5, wherein said siliciding step comprises depositing a layer of metal (6) on said first and second lateral faces ( 123, 124, 143, 144) and annealing of the deposited metal.
    [7" id="c-fr-0007]
    7. Method for manufacturing a field effect transistor with a covering gate (41) according to claim 5 or 6, in which said first and second lateral faces (123,124,143,144) of said first and second nanowires supplied are recessed with respect to said first and second spacers (18, 19) respectively.
    [8" id="c-fr-0008]
    8. A method of manufacturing a field effect transistor with a covering gate (41) according to any one of claims 1 to 6, comprising a step of depositing an amorphous silicon alloy (7) on said first and second lateral faces (123, 124, 143, 144) of said first and second nanowires, then a step of crystallization of said silicon alloy.
    [9" id="c-fr-0009]
    9. A method of manufacturing a field effect transistor with a covering gate (41) according to any one of claims 1 to 4, further comprising a step of depositing a layer of dielectric material (8) on the parts. doped with the first and second nanowires, producing said metal deposit forming the first and second metal contacts (51, 52) on said layer of dielectric material.
    [10" id="c-fr-0010]
    10. A method of manufacturing a field effect transistor with a covering gate (41) according to claim 9, comprising a step of depositing an amorphous silicon alloy (7) on said first and second lateral faces (123, 124 , 143, 144) of said first and second nanowires, then a step of crystallization of said silicon alloy so as to extend said doped parts of the first and second nanowires, then carry out said step of depositing the layer of dielectric material.
    [11" id="c-fr-0011]
    11. A method of manufacturing a field effect transistor with a covering gate (41) according to claim 9 or 10, further comprising a step of siliciding the first and second lateral faces of said doped parts of the first and second ends of the first and second nanowire (12, 14).
    [12" id="c-fr-0012]
    12. Method for manufacturing a field effect transistor with a covering gate (41) according to any one of the preceding claims, in which said first and second ends of the first and second nanowires each have a length of between 5 and 10 nm. .
    ICG011128 EN Text Depot.docx
    [13" id="c-fr-0013]
    13. A method of manufacturing a field effect transistor with a covering gate (41) according to any one of the preceding claims, comprising a step of depositing a layer of dielectric material on said first and second lateral faces of said doped parts. first and second nanowires, said metal deposit being produced on said layer of dielectric material so as to form said first and second metal contacts in the form of an MIS type contact.
    [14" id="c-fr-0014]
    14. A method of manufacturing a field effect transistor with a covering gate (41) according to any one of the preceding claims, in which said first and second nanowires supplied have a thickness at most equal to 15 nm.
    [15" id="c-fr-0015]
    15. Field effect transistor (1) with a covering grid (41), characterized in that it comprises:
    a substrate surmounted by first and second nanowires of semiconductor material (12, 14) extending in the same longitudinal direction and arranged vertically from one another, each of these first and second nanowires having:
    a middle part (120, 140), covered by a first material (44); first and second ends (123, 143, 124, 144) formed on either side of the middle part in said longitudinal direction, the periphery of which is covered by respective first and second dielectric spacers (18, 19) in a second material different from the first material, said first and second ends having respective doped parts having a dopant at a concentration greater than that of their middle part;
    first and second metal contacts (51, 52) in electrical contact respectively with the doped parts of the first and second ends of the first and second nanowires.
    ICG011128 FR Text Depot.docx 32 31 33
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    FR3064815B1|2019-11-08|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1752741|2017-03-31|
    FR1752741A|FR3064815B1|2017-03-31|2017-03-31|METHOD FOR MANUFACTURING A COILGROUND FIELD EFFECT TRANSISTOR|FR1752741A| FR3064815B1|2017-03-31|2017-03-31|METHOD FOR MANUFACTURING A COILGROUND FIELD EFFECT TRANSISTOR|
    US15/938,321| US10256102B2|2017-03-31|2018-03-28|Method for fabricating a field effect transistor having a surrounding grid|
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