• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Integrated artificial neuron device comprising a refractory block (3) configured to inhibit the integrator block (1) during an inhibition period after said delivery of at least one output signal (Si) by the generator block (2), the refractory block (3) comprising a first MOS transistor (Ts1) coupled between the input terminal (BE) and the reference terminal (BR) and whose gate (Gs1) is connected to said output terminal (BS) by the intermediate of a second MOS transistor (Ts2) of which a first electrode (Ds2) is coupled to said supply terminal (BV) and whose gate (Gs2) is coupled to the output terminal (BS), the refractory block (3) further comprising a resistive-capacitive circuit coupled between the supply terminal (BV), the reference terminal (BR) and the gate of the second MOS transistor (Ts2), said inhibition time being dependent on the constant of time of said resistive-capacitive circuit.
    公开号:FR3064384A1
    申请号:FR1752384
    申请日:2017-03-23
    公开日:2018-09-28
    发明作者:Philippe Galy；Thomas Bedecarrats
    申请人:STMicroelectronics SA；
    IPC主号:
    专利说明:

    (57) Integrated artificial neuron device comprising a refractory block (3) configured to inhibit the integrating block (1) during an inhibition period after said delivery of at least one output signal (Si) by the generator block (2 ), the refractory block (3) comprising a first MOS transistor (Ts1) coupled between the input terminal (BE) and the reference terminal (BR) and whose gate (Gs1) is connected to said output terminal (BS ) via a second MOS transistor (Ts2), a first electrode (Ds2) of which is coupled to said supply terminal (BV) and the gate of which (Gs2) is coupled to the output terminal (BS), the refractory block (3) further comprising a resistive-capacitive circuit coupled between the power supply terminal (BV), the reference terminal (BR) and the gate of the second MOS transistor (Ts2), said inhibition time depending on the time constant of said resistive-capacitive circuit.

    i
    Refractory block for integrated artificial neuron device
    Embodiments of the invention relate to artificial intelligence, and in particular the creation of neural networks in the context in particular of deep learning, known by a person skilled in the art under the Anglo-Saxon name "Deep learning" . More specifically, embodiments relate to integrated electronic circuits simulating the behavior of neurons, and more particularly the structure of the refractory blocks of such circuits.
    A biological neuron comprises several parts, including in particular one or more dendrites which deliver an electrical input signal, the body of the neuron or soma, which accumulates the input signal in the form of a potential difference between the interior and the outside of its membrane, and an axon intended to deliver an output signal, or action potential when the voltage between the outside and the inside of the membrane reaches a certain threshold. In a biological neuron, electrical leaks occur through the membrane if the electrical balance is not reached between the inside and the outside of the membrane.
    Thus, an artificial neuron should be capable of receiving an input signal, of integrating this input signal, and when the integrated signal reaches a threshold, of transmitting an output signal in the form of a or more voltage spikes.
    In the field of artificial neural networks, the acronym LIF (“Leaky, Integrate and Fire”) designates a simple behavior model of the artificial neuron, in which the latter receives and accumulates an input signal up to to exceed a threshold value, beyond which the neuron emits an output signal.
    This model takes into account in particular the electrical leakage of the neuron through the membrane thereof.
    The neuron can either receive a series of successive current peaks up to the generation of an output current peak, or receive a continuous signal at input and generate a train of current peaks at output.
    It has also been observed that neurons exhibit a period of refraction, or inhibition period, immediately after the delivery of an action potential by the axon, during which the neuron is inhibited.
    This inhibition period should then be reproduced in order to get as close as possible to the functioning of a biological neuron.
    There are solutions for producing artificial neurons according to the LIF model, making it possible to implement a period of refraction, comprising for example several tens of large components.
    Applications in the field of artificial intelligence, such as, for example but not limited to simulating brain activity, require the creation of networks comprising a very large number of artificial neurons, typically of the order of a billion. It would thus be very advantageous to use integrated circuits of reduced size.
    There are solutions using smaller neurons and allowing higher operating speeds, but these solutions require the implementation of specific manufacturing processes.
    Thus, according to one embodiment, an artificial neuron is proposed, allowing the implementation of a refractive period and having a limited refractory block surface, and which can advantageously be produced by conventional CMOS manufacturing methods.
    According to one aspect, an integrated artificial neuron device is proposed, comprising an input terminal intended to receive at least one input signal, an output terminal intended to deliver at least one output signal, a reference terminal intended to deliver at least one reference signal, a supply terminal intended to receive a supply voltage, an integrator block configured to receive and integrate said at least one input signal and to deliver an integrated signal, a generator block configured to receive the integrated signal and, when the integrated signal exceeds a threshold, deliver the output signal.
    The device further comprises a refractory block configured to inhibit the integrator block during an inhibition period after said delivery of said at least one output signal by the generator block, the refractory block comprising a first MOS transistor of which a first electrode is coupled to the input terminal, a second electrode is coupled to the reference terminal and whose gate is connected to said output terminal via a second MOS transistor, a first electrode of which is coupled to said supply terminal, a second electrode of which is coupled to the gate of the first MOS transistor, and the gate of which is coupled to the output terminal, the refractory block further comprising a capacitive resistive circuit coupled between the supply terminal, the reference terminal and the gate of the second MOS transistor, said inhibition duration depending on the time constant of said resistor circuit stifcapacitive.
    The neuron device comprising a refractory block therefore behaves even closer to that of a biological neuron.
    In addition, the use of a reduced number of components allows a reduced surface of the refractory block.
    The resistive-capacitive circuit may include a capacitor, a first electrode of which is coupled between said power supply terminal and the gate of the first MOS transistor, and a resistor coupled between the gate of the second MOS transistor and the reference terminal.
    The capacitor is advantageously an MOS capacitor.
    According to another aspect, an integrated circuit is proposed comprising an artificial neural network comprising a plurality of devices such as those described above.
    Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments of the invention, in no way limiting, and the attached drawings in which:
    - Figures 1 and 2 illustrate embodiments of the invention.
    FIG. 1 schematically illustrates, from an electrical point of view, an integrated DIS device of an artificial neuron DIS, produced in and on a semiconductor substrate which can either be a solid substrate or a substrate of silicon on insulator type, and configured to notably implement the LIF neuron model.
    The DIS neuron device therefore operates here similar to that of a biological neuron.
    The device DIS includes an input terminal BE, intended to receive an input signal Se, an output terminal BS, intended to deliver an output signal Ss, and a reference terminal BR intended to receive a reference voltage, for example here the mass.
    The input signal can come from a single source or be the combination at the BE terminal of several different signals from different sources.
    The device DIS also includes an integrator block 1, configured to receive and integrate the input signal Se and to deliver an integrated input signal Si, and a generator block 2, configured for, when the integrated signal reaches a threshold (or "Trip threshold"), deliver the output signal Ss.
    The integrator jar 1 and the generator block 2 may each include one or more components which can be arranged according to any structure of the prior art, such as that described
    - in the article "Xinyu Wu, V. Saxena and Kehan Zhu, A
    CMOS spiking neuron for dense memristor-synapse connectivity for brain-inspired computing, 2015
    Joint Conference on Neural Networks Killarney, 2015, pp. 1-6.
    doi: 10.1109 / IJCNN.2015. 7280819 ", or
    - in the article "Indiveri G., Linares-Barranco B., Hamilton T. J., van Schaik A., Etienne-Cummings R., Delbruck T., and
    International (IJCNN), al. (2011). Neuromorphic Silicon neuron circuits. Forehead. Neurosci. 5:73. 10.3389 / fnins. 2011. ", or
    - in the French patent application filed on the same day as this patent application in the name of the applicant and entitled "Integrated device of artificial neuron".
    The neuron device DIS also comprises a refractory block 3 configured to inhibit the integrator block 1 during an inhibition period, and a supply terminal BV intended to receive a supply voltage Vdd, for example here a voltage of one volt.
    Indeed, it has been observed that biological neurons are inhibited during a period following the delivery of an action potential by the axon of the neuron.
    This refractory block 3 therefore aims to bring the functioning of the DIS neuron device even closer to the functioning of a biological neuron.
    The refractory block 3 comprises a first transistor Tsl, of which a first electrode, here the drain Dsl, is coupled to the input terminal, and of which a second electrode, here the source Ssl, is coupled to the reference terminal.
    The gate Gsl of the first transistor Tsl is coupled to a common node N.
    A second transistor Ts2 has its gate coupled to the output terminal BS, a first electrode, here the drain Ds2, coupled to the supply terminal BV, and a second electrode, here the source Ss2, coupled to the common node N.
    Depending on the structure chosen for generator block 2, the value of the voltage Ss (output signal) may be different. Also depending on the case, the gate of the transistors Ts2 can be coupled directly to the terminal Bs or else indirectly via a conventional voltage matching circuit, so that the characteristics of the output signal Ss are compatible. with those of transistor Ts2.
    A capacitor Cs is coupled between the supply terminal BV and the common node N. The capacitor Cs is here an MOS capacitor having for example a surface of a square micrometer.
    A resistor Rs, for example here a resistance of one gigaohm which can be achieved in practice by a MOS transistor in the on state, is coupled between the common node N and the reference terminal BF.
    Thus in operation, before the appearance of a voltage peak on the output terminal, the capacitor Cs is charged and the voltage at its terminals is equal to the voltage Vdd.
    The potential of the common node N is therefore zero, and the gate of the first transistor Tsl is not polarized.
    In the presence of a current peak on the output terminal, the gate Gs2 of the second transistor is polarized and the second transistor Ts2 becomes conducting.
    The gate of the first transistor Tsl is therefore biased at the voltage Vdd by means of the second transistor Ts2, and the first transistor Tsl therefore becomes on, thus short-circuiting the capacitor Cs.
    The potential of the common node N, and therefore the gate Gsl of the first transistor Tsl, is biased at the supply voltage Vdd, and the first transistor Tsl becomes conducting, thus short-circuiting the integrator block 1.
    Once the current peak on the output terminal passed, the second transistor Ts2 is blocked again, the voltage across the capacitor Cs increases gradually, and the potential of the common node therefore decreases gradually until reaching a zero value when the capacitor is fully charged.
    When the potential of the common node reaches a value lower than the triggering threshold of the first transistor, the first transistor is blocked again.
    Thus, inhibition of the integrator block by the refractory block takes place during an inhibition period which depends on the charge speed of the capacitor Cs through the resistor Rs.
    The duration of inhibition therefore depends on the time constant of the resistive-capacitive circuit comprising the resistor Rs and the capacitor Cs.
    The structure of such a refractory block is advantageous compared to the refractory blocks of the prior art in that it has a reduced number of components, and consequently makes it possible to obtain a refractory block whose surface is smaller. to two square micrometers. As an indication, for a CMOS technology of twenty eight nanometers, the surface of the refractory block is of the order of two square micrometers.
    According to an embodiment illustrated in FIG. 2, it is possible to have an integrated circuit CI comprising a network of artificial neurons, comprising a plurality of neuron devices according to one or more of the embodiments described previously in connection with the figure 1, coupled together via their input or output terminal.
    权利要求:
    Claims (4)
    [1" id="c-fr-0001]
    1. Integrated artificial neuron device, comprising an input terminal (BE) intended to receive at least one input signal (Se), an output terminal (BS) intended to deliver at least one output signal (Ss) , a reference terminal (BR) intended to receive a reference voltage, a supply terminal (BV) intended to receive a supply voltage, an integrator block (1) configured to receive and integrate said at least one signal d input (Se) and deliver an integrated signal (Si), a generator block (2) configured to receive the integrated signal (Si) and, when the integrated signal (Si) exceeds a threshold, deliver the output signal, and a refractory block (3) configured to inhibit the integrator block (1) during an inhibition period after said delivery of said at least one output signal (Si) by the generator block (2), the refractory block (3) comprising a first MOS transistor (Tsl) including a first electrode (Dsl) is coupled to the input terminal (BE), a second electrode (Ssl) is coupled to the reference terminal (BR) and whose gate (Gsl) is connected to said output terminal (BS) by l intermediary of a second MOS transistor (Ts2) of which a first electrode (Ds2) is coupled to said supply terminal (BV), of which a second electrode is coupled to the gate of the first MOS transistor, and of which the gate (Gs2 ) is coupled to the output terminal (BS), the refractory block (3) further comprising a capacitive resistive circuit coupled between the power supply terminal (BV), the reference terminal (BR) and the gate of the second MOS transistor (Ts2), said inhibition duration depending on the time constant of said resistive-capacitive circuit.
    [2" id="c-fr-0002]
    2. Device according to claim 1, in which the resistive-capacitive circuit comprises a capacitor (Cs) coupled between said supply terminal (BV) and the gate (Gsl) of the first MOS transistor, and a resistor (Rs) coupled between the gate of the second MOS transistor and the reference terminal (BR).
    [3" id="c-fr-0003]
    3. Device according to claim 2, wherein the capacitor (Cs) is a CMOS capacitor.
    [4" id="c-fr-0004]
    4. Integrated circuit comprising an artificial neural network comprising a plurality of devices according to one of claims 1 to 3.
    1/1
    类似技术:
    公开号 | 公开日 | 专利标题
    FR3064384A1|2018-09-28|REFRACTORY BLOCK FOR INTEGRATED ARTIFICIAL NEURONE DEVICE
    EP1079525A1|2001-02-28|System for controlling a two-transistor bidirectional switch
    EP2819068A2|2014-12-31|Artificial neuron including a resistive memory
    FR3050050A1|2017-10-13|ARTIFICIAL NEURONE
    EP2600125B1|2016-04-20|Radiation-detection device with improved illumination range
    FR2984604A1|2013-06-21|COMPACT ELECTRONIC DEVICE FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES.
    FR3070774A1|2019-03-08|VOLTAGE DROP COMPENSATION METHOD ON USB TYPE C CABLE AND CORRESPONDING CIRCUIT
    FR3064383B1|2019-11-15|INTEGRATED ARTIFICIAL NEURONE DEVICE
    EP0022015A1|1981-01-07|Amplifier arrangement and method of amplification for audio frequencies
    CA3013842C|2021-07-27|Circuit for detecting light pulses
    EP0096756B1|1988-07-27|Electronic subscriber junctor
    FR2534751A1|1984-04-20|RESTORATION CIRCUIT AT POWER ON FOR AN ELECTRICAL CONTROL SYSTEM
    EP1553677A1|2005-07-13|Equalising the voltages ofelectrochemical generators in rechargeable batteries throughcircuits
    WO2002052364A1|2002-07-04|Voltage regulator with static gain in reduced open loop
    EP1040580A1|2000-10-04|Cmos output amplifier independent of temperature, supply voltage and manufacturing quality of transistors
    EP1487106A1|2004-12-15|Integrated circuit producing power supply independent logic levels without regulators in the power section and a corresponding communication module.
    EP2463632B1|2013-06-05|Detection device comprising a robust test circuit
    FR3072564B1|2019-10-18|OPTICAL SENSOR
    EP2783192A1|2014-10-01|Detection circuit with a noise-reduction module
    FR3063574A1|2018-09-07|COMPACT DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES
    FR3059805A1|2018-06-08|ARTIFICIAL SYNAPSE MODULATION DEVICE AND METHOD COMPRISING SAID MODULATION DEVICE, SHORT-TERM PLASTICITY METHOD IN ARTIFICIAL NEURON NETWORK COMPRISING SAID ARTIFICIAL SYNAPSE
    FR2631503A1|1989-11-17|Interfacing circuit for delivering analogue clock signals to a charge transfer device
    EP2717462A1|2014-04-09|Method for controlling a microinverter
    FR2829599A1|2003-03-14|BUS CONTROL CIRCUIT
    FR2659809A1|1991-09-20|FIELD EFFECT TRANSISTOR LIMITER DEVICE
    同族专利:
    公开号 | 公开日
    CN207319273U|2018-05-04|
    US20180276536A1|2018-09-27|
    FR3064384B1|2019-05-03|
    CN108629404A|2018-10-09|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US6242988B1|1999-09-29|2001-06-05|Lucent Technologies Inc.|Spiking neuron circuit|
    CN101997538B|2009-08-19|2013-06-05|中国科学院半导体研究所|Pulse coupling based silicon-nanowire complementary metal oxide semiconductors neuronal circuit|
    CN102610274B|2012-04-06|2014-10-15|电子科技大学|Weight adjustment circuit for variable-resistance synapses|
    WO2014018078A1|2012-07-25|2014-01-30|Hrl Laboratories, Llc|Neuron circuit and method|
    US9542643B2|2013-05-21|2017-01-10|Qualcomm Incorporated|Efficient hardware implementation of spiking networks|KR20180112458A|2017-04-04|2018-10-12|에스케이하이닉스 주식회사|Synapse Having Two Transistors and One Variable Resistive Device and a Synapse Array Including the Synapse|
    CN109376853B|2018-10-26|2021-09-24|电子科技大学|Echo state neural network output axon circuit|
    WO2021092899A1|2019-11-15|2021-05-20|江苏时代全芯存储科技股份有限公司|Neural-like circuit and operation method|
    法律状态:
    2018-02-19| PLFP| Fee payment|Year of fee payment: 2 |
    2018-09-28| PLSC| Publication of the preliminary search report|Effective date: 20180928 |
    2019-02-20| PLFP| Fee payment|Year of fee payment: 3 |
    2020-02-20| PLFP| Fee payment|Year of fee payment: 4 |
    2021-12-10| ST| Notification of lapse|Effective date: 20211105 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1752384A|FR3064384B1|2017-03-23|2017-03-23|REFRACTORY BLOCK FOR INTEGRATED ARTIFICIAL NEURONE DEVICE|
    FR1752384|2017-03-23|FR1752384A| FR3064384B1|2017-03-23|2017-03-23|REFRACTORY BLOCK FOR INTEGRATED ARTIFICIAL NEURONE DEVICE|
    CN201721105807.7U| CN207319273U|2017-03-23|2017-08-31|Artificial neuron component sum aggregate is integrated into circuit|
    CN201710770721.4A| CN108629404A|2017-03-23|2017-08-31|Circuit is not answered for integrate artificial neuron component|
    US15/697,598| US20180276536A1|2017-03-23|2017-09-07|Refractory circuit for integrated artificial neuron device|
    [返回顶部]