• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An integrated circuit, comprising a semiconductor substrate (SB) having a rear face (FR) and a front face (FV) and including an assembly of at least one semiconductor well (CS1, CS2) electrically isolated from the remainder (3) of the substrate, and a device (DIS) for detecting a thinning of the substrate by its rear face, said device (DIS) comprising a group of at least one first trench (TR11) extending in said at least one box between two locations of its periphery and from said front face to a location remote from the bottom of said at least one box, said at least one first trench (TR11) being electrically isolated from the box, and detection means (4) configured to measure a physical quantity representative of the electrical resistance of the box between two contact zones (ZC1, ZC2) located respectively on either side of said group of at least one first trench.
    公开号:FR3063385A1
    申请号:FR1751595
    申请日:2017-02-28
    公开日:2018-08-31
    发明作者:Abderrezak Marzaki
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    © Publication no .: 3,063,385 (to be used only for reproduction orders)
    ©) National registration number: 17 51595 ® FRENCH REPUBLIC
    NATIONAL INSTITUTE OF INDUSTRIAL PROPERTY
    COURBEVOIE © Int Cl 8 : H 01 L 21/66 (2017.01), H 01 L 21/02, H 05 K 1/02
    A1 PATENT APPLICATION
    ©) Date of filing: 28.02.17. © Applicant (s): STMICROELECTRONICS (ROUS- (© Priority: SET) SAS - FR. @ Inventor (s): MARZAKI ABDERREZAK. ©) Date of public availability of the request: 31.08.18 Bulletin 18/35. ©) List of documents cited in the report preliminary research: Refer to end of present booklet (© References to other national documents ® Holder (s): STMICROELECTRONICS (ROUSSET) related: SAS. ©) Extension request (s): (© Agent (s): CASALONGA.
    INTEGRATED CIRCUIT WITH DETECTION OF THINNING FROM THE REAR PANEL AND DECOUPLING CAPACITORS.
    FR 3,063,385 - A1 (97) Integrated circuit, comprising a semiconductor substrate (SB) having a rear face (FR) and a front face (FV) and including an assembly of at least one semiconductor case (CS1, CS2) electrically isolated from the rest (3) of the substrate, and a device (DIS) for detecting a thinning of the substrate by its rear face, said device (DIS) comprising a group of at least a first trench (TR11) extending in said at least one box between two locations on its periphery and from said front face to a location located at a distance from the bottom of said at least one box, said at least one first trench (TR11) being electrically isolated from the box, and means detection (4) configured to measure a physical quantity representative of the electrical resistance of the box between two contact zones (ZC1, ZC2) respectively located on either side of said group of at least a first trench.

    i
    Integrated circuit with rear thinning detection and decoupling capacitors
    Embodiments of the invention relate to integrated circuits, and more particularly the detection of a possible thinning of the substrate of an integrated circuit from its rear face.
    Integrated circuits, in particular those equipped with memories containing sensitive information, must be protected as much as possible against attacks, in particular intended to discover stored data.
    A possible attack can be carried out by a focused ion beam (FIB Focus Ion Beam), for example by means of a laser beam.
    The effectiveness of such an attack increases when the substrate of the integrated circuit is thinned by the attacker, from its rear face so as to come as close as possible to the components of the integrated circuit, produced at its front face.
    According to one embodiment and embodiment, it is therefore proposed to detect a possible thinning of the substrate of an integrated circuit from its rear face, which is simple to implement and particularly compact in terms of size. surface.
    In addition, integrated circuits can also be fitted with decoupling capacitors between the supply voltage and ground, more commonly known to those skilled in the art under the Anglo-Saxon expression: "filler cap".
    According to one embodiment, it is proposed to use at least part of the thinning detection device for producing decoupling capacitors.
    According to one aspect, an integrated circuit is proposed comprising a semiconductor substrate having a rear face and a front face and including a set of at least one semiconductor box electrically isolated from the rest of the substrate (the set may possibly include several semiconductor boxes) .
    The integrated circuit also comprises a device for detecting a thinning of the substrate by its rear face, this device comprising a group of at least a first trench (the group possibly comprising several first trenches) extending in said at least a box between two locations on its periphery and from the front face of the substrate to a location located at a distance from the bottom of said at least one box.
    Said at least a first trench is electrically isolated from the box.
    The detection device comprises detection means configured to measure a physical quantity representative of the electrical resistance of the box between two contact zones located respectively on either side of said group of at least one first trench.
    Thus, according to this aspect, said at least one trench is directly produced in the semiconductor box, typically an active area, which is simple to perform and advantageous from a surface congestion point of view.
    The trench extends away from the bottom of the caisson. Consequently, if the substrate is thinned until it comes to thin the box, the electrical resistance of the latter will increase, which will make it possible to detect this thinning.
    The physical quantity representative of this resistance can be the resistance itself, or a current or a voltage.
    Although it is possible to use this detection device in a semiconductor well of conductivity type N arranged in a semiconductor substrate of type P, it is particularly advantageous to produce the first trench (s) in a well of conductivity type P electrically isolated from the rest of the substrate by a structure of the triple well type (“triple well”). In fact, the surface area of such a P-type box is smaller compared to that of an N-type box, in particular as regards its lateral insulation.
    Thus, according to one embodiment, the substrate and said at least one box are of conductivity type P and said at least one box is electrically isolated from the substrate by an insulation region comprising an insulating peripheral trench, for example a trench of the Shallow Trench Isolation type (STI) extending into the substrate from the front face and surrounding said at least one box.
    The isolation region also comprises a semiconductor layer of conductivity type N buried in the substrate under said at least one well (this buried layer is commonly designated by a person skilled in the art under the acronym "NISO").
    The isolation region also includes an intermediate peripheral insulating zone surrounding said at least one box and configured to provide continuity of electrical insulation between said buried semiconductor layer and the insulating peripheral trench.
    Said at least a first trench then extends at least between two places of the insulating peripheral trench.
    According to a first possible variant embodiment, the isolation region comprises an additional peripheral trench having at least one insulating envelope, extending from said front face through said insulating peripheral trench (for example of the shallow trench type) and having a lower part extending under this insulating peripheral trench up to contact with said buried semiconductor layer.
    According to another possible alternative embodiment, this additional peripheral trench having at least one insulating envelope extends from the front face through said insulating peripheral trench and has a lower part extending under this insulating peripheral trench at a distance from the semiconductor layer buried and an implanted zone of conductivity type N situated between said lower part and said buried semiconductor layer.
    In other words, in this variant, the additional peripheral trench does not come into contact with the buried insulating layer and the insulation of the box is then carried out by this implanted zone of type of conductivity N.
    Said at least a first trench can then extend between two locations of the additional peripheral trench.
    This additional peripheral trench can be completely insulating.
    It can be the same for said at least one first trench.
    By way of example, the detection means may include polarization means configured to apply a potential difference between said two contact areas, as well as measurement means configured to measure the current flowing between said two contact areas.
    Instead of the additional peripheral trench and said at least one first trench being completely insulating, they may each comprise an electrically conductive central region, for example polysilicon, wrapped in an insulating envelope, for example silicon dioxide.
    In this case, these trenches can also be used to form decoupling capacitors.
    In this regard, according to one embodiment, said group may include several first parallel trenches connecting two opposite edges of said additional peripheral trench.
    The detection means can then comprise first polarization means configured to apply a first potential difference between said two contact zones and measurement means configured to measure the current flowing between said two contact zones, and the integrated circuit can comprise second polarization means configured to apply a second potential difference between the central region of said additional peripheral trench and said at least one semiconductor box (which makes it possible to produce the decoupling capacitors between the supply voltage and the ground).
    The invention is also advantageously compatible with the production, within the integrated circuit, of a memory device comprising a memory plane having non-volatile memory cells and selection transistors with buried gate since said at least one first trench can have a depth substantially equal to that of said buried grids.
    When the integrated circuit comprises several boxes, the device may further comprise coupling means configured to couple two adjacent boxes electrically in series so as to form a chain of boxes electrically coupled in series, the coupling means being arranged between the two groups at least a first trench extending respectively into said two adjacent boxes.
    The two contact zones are then respectively located on either side of the two groups of at least a first trench extending respectively into the two boxes respectively located at the two ends of said chain.
    The detection means are then configured to measure a physical quantity representative of the electrical resistance of the box chain between said two contact zones.
    Such a structure of chained boxes can also be used as such, that is to say not necessarily in combination with a device for detecting a thinning of the substrate, so as to create in the integrated circuit a circuit or path resistive having a high resistive value while having a reduced bulk, which is particularly advantageous in analog applications.
    Thus according to another aspect an integrated circuit is proposed, comprising a semiconductor substrate having a rear face and a front face and including a set of several (at least two) semiconductor boxes electrically isolated from the rest of the substrate, a group of at least a first trench extending in each box between two locations on its periphery and from said front face to a location located at a distance from the bottom of said box, said at least one first trench being electrically isolated from said box, configured coupling means for electrically coupling in series two adjacent caissons so as to form a chain of electrically coupled caissons in series, the coupling means being arranged between the two groups of at least one first trench extending respectively into said two adjacent caissons, and two contact areas respectively located on either side of the two grou pes of at least a first trench extending respectively into the two boxes respectively located at the two ends of said chain, so as to form a resistive circuit extending between said two contact zones.
    According to another aspect, an object is proposed, for example a smart card or an electronic device, such as for example a cellular mobile telephone or a tablet, comprising an integrated circuit as defined above.
    According to another aspect, a method is proposed for detecting a thinning of the semiconductor substrate of an integrated circuit from its rear face, the substrate including a set of at least one semiconductor box electrically isolated from the rest of the substrate and comprising a group of at least a first trench extending in said at least one box between two locations on its periphery and from the front face of the substrate to a location located at a distance from the bottom of said at least one box, said at least one the first trench being electrically isolated from the box, the method comprising a measurement of a physical quantity representative of the electrical resistance of the box between two contact zones respectively located on either side of said group of at least one first trench.
    Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiments, in no way limiting, and the appended drawings in which:
    FIGS. 1 to 11 schematically illustrate different modes of implementation and embodiment of the invention.
    In FIG. 1 and in FIG. 2, the reference IC designates an integrated circuit comprising in particular a set ENS1 of semiconductor wells here of conductivity type P, produced within a semiconductor substrate SB also of conductivity type P.
    In the example described here, the ENS1 assembly includes two semiconductor wells CS1 and CS2. For the sake of simplification of the figures, only the box CS1 is shown in FIG. 1 and, therefore, the left part of FIG. 2 is a sectional view along the line II-II of FIG. 1.
    As will be seen now, each well CS1, CS2 is electrically isolated from the lower part 3 of the substrate SB by an isolation region comprising a certain number of elements.
    More particularly, if, for the sake of simplification, reference is made only to the box CS1, it can be seen that the isolation region comprises an insulating peripheral trench 1, for example of the shallow trench type (STI: “Shallow Trench Isolation ”) Surrounding the housing CS1 and extending into the substrate from the front face FV or upper face.
    The isolation region also includes a semiconductor layer 2, buried in the substrate, under the well CS1 and moreover also under the well CS2, and of conductivity type N.
    The isolation region also includes an intermediate peripheral insulating zone surrounding the box CS1 and configured to ensure continuity of electrical insulation between the buried semiconductor layer 2 and the insulating peripheral trench 1.
    In the example illustrated in FIG. 1 and in FIG. 2, the isolation region comprises an additional peripheral trench TR3 extending from the front face FV through the insulating peripheral trench 1 and having a lower portion TR1200 extending under this insulating peripheral trench 1 until contact with the buried semiconductor layer.
    This lower part TR1200 here forms the intermediate peripheral insulating zone which makes it possible to ensure the continuity of electrical insulation between the buried semiconductor layer 2 and the peripheral insulating trench 1.
    As can be seen in these figures 1 and 2, the additional peripheral trench TR3 which surrounds the box CS1, is here rectangular in shape and has two first parallel branches TR12 here forming the short sides of the rectangle and two other parallel branches TR31 and TR32 forming the two long sides of the rectangle.
    In the example illustrated in these Figures 1 and 2, this additional peripheral trench TR3 is fully insulating and comprises, for example, silicon dioxide.
    The integrated circuit IC also includes a device DIS for detecting a thinning of the substrate SB by its rear face FR.
    The device DIS here comprises a first trench TR11 extending in the box CS1 between two locations of the additional peripheral trench TR3, and more particularly between the two opposite edges TR31 and TR32 of this additional peripheral trench.
    The first trench TR11 extends from the front face FV to a location located at a distance from the bottom of the box CS1, that is to say here at a distance from the buried semiconductor layer 2.
    The depth of this first trench TR11 is noted PR.
    This first trench is electrically isolated from the box.
    In this respect, in the embodiment illustrated in FIGS. 1 and 2, the first trench TR11 is completely insulating and includes, for example, silicon dioxide.
    A first trench TR21, of structure similar to the first trench TR11, is produced in the other semiconductor well CS2 whose lateral isolation region includes another additional peripheral trench TR3.
    The DIS device also includes detection means 4 configured to measure a physical quantity representative of the electrical resistance of the box CS1 between two contact zones ZC1, ZC2 respectively located on either side of the first trench TR11.
    By analogy, the device DIS also comprises detection means 4 configured to measure a physical quantity representative of the electrical resistance of the box CS2 between two contact zones ZC3 and ZC4 respectively located on either side of the first corresponding trench TR21.
    Indeed, the measurement of this physical quantity representative of the electrical resistance of a box makes it possible to detect the thinning of the substrate SB from its rear face.
    Indeed, the more the substrate SB will be thinned up to thin the corresponding box CSi, the more the electrical resistance of this box CSi will increase until becoming almost infinite when the thinning has reached the lower end of the first corresponding trench TR11 (TR21).
    In this regard, by way of nonlimiting example, the detection means 4 may comprise biasing means 40 configured to apply a potential difference between the two contact zones ZC1, ZC2, for example a supply voltage VDD on contact ZC1 and ground on contact ZC2, and measuring means 41 configured to measure the current flowing between the two contact zones.
    There may also be provided comparison means capable of comparing the measured value of the current with a reference value corresponding to the value of the current in the absence of a thinning of the box.
    As a variant, it would also be possible to provide for the detection means to include a comparator whose non-inverting input would be connected to a voltage divider bridge and whose inverting ίο input would be connected to one of the contacts ZC1 or ZC2. The comparator then compares the voltage present on the contact with the reference voltage supplied by the voltage divider and delivers a signal whose value is representative of the fact that the voltage present on the contact is lower or not than the reference voltage.
    And this voltage is indeed a quantity representative of the current flowing in the resistive path formed by the two contact zones ZC1 and ZC2 and the box Cl, and in particular the resistance of this box CS1.
    FIG. 3 illustrates an alternative embodiment of the intermediate peripheral insulating zone surrounding the box CS1 and configured to ensure continuity of electrical insulation between the buried semiconductor layer 2 and the insulating peripheral layer
    1.
    In this embodiment, the lower part TR1200 of the additional peripheral trench TR3 does not come into contact with the buried semiconductor zone 2. And, the intermediate peripheral insulating zone then comprises this lower part TR1200 as well as an implanted zone 50 of the type of conductivity N (and therefore of conductivity type identical to the type of conductivity of layer 2) located between said lower part TR1200 and the buried semiconductor layer 2.
    It should be noted that the first TRI 1 trench is also extended by an implanted zone of conductivity type N, referenced 51, which makes it possible to increase the depth and to approach even closer to the buried semiconductor layer 2.
    While in the embodiments which have just been described, each first trench and each additional peripheral trench are completely insulating, it is possible, as illustrated in FIG. 4, that each first trench (referenced TRI 10 in FIG. 4) and each additional peripheral trench (referenced TR130 in FIG. 4) each comprise an electrically conductive central region RC, for example made of polysilicon, wrapped in an insulating envelope ENV, for example made of silicon dioxide.
    And, as illustrated in FIG. 4, such a TRI 10 trench (TR130) can advantageously be supplemented by an implanted zone of conductivity type N 50 (51).
    The use of trenches comprising an electrically conductive central region wrapped in an insulating envelope ENV makes it possible to use these trenches to form decoupling capacitors as will be explained in more detail below.
    As we have just seen, the bottom of the first trench TR11 may be at a distance from the buried semiconductor layer 3.
    This is compatible with a method of producing a memory device (produced in another location of the integrated circuit), the memory plane PM of which, as illustrated diagrammatically in FIG. 5, non-volatile memory cells CEL and selection transistors with TSL buried grid.
    More specifically, each CEL memory cell comprises a floating gate transistor TGF produced in and on a P-type semiconductor well separated from the underlying P-type substrate by an N-type semiconductor layer (not shown here for simplification purposes ).
    Conventionally, each floating gate transistor comprises a floating gate GF, for example made of polysilicon, and a control gate CG.
    Each selection transistor TSL makes it possible to select a row of cells and is a MOS transistor whose gate GTSL is a gate buried in the P-type well and electrically isolated from this well by an OX gate oxide, typically silicon dioxide.
    The GTSL buried gate is common to the two adjacent TSL selection transistors, the two gate oxides of which OX are respectively located on the two sides of this buried gate.
    And, as illustrated in FIG. 5, the depth PR of the trenches which allowed the realization of the buried selection grids GTSL is then advantageously identical or substantially identical to the depth PR of each first trench TR11.
    Reference is now made more particularly to FIGS. 6 to 8 to describe a trench structure making it possible to combine a detection of a thinning of the substrate by the rear face and a formation of decoupling capacitors between the supply voltage VDD and the ground GND .
    In this regard, all the trenches comprise, as illustrated in FIG. 4, an electrically conductive central region, for example made of polysilicon, enveloped in an insulating envelope ENV playing the role of a dielectric of capacitor.
    Furthermore, in the example illustrated in FIG. 7 which is a sectional view on the line VII-VII in FIG. 6, the trenches are extended at their lower part by implanted regions of conductivity type N 50 or 51.
    In this example, the additional peripheral trench TR 130 is still rectangular in shape and the device DIS for detecting a thinning of the substrate by the rear face FR here comprises within the well CS1 a group of several first TRI 10 trenches all parallel and extending between the two large opposite edges TR1301 and TR1302 of the additional peripheral trench TR130.
    A first contact zone ZC1 is arranged in contact with the caisson CS1 and a second contact zone ZC2 is arranged in contact with the caisson CS1 on the other side of the group of first trench TR110.
    Furthermore, a third contact zone ZC3 is arranged in contact with the additional peripheral trench TR130.
    In this regard, the integrated circuit IC comprises a first supply rail RL1 intended to convey the supply voltage VDD and a second supply rail RL2 intended to be connected to ground GND.
    The contacts ZC1 are connected to the rails RL1 by vias (not shown here) and a metallization ML1.
    Likewise, the contacts ZC3 are connected to the rails RL2 by vias and another metallization ML3.
    Finally, the contacts ZC2 are connected by vias to another metallization ML2.
    And, as can be seen in FIG. 8, the detection means 4 comprise first polarization means 40 configured to apply, via the metallizations ML1 and ML2, a first potential difference between the two contact zones ZC1 and ZC2 as well as measuring means 41 configured to measure for example the current flowing between these two contact zones ZC1 and ZC2.
    Furthermore, second polarization means 43 are configured to apply, via the metallizations ML1 and ML3, a second potential difference (typically the difference VDDGND) between the central region of the additional peripheral trench TR130 and the semiconductor well CS1, this which makes it possible to produce decoupling capacitors between the supply voltage and ground.
    As can be seen in FIG. 9, it is possible to couple several boxes electrically in series (here only two boxes are shown) each equipped with at least a first trench TR11, TR21, so as to form a chain of electrically coupled boxes serial.
    In FIG. 9, the wells CS1 and CS2 are of the type of those illustrated in FIG. 2, that is to say wells of conductivity type P electrically isolated from the rest 3 of the substrate by the insulating region 1, TR1200, 2.
    As a variant, the caissons could also be N type caissons in a substrate P.
    In FIG. 9, the coupling means allowing the electrical coupling between two adjacent caissons CS1 and CS2 comprise metallization MTL and vias VI and V2 connecting the two contact zones ZC2 and ZC3.
    Of course, the caissons could be of the type comprising groups of several first trenches.
    The DIS device then includes detection means 4, for example of the type of those described above, configured to measure a physical quantity representative of the electrical resistance between the two contact zones ZC1, ZC4 respectively located on either side of the two first trenches TR11 and TR21 extending in the boxes arranged at the two ends of the box chain.
    As can be seen in FIG. 10, it is also possible to use this chain structure of boxes electrically coupled in series to produce within the integrated circuit IC a resistive circuit RES having a large resistive value while having a reduced bulk.
    This is particularly interesting for analog applications.
    The integrated circuit IC may include such a resistive circuit RES without necessarily comprising a device DIS for detecting a thinning of the substrate by the rear face.
    That said, if the integrated circuit includes both such a resistive circuit RES and a device DIS for detecting a thinning of the substrate by the rear face, the circuit RES and the device DIS can be placed at different locations of the integrated circuit.
    In FIG. 10, the wells CS1 and CS2 are, as in FIG. 9, of the type of those illustrated in FIG. 2, that is to say wells of conductivity type P electrically isolated from the rest 3 of the substrate by the insulating region 1, TR1200, 2.
    However, the wells could also be type N wells in a P substrate.
    The coupling means allowing the electrical coupling between the two adjacent wells CS1 and CS2 here comprise a metallization MTL and vias VI and V2 connecting the two contact zones ZC2 and ZC3.
    Thus the resistive circuit RES extends in particular in the box chain, here the two boxes CS1 and CS2, between the two contact zones ZC1 and ZC4 which are located on the boxes located at the two ends of the box chain CS1, CS2 on either side of the first two trenches TR11 and TR21 extending in these end boxes.
    Of course, the caissons could be of the type illustrated in FIGS. 6 and 7, that is to say comprising groups of several first trenches.
    Such an integrated circuit IC can be incorporated into any object, in particular a smart card CP, as illustrated very diagrammatically in FIG. 11.
    权利要求:
    Claims (19)
    [1" id="c-fr-0001]
    1. Method for detecting a thinning of the semiconductor substrate of an integrated circuit from its rear face, the substrate including a set of at least one semiconductor well (CS1, CS2) electrically isolated from the rest (3) of the substrate and comprising a group of at least a first trench (TR11) extending in said at least one box between two locations on its periphery and from the front face (FV) of the substrate to a location located at a distance from the bottom of said at least a box (CS1), said at least one first trench (TR11) being electrically isolated from the box, the method comprising a measurement of a physical quantity representative of the electrical resistance of the box between two contact zones (ZC1, ZC2) respectively located on either side of said group of at least a first trench (TR11).
    [2" id="c-fr-0002]
    2. Integrated circuit, comprising:
    - a semiconductor substrate (SB) having a rear face (FR) and a front face (FV) and including a set of at least one semiconductor well (CS1, CS2) electrically isolated from the rest (3) of the substrate, and
    a device (DIS) for detecting a thinning of the substrate by its rear face, said device (DIS) comprising o a group of at least a first trench (TR11) extending in said at least one box between two places from its periphery and from said front face to a location located at a distance from the bottom of said at least one box, said at least one first trench (TR11) being electrically isolated from the box, and o detection means (4) configured for measuring a physical quantity representative of the electrical resistance of the box between two contact zones (ZC1, ZC2) respectively located on either side of said group of at least one first trench.
    [3" id="c-fr-0003]
    3. Integrated circuit according to claim 2, in which the detection means comprise polarization means (40) configured to apply a potential difference between said two contact zones (ZC1, ZC2; ZC1, ZC4)) and means for measurement (41) configured to measure the current flowing between said two contact zones.
    [4" id="c-fr-0004]
    4. Integrated circuit, including
    - a semiconductor substrate (SB) having a rear face (FR) and a front face (FV) and including a set of several semiconductor wells (CS1, CS2) electrically isolated from the rest (3) of the substrate,
    - A group of at least a first trench (TR11, TR21) extending in each box between two locations on its periphery and from said front face to a location located at a distance from the bottom of said box, said at least one first trench (TR11, TR21) being electrically isolated from said box,
    - coupling means (MTL, VI, V2) configured to couple two adjacent boxes electrically in series so as to form a chain of boxes electrically coupled in series, the coupling means being arranged between the two groups of at least a first trench extending respectively into said two adjacent caissons, and
    - two contact zones (ZC1, ZC4) respectively located on either side of the two groups of at least a first trench respectively extending in the two boxes respectively located at the two ends of said chain, so as to form a resistive circuit (RES) extending between said two contact zones (ZC1, ZC4).
    [5" id="c-fr-0005]
    5. Integrated circuit according to claim 2, 3 or 4, wherein said substrate and said at least one box are of conductivity type P, and said at least one box is electrically isolated from the substrate by an insulation region comprising a trench. insulating device (1) extending in the substrate from the front face and surrounding said at least one well (CS1), a semiconductor layer (2) of type N conductivity buried in the substrate under said at least one well, and a intermediate peripheral insulating zone (TR1200, 50) surrounding said at least one box and configured to ensure continuity of electrical insulation between said buried semiconductor layer (2) and the insulating peripheral trench (1), and said at least one first trench ( TR11) extends at least between two places in the insulating peripheral trench.
    [6" id="c-fr-0006]
    6. Integrated circuit according to claim 5, in which the isolation region comprises an additional peripheral trench (TR12) having at least one insulating envelope, extending from said front face through said insulating peripheral trench and having a lower part ( TR1200) extending under this insulating peripheral trench up to contact with said buried semiconductor layer.
    [7" id="c-fr-0007]
    7. The integrated circuit according to claim 6, in which the isolation region comprises an additional peripheral trench (TR12) having at least one insulating envelope, extending from said front face through said insulating peripheral trench and having a lower part ( TR1200) extending under this insulating peripheral trench (1) at a distance from the buried semiconductor layer (2), and an implanted zone (50) of conductivity type N located between said lower part (TR1200) and said buried semiconductor layer ( 2).
    [8" id="c-fr-0008]
    8. Integrated circuit according to claim 6 or 7, wherein said at least one first trench (TR11) extends between two locations of the additional peripheral trench.
    [9" id="c-fr-0009]
    9. Integrated circuit according to claim 6, 7 or 8, wherein said additional peripheral trench (TR12) is completely insulating.
    [10" id="c-fr-0010]
    10. Integrated circuit according to one of claims 2 to 9, wherein said at least one first trench (TR11) is completely insulating.
    [11" id="c-fr-0011]
    11. Integrated circuit according to one of claims 2 to 10, wherein said group comprises several first trenches (TRI 10).
    [12" id="c-fr-0012]
    12. Integrated circuit according to claim 7, 8 or 9, in which said additional peripheral trench (TR130) and said at least one first trench (TRI 10) each comprise an electrically conductive central region (RC) enveloped in an insulating envelope (ENV ).
    [13" id="c-fr-0013]
    13. An integrated circuit according to claim 12, wherein said group comprises several first parallel trenches (TRI 10) connecting two opposite edges (TR1301, TR1302) of said additional peripheral trench (TR130).
    [14" id="c-fr-0014]
    14. Integrated circuit according to claim 2 or 3 taken in combination with claim 12 or 13, in which the detection means (4) comprise first polarization means (40) configured to apply a first potential difference between said two zones contact (ZC1, ZC2) and measuring means (41) configured to measure the current flowing between said two contact areas, and the integrated circuit comprises second bias means (43) configured to apply a second potential difference between the central region of said additional peripheral trench (TR130) and said at least one semiconductor well (CS1).
    [15" id="c-fr-0015]
    15. Integrated circuit according to one of claims 2 to 14, comprising a memory device (DM) comprising a memory plane (PM) having non-volatile memory cells (CEL) and selection transistors (TSL) with grids buried, said at least one first trench (4) having a depth (PR) substantially equal to that of said buried grids.
    [16" id="c-fr-0016]
    16. Integrated circuit according to any one of claims 2, 3 and 5 to 15, wherein said assembly comprises several semiconductor wells (CS1, CS2).
    [17" id="c-fr-0017]
    17. The integrated circuit according to claim 16 taken in combination with claim 2 or 3, further comprising coupling means (MTL, VI, V2) configured to electrically couple two adjacent boxes in series so as to form a chain of boxes electrically coupled in series, the coupling means being arranged between the two groups of at least a first trench extending respectively into said two boxes
    5 adjacent, and the two contact zones (ZC1, ZC4) are respectively located on either side of the two groups of at least one first trench extending respectively into the two boxes respectively located at the two ends of said chain, the detection means (4) being configured to measure a
    10 physical quantity representative of the electrical resistance of the box chain between said two contact zones (ZC1, ZC4).
    [18" id="c-fr-0018]
    18. Object containing an integrated circuit (IC) according to one of claims 2 to 17.
    [19" id="c-fr-0019]
    19. Object according to claim 18 forming a card to
    15 chip (CP).
    1/6
    类似技术:
    公开号 | 公开日 | 专利标题
    FR3063385A1|2018-08-31|INTEGRATED CIRCUIT WITH REAR-SIDE SLURRY DETECTION AND DECOUPLING CAPACITORS
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    同族专利:
    公开号 | 公开日
    CN108511418A|2018-09-07|
    CN208045490U|2018-11-02|
    US20190027448A1|2019-01-24|
    US10109601B2|2018-10-23|
    US20200411454A1|2020-12-31|
    FR3063385B1|2019-04-26|
    CN108511418B|2021-11-09|
    US10804223B2|2020-10-13|
    US20180247901A1|2018-08-30|
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    FR2946775A1|2009-06-15|2010-12-17|St Microelectronics Rousset|DEVICE FOR DETECTING SUBSTRATE SLIP DETECTION OF INTEGRATED CIRCUIT CHIP|
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    FR2976721B1|2011-06-17|2013-06-21|St Microelectronics Rousset|DEVICE FOR DETECTING ATTACK IN AN INTEGRATED CIRCUIT CHIP|
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    FR3063385B1|2017-02-28|2019-04-26|Stmicroelectronics Sas|INTEGRATED CIRCUIT WITH REAR-SIDE SLURRY DETECTION AND DECOUPLING CAPACITORS|US11076419B2|2016-03-14|2021-07-27|Lg Electronics Inc.|Method for transmitting uplink data in wireless communication system and apparatus therefor|
    FR3057393A1|2016-10-11|2018-04-13|StmicroelectronicsSas|INTEGRATED CIRCUIT WITH DECOUPLING CAPACITOR IN A TYPE TRIPLE CAISSON STRUCTURE|
    FR3063385B1|2017-02-28|2019-04-26|StmicroelectronicsSas|INTEGRATED CIRCUIT WITH REAR-SIDE SLURRY DETECTION AND DECOUPLING CAPACITORS|
    FR3069954B1|2017-08-01|2020-02-07|StmicroelectronicsSas|METHOD FOR DETECTING A THINNING OF THE SUBSTRATE OF AN INTEGRATED CIRCUIT THROUGH ITS REAR SIDE, AND ASSOCIATED INTEGRATED CIRCUIT|
    FR3070535A1|2017-08-28|2019-03-01|StmicroelectronicsSas|INTEGRATED CIRCUIT WITH VERTICAL STRUCTURE CAPACITIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME|
    FR3070534A1|2017-08-28|2019-03-01|StmicroelectronicsSas|PROCESS FOR PRODUCING CAPACITIVE ELEMENTS IN TRENCHES|
    FR3072211B1|2017-10-11|2021-12-10|St Microelectronics Rousset|METHOD OF DETECTION OF AN INJECTION OF FAULTS AND THINNING OF THE SUBSTRATE IN AN INTEGRATED CIRCUIT, AND ASSOCIATED INTEGRATED CIRCUIT|
    FR3076660B1|2018-01-09|2020-02-07|StmicroelectronicsSas|INTEGRATED CAPACITIVE FILLING CELL DEVICE AND MANUFACTURING METHOD THEREOF|
    FR3087027A1|2018-10-08|2020-04-10|StmicroelectronicsSas|CAPACITIVE ELEMENT OF ELECTRONIC CHIP|
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    法律状态:
    2018-01-22| PLFP| Fee payment|Year of fee payment: 2 |
    2018-08-31| PLSC| Publication of the preliminary search report|Effective date: 20180831 |
    2020-01-22| PLFP| Fee payment|Year of fee payment: 4 |
    2021-01-20| PLFP| Fee payment|Year of fee payment: 5 |
    2022-01-19| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1751595|2017-02-28|
    FR1751595A|FR3063385B1|2017-02-28|2017-02-28|INTEGRATED CIRCUIT WITH REAR-SIDE SLURRY DETECTION AND DECOUPLING CAPACITORS|FR1751595A| FR3063385B1|2017-02-28|2017-02-28|INTEGRATED CIRCUIT WITH REAR-SIDE SLURRY DETECTION AND DECOUPLING CAPACITORS|
    CN201710779125.2A| CN108511418B|2017-02-28|2017-08-31|Integrated circuit with thinning detection via backside and decoupling capacitor|
    CN201721107313.2U| CN208045490U|2017-02-28|2017-08-31|Integrated circuit|
    US15/698,882| US10109601B2|2017-02-28|2017-09-08|Integrated circuit with detection of thinning via the back face and decoupling capacitors|
    US16/139,370| US10804223B2|2017-02-28|2018-09-24|Integrated circuit with detection of thinning via the back face and decoupling capacitors|
    US17/017,910| US20200411454A1|2017-02-28|2020-09-11|Integrated circuit with detection of thinning via the back face and decoupling capacitors|
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