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    • 专利摘要:
    The invention relates to a three-phase switching module including three identical switching cells, each comprising a first switch (M) and a second switch (M) electrically in series, comprising a substrate of which: a first level receives, on conductive zones ( 92), rear faces of integrated circuits forming said switches and; at least one second level comprises conductive zones (101) interconnecting vias between the first and second levels, the conductive zones of the different levels respecting a symmetry of revolution of order 3.
    公开号:FR3061626A1
    申请号:FR1663513
    申请日:2016-12-29
    公开日:2018-07-06
    发明作者:Guillaume LEFEVRE
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    @ Holder (s): COMMISSIONER FOR ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.
    O Extension request (s):
    ® Agent (s): CABINET BEAUMONT.
    FR 3 061 626 - A1 ® THREE-PHASE SWITCHING MODULE.
    (57) The invention relates to a three-phase switching module including three identical switching cells, each comprising a first switch (M) and a second switch (M) electrically in series, comprising a substrate of which: a first level receives, on conductive areas (92), rear faces of integrated circuits forming said switches and; at least a second level comprises conductive zones (101) for interconnecting vias between the first and second levels, the conductive zones of the different levels respecting order 3 symmetry of revolution.

    B15574 - DD17530 MR
    THREE-PHASE SWITCHING MODULE
    Field
    This description relates generally to electronic energy conversion systems and more particularly, the production of a three-phase current inverter. This description relates more precisely to the architecture of a static power converter intended for inverter type applications (CC-CA).
    Presentation of the prior art
    A two-stage three-phase AC alternating direct current AC static converter (inverter) is generally based on two sets of three (or three sets of two) electronic switches, typically MOS power transistors (MOSFET) associated with diodes.
    A distinction is made between voltage inverters in which the transistors are directly in series two by two and each transistor is equipped with an antiparallel diode, and current inverters in which each transistor is in series with a diode to constitute a bidirectional switch in voltage and unidirectional current. The present description relates more particularly to current inverters.
    In power applications, the transistors and the diodes are generally produced individually under the
    B15574 - DD17530MR form of discrete components or bare chips. Each switch with controlled switching (transistor) or spontaneous switching (diode) is produced in the form of an individual chip based on semiconductor materials and the various chips are then mounted on a substrate (printed circuit or Printed Circuit Board
    - PCB, direct solder copper or Direct Bond Copper - Metallic DBC, insulated metal substrate or Insulated Metal Substrate
    - IMS, etc.) then electrically connected to perform the three-phase current inverter function.
    There is a need to improve three-phase current inverters and in particular their spatial architecture.
    summary
    One embodiment overcomes all or part of the drawbacks of three-phase current inverters.
    One embodiment provides a solution for homogenizing the operating constraints between the various switches of a three-phase current inverter.
    A particularly suitable embodiment offers a solution to the realization of a current inverter.
    Thus, one embodiment provides a three-phase switching module including three identical switching cells, each comprising a first switch and a second switch electrically in series, comprising a substrate of which:
    a first level receives, on conductive areas, rear faces of integrated circuits forming said switches and;
    at least a second level comprises conductive areas for interconnecting vias between the first and second levels, the conductive areas of the different levels respecting order 3 symmetry of revolution.
    According to one embodiment, the first level comprises:
    B15574 - DD17530MR three first conductive zones for receiving a rear conduction terminal from at least one first switch of each cell; and three second conductive zones for receiving wires for connection to a conduction terminal before said first switch.
    According to one embodiment, the second level comprises:
    first three conductive areas respectively plumb with the first switches; and at least one second conductive zone directly above the second switches.
    According to one embodiment, the first level further comprises:
    a third central conductive area for receiving a rear conduction terminal of the second switches of the three cells; and three fourth conductive zones for receiving wires for connection to a rear conduction terminal of said second switches.
    According to one embodiment, the second level further comprises three third conductive zones, each connected by vias to a second and to a fourth conductive zone of the first level.
    According to one embodiment, said third conductive zone of the first level has a Y shape, each branch receiving one of said second switches.
    According to one embodiment, the module is in a triangular shape.
    According to one embodiment, a third level of the substrate, between the first and second levels, comprises:
    first conductive zones perpendicular to each first switch; and a second conductive zone extending under the three second switches.
    B15574 - DD17530MR
    According to one embodiment, a fourth level of the substrate between the second and third levels, comprises:
    first conductive zones perpendicular to each first switch; and a second conductive zone extending under the three second switches.
    According to one embodiment, the first conductive zones of the first level receive respective conduction terminals of the second switches, the first level further comprising three third conductive zones for receiving wires for connection to respective front conduction terminals of the second switches.
    According to one embodiment, the second conductive areas of the first level are each connected, via vias, to one of said first conductive areas of the second level.
    According to one embodiment, said first conductive areas of the second level describe a hexagonal ring.
    According to one embodiment, the module is inscribed in a hexagonal shape.
    According to one embodiment, said switches are transistors.
    According to one embodiment, the substrate is an insulated metallic substrate, multilevel, preferably on ceramic.
    According to one embodiment, the substrate is a multilevel printed circuit.
    One embodiment provides a three-phase current inverter, comprising two modules.
    According to one embodiment, the cells of the two modules are electrically connected in pairs, the interconnection nodes defining three phase terminals.
    Brief description of the drawings
    These and other features and advantages will be discussed in detail in the following description of modes of
    B15574 - DD17530MR particular realization made without limitation in relation to the attached figures among which:
    Figure 1 is a schematic representation and in the form of blocks of a three-phase inverter of the type to which the described embodiments apply;
    FIG. 2 represents an electrical diagram of a three-phase current inverter;
    Figure 3 is a schematic representation of a conventional architecture of a switching module of a three-phase current inverter;
    FIG. 4A represents, very schematically, an embodiment of a first three-phase current inverter module in a first level of an insulated metal substrate;
    FIG. 4B very schematically represents an embodiment of a second level of the metal substrate isolated from the first module of FIG. 4A;
    FIG. 4C very schematically represents the two superimposed levels, that is to say the module completed;
    FIG. 5A shows, very schematically, an embodiment of a second three-phase current inverter module in a first level of an insulated metal substrate;
    FIG. 5B very schematically represents an embodiment of a second level of the metal substrate isolated from the second module of FIG. 5A;
    FIG. 5C very schematically represents the two superimposed levels, that is to say the module completed;
    FIG. 6A very schematically shows another embodiment of a first level of insulated metal substrate in which a three-phase current inverter module is produced;
    FIG. 6B represents, very schematically, another embodiment of a second level of insulated metal substrate in which a three-phase current inverter module according to FIG. 6A is produced;
    B15574 - DD17530MR FIG. 7 represents the electrical diagram of a module in which each cell is formed of two MOS transistors in series;
    FIG. 8A represents, very schematically, an embodiment of a first level of a quadri-level insulated metal substrate in which a three-phase current inverter module is produced;
    FIG. 8B very schematically represents an embodiment of a third level of the quadri-level insulated metal substrate in which a three-phase current inverter module according to FIG. 8A is produced;
    FIG. 8C very schematically represents an embodiment of a fourth level of the quadri-level insulated metal substrate in which a three-phase current inverter module according to FIG. 8A is produced; and FIG. 8D very schematically represents an embodiment of a second level of the quadri-level insulated metal substrate in which a three-phase current inverter module according to FIG. 8A is produced.
    detailed description
    For the sake of clarity, only the elements which are useful for understanding the described embodiments have been shown and will be detailed. In particular, the control of a power converter based on the three-phase inverters described has not been detailed, the embodiments described being compatible with the usual industrial manufacturing processes and control circuits. In addition, the constitution and construction of the circuits upstream and downstream of the three-phase inverters described have not been detailed either, the embodiments described being compatible with the usual applications of such three-phase inverters. It should be noted that, in the figures, the structural and / or functional elements common to the various embodiments may have the same references and may have identical structural, dimensional and material properties. Unless otherwise specified
    B15574 - DD17530MR on the contrary, the expressions approximately, substantially and of the order of mean to the nearest 10%, preferably to 5%, or to 10 ° near, preferably to 5 °.
    Figure 1 is a schematic representation and in the form of blocks of a three-phase inverter of the type to which the embodiments described apply.
    The function of a three-phase inverter 1 is to convert a direct current Idc flowing between two input terminals 11 and 12 into a three-phase alternating current lac on output terminals 15, 16, 17 and 19. Terminals 15, 16 and 17 represent the terminals of the different phases and terminal 19 represents the optional neutral terminal.
    Figure 2 shows an electrical diagram of a three-phase current inverter.
    The inverter 1 comprises two switching modules 2h and 21 of similar internal structures. Each module 2 comprises three switching cells, cyclically involving two of the three switches, respectively 3h-l, 3h-2, 3h-3 and 31-1, 31-2, 31-3 identical and each consisting of a transistor MOS (N-channel) respectively Mh-1, Mh-2, Mh-3, Ml-1, Ml-2, Ml-3 in series with a diode, respectively Dh-1, Dh-2, Dh-3, Dl -1, Dl-2, Dl-3. The drains of the transistors Mh-1, Mh-2 and Mh-3 are interconnected at the terminal 11 of application of a first potential of the current source Idc. The sources of the transistors Mh-1, Mh-2 and Mh-3 are respectively connected to the anodes of the diodes Dh-1, Dh-2 and Dh-3, whose cathodes are connected respectively to the terminals 15, 16 and 17 of the three phases of alternating voltage. The drains of the transistors Ml-1, Ml-2, Ml-3 are respectively connected to terminals 15, 16 and 17. The sources of the transistors Ml-1, Ml-2 and Ml-3 are respectively connected to the anodes of the diodes Dl- 1, Dl-2 and Dl-3, the cathodes of which are interconnected at terminal 12 for applying a second potential from the current source Idc.
    The grids of the transistors Mh-1, Mh-2, Mh-3, Ml-1,
    Ml-2, Ml-3 are individually connected to a circuit
    B15574 - DD17530MR command 4 (CTRL) responsible for organizing the switching of the different cells to generate a three-phase alternating current lake. In a current inverter, the current flows successively in each of the switching cells (for example 3h-l / 3h-2, 3h-l / 3h-3, 3h-2 / 3h-3) of one first module together with each of the switching cells (for example 31-1 / 31-2, 31-1 / 31-3, 31-2 / 31-3) of the other module. We thus obtain the 9 combinations allowing to generate the three-phase alternating current with the appropriate phase shifts. The control of such a current inverter is usual.
    In the present description, the high or low module of the three-phase current inverter to which the element identified by the numerical reference is identified is identified by the letter "h" or "1" completing the same digital reference. Furthermore, the references are completed with “-1”, “-2” or “-3” to identify the switching branch (representing the phase of the alternating voltage) to which the element identified by the numerical reference belongs. These additional references may be omitted when a distinction need not be made for the purposes of the presentation.
    Figure 3 is a schematic representation of a usual architecture of a switching module of a three-phase current inverter.
    In the power applications targeted by the present description, the transistors and diodes are produced in the form of vertical components made of semiconductor materials mounted on a plane (metallic substrate or printed circuit) 51.
    In the example of FIG. 3, a high module 2h is considered, the diodes and transistors of which are inverted with respect to FIG. 2. It is therefore the anodes of the diodes Dh-1, Dh-2, Dh-3 which are interconnected at terminal 11. The three diodes Dh-1, Dh-2 and Dh-3 are produced individually on P-type substrates and the cathodes are produced by N-type regions in these substrates. Anode electrodes, generally made
    B15574 - DD17530MR in the form of a metallization on the rear face of the chips forming the diodes Dh-1, Dh-2, Dh-3, are attached to a conductive area 53 (typically a metallic conductive plane) of a substrate 51, in this example an insulated metal substrate. A metallization defining the terminal 11 is connected to the plane 53 by one or more wires 55. The transistors Mh-1, Mh-2 and Mh-3 are also produced individually in the form of chips 56-1, 56-2 and 56-3 . The drain electrode of each transistor, generally produced in the form of a metallization on the rear face of the chip, is attached to a conductive area 58-1,
    58-2 and 58-3 respectively of the insulated metal substrate 51. The cathode electrodes corresponding to metallizations front face 52-1, 52-2 and 52-3 of the chips forming the diodes Dh-1, Dh-2 and Dh- 3 are respectively electrically connected to the zones
    58-1, 58-2 and 58-3 by one or more wires 57-1, 57-2, 57-3. The source electrode of each transistor Mh-1, Mh-2, Mh-3 corresponds to a metal contact on the front face, respectively
    59-1,59-2,59-3, connected by one or more wires 60-1,60-2,
    60-3 at a contact of the insulated metal substrate, defining a terminal, respectively 15, 16, 17. The gates of the transistors Mh-1, Mh-2 and Mh-3 are taken up on the front face of the chips by contacts 62-1 , 62-2 and 62-3, individually connected by one or more wires 63-1, 63-2, 63-3, to respective contacts of the insulated metal substrate 51, defining terminals 64-1, 64-2, 64 -3 intended to be connected to control circuit 4 (Figure 2).
    An architecture as illustrated in FIG. 3 in which the chips are juxtaposed generates operating constraints, thermal and electrical, different according to the operating phases, which affects its reliability.
    Furthermore, there is an imbalance between the different conduction meshes, which also affects operation.
    The embodiments which will be described start from a new analysis based on the architecture or the layout.
    B15574 - DD17530MR of the different switching cells on a substrate with metallic zones, for example an insulated metallic substrate.
    In particular, provision is made to make the electrical and thermal stresses undergone by the various chips of the converter, identical whatever the phase. Thus, the aging is homogenized, which increases the reliability of the current inverters.
    More particularly, provision is made to use a multilayer insulated metallic substrate (at least two) and to arrange the constituent elements of each switching cell with, in the plane, a symmetry of revolution of order 3 relative to the center of the structure . More precisely, the three cells of a module are arranged in branches of a star or Y structure on a first level (called arbitrarily higher) of the insulated metal substrate in which metallized zones are defined and interconnections are made in at least a second level of the insulated metal substrate in which metallized zones are also defined, the connection between metallized zones from one level to another being effected by conductive vias.
    To simplify the representation of the figures and the description which follows, only the metallized zones of the different levels of the isolated metal substrates have been represented. These areas are of course carried by an insulating support and the different levels are separated by insulating levels.
    FIG. 4A very schematically represents an embodiment of a first 2h module of a three-phase current inverter in a first level of an insulated metal substrate.
    FIG. 4B very schematically represents an embodiment of a second level of the metal substrate isolated from the first module of FIG. 4A.
    FIG. 4C very schematically represents the two superimposed levels, that is to say the module 2 hours finished.
    B15574 - DD17530MR
    In the example of FIGS. 4A to 4C, the diodes of the cells are arranged at the start of the branches of the Y (towards the center) and the transistors are arranged towards the free ends of the branches of the Y. Furthermore, an electrical diagram is assumed in which the respective positions of the diodes and transistors are reversed with respect to the electrical diagram of FIG. 2. In other words, in the high module 2h, the anodes of the diodes are interconnected at terminal 11 and the sources of the transistors are connected to respective terminals 15, 16 and 17.
    As before, the diodes and transistors are produced individually in the form of discrete chips of vertical components made of semiconductor materials.
    In the first level (FIG. 4A), first conductive zones 71h-l, 71h-2, 71h-3 are produced of approximately rectangular shape for receiving rear conduction terminals (for example the drains) of the transistors Mh-1, Mh -2, Mh-3 (corresponding to metallizations on the rear face of the chips forming these transistors) and rear conduction terminals (for example the cathodes) of each chip 56h-l, 56h-2, 56h-3, forming the respective diodes Dh-1, Dh-2, Dh-3.
    Second conducting zones 72h-l, 72h-2, 72h-3 are produced at the respective external ends of the first zones 71. The zones 72 are intended to each receive one or more wires 57h-l, 57h-2, 57h-3 of connection of the front conduction terminals (for example the sources) of the transistors Mh-1, Mh-2 and Mh-3 (corresponding to metallizations on the front face of the chips forming these transistors). The zones 72 are connected, via vias 73h-l, 73h-2, 73h-3 to the first zones 81h-l, 81h-2, 81h-3 (FIG. 4B) of the second level of the isolated metallic substrate.
    Third conductive areas 74h-1, 74h-2, 74h-3 are produced in the central region near the chips of the respective diodes Dh-1, Dh-2, Dh-3. These zones 74 are each intended to receive one or more wires 60h-l, 60h-2, 60h-3 for connecting the front conduction terminals (for example the anodes) of the diodes Dh-1, Dh-2, Dh-3. These anodes are intended for
    B15574 - DD17530MR be interconnected (at terminal 11). For this, the zones 74 are connected, via vias 75h-1, 75h-2, 75h-3 to a second central zone 82-h (FIG. 4B) of the second level of the insulated metal substrate.
    The gate contacts 62h-l, 62h-2 and 62-3 of the transistors Mh-1, Mh-2, Mh-3 are accessible for connection, for example by wires to control circuits which, as will be seen by following, are preferably placed nearby.
    In the second level (FIG. 4B), the realization of the zones 81h and 82h depends on the respective positions of the zones of the first level. However, as for the conductive areas of the first level, the conductive areas of the second level respect, in the plane, a symmetry of revolution of order 3 relative to the center of the structure. In other words, the entire structure has substantially a symmetry of revolution of 120 °.
    In the example of FIG. 4B, the second level describes a hexagon. The zones 81 correspond to three identical metallized zones 81h-l, 81h-2, 81h-3, each having the shape of a portion of a hexagonal annular strip, each zone being separated from its two neighboring zones. The central zone 82h has a shape, here approximately in a star, plumb with the three zones 74h-l, 74h-2 and 74h-3 of the first level. Zones 81h-1, 81h-2, 81h-3 define terminals 15, 16 and 17 respectively. Zone 82h defines terminal 11.
    This arrangement makes it possible to integrate, in the example shown, on the upper face side, capacitive elements C for decoupling electrically connecting the terminals 15, 16, and 17 two by two. To do this, zones 77 and 79 are designed in the first level, vertically at the ends of the zones 81, intended to receive the respective electrodes of the capacitors C and connected by vias 76 to the underlying zones 81.
    As a variant, the capacitive elements C are welded directly to the second face of the insulated metal substrate
    B15574 - DD17530MR (in this case zones 77 and 79 are not necessary). The embodiment illustrated in FIGS. 4A to 4C however makes it possible to keep the rear face for a radiator.
    Preferably, provision is made in the second level, plumb with the diodes and the transistors, for cutouts of the conductive zones likely to be present in order to prevent the chips from being plumb with conductive zones of the second level.
    FIG. 5A represents, very schematically, an embodiment of a second module 21 of three-phase current inverter in a first level of an insulated metal substrate.
    FIG. 5B represents, very schematically, an embodiment of a second level of the metal substrate isolated from the second module of FIG. 5A.
    FIG. 5C very schematically represents the two superposed levels, that is to say the module 21 finished.
    Here, the cell diodes are arranged towards the ends of the branches of the Y and the transistors are arranged towards the center. Here again, an electrical diagram is assumed in which the respective positions of the diodes and transistors are reversed relative to the electrical diagram of FIG. 2. In other words, in the low module 21, the sources of the transistors are interconnected at the terminal 12 and the anodes of the diodes are connected to the respective terminals 15, 16 and 17. However, any other arrangement could be envisaged provided that the symmetry of revolution of approximately 120 ° is respected. Indeed, the respective positions of the transistors and diodes in each of the modules can be reversed.
    In the first level (FIG. 5A), first conductive zones 711-1, 711-2, 711-3 are produced with an approximately rectangle shape for receiving the cathode electrodes on the rear face of each chip 561-1, 561-2, 561-3 forming the diodes Dl-1, Dl-2, Dl-3 and the drain contacts of the respective transistors Ml-1, Ml-2, Ml-3.
    Second conductive zones 741-1, 741-2, 741-3 are produced at the respective external ends of the first
    B15574 - DD17530MR zones 71 near the chips 561-1, 561-2, 561-3 of the respective diodes Dl-1, Dl-2, Dl-3. These zones 74 are intended to each receive one or more wires 601-1, 601-2, 601-3 for connecting the anodes of the diodes Dl-1, Dl-2, Dl-3. These anodes are intended to be individually connected to the respective terminals 15, 16 and 17. For this, the zones 74 are connected, by vias 751-1, 751-2, 751-3 to first zones 811-1, 811- 2, 811-3 (Figure 5B) of the second level of insulated metal substrate.
    Third conductive zones 721-1, 721-2, 721-3 are produced in the central region near the chips of the respective transistors Ml-1, Ml-2, Ml-3. The zones 72 are intended to each receive one or more wires 571-1, 571-2, 571-3 for connecting the sources of the transistors. These sources are intended to be interconnected (at terminal 12). For this, the zones 72 are connected, via vias 731-1, 731-2, 731-3 to a second central zone 821 (FIG. 5B) of the second level of insulated metal substrate.
    The gate contacts 621-1, 621-2 and 621-3 of the transistors Ml-1, Ml-2, Ml-3 are accessible for connection, for example by wires to control circuits, preferably placed nearby.
    In the second level (FIG. 5B), the realization of the zones 81 and 82 depends on the respective positions of the zones of the first level. However, here again, as for the conductive zones of the first level, the conductive zones of the second level respect, in the plane, a symmetry of revolution of order 3 relative to the center of the structure.
    In the example of FIG. 5B, the zones 81 correspond to three zones
    811-1, 811-2, 811-3 identical metallized, each having the shape of a portion of a hexagonal annular band, each zone being separated from its two neighboring zones. The central zone 821 has a shape, here approximately also hexagonal, plumb with the three zones 721-1, 721-2 and
    721-3 of the first level. Zones 811-1, 811-2, 811-3 define
    B15574 - DD17530MR respectively terminals 15, 16 and 17. Zone 821 defines terminal 12.
    As for the 2h module, it is possible to integrate, on the upper face side, capacitive elements C for decoupling electrically connecting the terminals 15, 16, and 17 in pairs. For this, in the first level, vertical to the ends of the areas 81, areas 77 and 79 respectively are designed to receive the respective electrodes of the capacitors C and connected by vias 76 to the underlying areas 81. Again, the capacitive elements C can alternatively be soldered directly to the second face of the insulated metal substrate.
    Still as for the 2h module, provision is preferably made in the second level, directly above the diodes and the transistors, to cut out the conductive areas which may be present in order to prevent the chips from being in line with the areas conductors of the second level.
    FIGS. 6A and 6B schematically represent another embodiment of a module of a three-phase current inverter on a bi-level insulated metal substrate.
    This embodiment illustrates, not only a different arrangement of the components and the conductive zones but also an embodiment according to which all the switches are transistors. Consequently, the arrangement of the conductive zones of FIGS. 6A and 6B can be used indifferently to produce a high module 2h or a low module 21 of a three-phase current inverter.
    FIG. 7 represents the electrical diagram of a module in which each cell is formed of two MOS transistors in series.
    In this example, the transistors M-1, M-2, M-3 of each cell are interconnected by their respective sources to the source of the other transistor M-4, M-5, M-6 of the cell. The drains of the transistors M-l, M-2 and M-3 are interconnected at terminal 11 or 12 depending on whether the module is mounted as a high module or
    B15574 - DD17530MR low, and the drains of the transistors M-4, M-5 and M-6 define the respective terminals 15, 16 and 17.
    In the first level (FIG. 6A), first conductive zones 92-4, 92-5, 92-6 are produced with an approximately rectangular (or square) shape for receiving the contacts (drains) of the rear face of the transistors M-4, M-5, M-6. We assume here rear face drain transistors. A third conductive zone 91 is also produced approximately in star or Y shape, each branch (preferably its free end) receiving the rear drain contact of one of the transistors M-1, M-2, M-3. The centers of the chips of the transistors of the same cell are approximately on the same fictitious radius of a circle connecting the centers of the chips of the transistors M1, M-2, M-3 between them and the centers of the chips of the transistors M-4, M -5, M-6 between them. The first zones 92 are connected, by a set of vias 99 arranged under the chip which they receive to respective first zones 101-1, 101-2, 101-3, of the second level (FIG. 6B) each describing a portion of 'an approximately triangular ring shape. The third zone 91 is connected, by sets of vias 94, arranged under the chips of the transistors M-1, M-2, M-3, to a second central zone 102, approximately in star or in Y, of the second level.
    Second 96-4, 96-5, 96-6 and fourth 95-1, 95-2, 95-3 conductive zones are made in the first level, near the first and second zones respectively, and are intended to receive each one or more wires 94-4, 94-5, 94-6, respectively 93-1, 93-2, 93-3, for connecting the source contacts of the transistors M-4, M-5, M-6, respectively Ml, M-2, M-3. Zones 95 and 96 are connected, two by two, via vias 97, to three approximately rectangular zones 103-1, 103-2 and 103-3 of the second level. The interconnection of zones 95 and 96 by the second level preserves easy access to grids 62-1, 62-2, 62-3, 62-4, 62-5, 62-6. As a variant, provision may be made for a specific cutting of zones 95 and 96 and an adapted layout of the connection tracks (not shown) of the
    B15574 - DD17530MR grids on the control circuits 4-1, 4-2, 4-3 to interconnect the sources in the first level.
    As for the previous embodiments, there are integrated, on the upper face side, capacitive elements C electrically connecting the terminals 15, 16, and 17 in pairs. For this, one realizes in the first level, vertically the ends of the zones 101, zones, respectively 77 and 79 intended to receive the respective electrodes of the capacitors C and connected by vias 76 to the underlying zones 101. In the example of FIGS. 6A and 6B, the zones 77 and 79 are arranged parallel to the branches of the triangle defined by the zones 81 and not perpendicularly (radially with respect to the center of the structure) as in the preceding figures. Both are possible.
    An advantage of the embodiment of FIGS. 6A and 6B is that it reduces the capacitive coupling between the power conductors (drain, source for MOS transistors or transmitter, collector for bipolar or IGBT transistors) and the gate control circuits. controlled switches.
    Another advantage is that the surface of the central zone is increased, which makes it possible to decrease the inductance of the mesh.
    Another advantage is that it contributes to reducing the common mode emissions linked to the capacitive couplings between the potentials of terminals 11 and 12 and the earth in the case of an isolated metal substrate directly cooled by a radiator.
    FIGS. 8A, 8B, 8C and 8D illustrate, schematically, an embodiment of a module of a three-phase current inverter on an insulated metal substrate with four levels. Figure 8A shows the first (upper) level. Figure 8D shows the second (lower) level. FIGS. 8B and 8C represent two intermediate levels, arbitrarily called third and fourth levels.
    The first level of Figure 8A is similar to that of Figure 6A. The only difference is that the zones, here designated 111-1, 111-2, 111-3, carrying the transistors M-4, M-5
    B15574 - DD17530MR and M-6 extend in the direction of zone 77 of the neighboring cell so as to receive a first electrode of capacitances C, the other electrode being received by zone 111. In the example of FIG. 8A, the zones 77 are radial at the center of the structure.
    The second level (FIG. 8D) corresponding to the rear face has in the center three second independent conductive zones 112-1, 112-2, 112-3 directly above the transistors M-1, M-2, M-3. These zones are connected via vias 94 to zone 91 under the transistors M-1, M-2, M-3 (by crossing the intermediate level or levels). This second level also comprises three first zones 113-1, 113-2, 113-3 respectively connecting, like the zones 101 in FIG. 6B, the rear face of each transistor chip M-4, M-5, M- 6 to zone 77 of the neighboring cell (via vias 76). Note that the zones 112 can be omitted. Their role is mainly to promote thermal connection with a radiator provided on the rear of the entire structure.
    The third level (FIG. 8B) located just below the first level has a central conductive area 114 identical to the area 91 of the first level through which the vias 94 pass. This level also includes three conductive areas
    116-1, 116-2, 116-3 of the type of the zones 103 of FIG. 6B, connecting via the vias 97, the conductive zones 95 and 96 of the first level of each cell. The role of these zones 116 is to constitute a protection plan under the control circuits 4-1, 4-2, 4-3. In addition, conductive zones 117-1, 117-2,
    117-3 are provided directly above the transistors M-4, M-5, M-6 through which the vias 99 pass. A role of the third level is to create conductive protection planes under the control circuits 4.
    The fourth level (FIG. 8C), located between the third and second levels, comprises a central zone 118, for example of hexagonal shape, through which the vias 94 pass. This level also comprises zones 119-1, 119-2 , 119-3
    B15574 - DD17530MR through which the vias 99 pass. The role of the zone 118 is to reduce the parasitic inductance linked to the connections. As a variant, the zone 118 may have a triangular shape integrating the regions of the vias 94.
    An arrangement of the chips as illustrated in the embodiments above has the advantage of homogenizing the electrical and thermal behavior of the various meshes of current circulation. Indeed, the geometric symmetry between the different cells means that the three possible meshes 3h-l / 3h-2, 3h-2 / 3h-3 and 3h-l / 3h-3 for the high module 2h and the three possible meshes 31 -1 / 31-2, 31-2 / 31-3 and 31-1 / 31-3 for the low module 21 have the same electrical behavior. In particular, the impedances of the different switching meshes used are identical and the overvoltage levels seen by the different switches are identical. In addition, their thermal behavior is also homogenized thanks to this geometric symmetry.
    Other shapes may be provided for the metal areas of the isolated metal substrate for receiving the switching cells, provided that in each level of the isolated metal substrate a symmetry of revolution of order 3, that is to say a offset of approximately 120 degrees, preferably exactly 120 degrees, from one cell to another around the center of the plane in which the module is inscribed.
    An advantage of the embodiments which have been described is that it is now possible to produce a three-phase current inverter in which the electrical and thermal behavior of the different switching meshes is identical.
    Various embodiments and variants have been described. Certain embodiments and variants may be combined and other variants and modifications will appear to those skilled in the art. In particular, the metal areas of the substrate used are of course separated from each other so as to be electrically isolated. In addition, these areas can be connected by conductive tracks or wires to other
    B15574 - DD17530MR metal regions of the substrate, in particular for connecting the inverter to upstream and downstream circuits. Furthermore, although more specific reference has been made to the use of an insulated metal substrate, the substrate on which the components are mounted may be any other suitable substrate, for example a printed circuit, a copper substrate to direct welding, etc. In addition, each switch can in fact be formed of several switches in parallel. The choice of dimensions and number of chips to be assembled in parallel to make each switch of an inverter depends on the application and, among other things, on the desired operating power.
    In addition, although the embodiments have been described in relation to examples applied to cells consisting of a MOS transistor in series with a diode or of two MOS transistors in series, they transpose to other cell structures or three-phase switching system realizing a bidirectional voltage switch and unidirectional or bidirectional current switch, in which similar problems arise.
    It will be noted that the two modules of the same three-phase current inverter are not necessarily paired on the same insulated metal substrate (in the same plane) but can be superimposed with the interposition of an insulator, by connecting the terminals 15, 16 and 17 through vias.
    Finally, the practical implementation of the embodiments and variants which have been described is within the reach of those skilled in the art from the functional indications given above.
    B15574 - DD17530MR
    权利要求:
    Claims (18)
    [1" id="c-fr-0001]
    1. Three-phase switching module (2h; 21) including three switching cells (3h-l, 3h-2, 3h-3; 31-1, 31-2,
    31-3) identical, each comprising a first switch (M) and a second switch (D; M) electrically in series, comprising a substrate of which:
    a first level receives, on conductive areas (71; 91, 92; 91, 111), rear faces of integrated circuits forming said switches and;
    at least a second level comprises conductive zones (81; 101; 113) for interconnecting vias between the first and second levels, the conductive zones of the different levels respecting order 3 symmetry of revolution.
    [2" id="c-fr-0002]
    2. Module according to claim 1, in which the first level comprises:
    first three conductive zones (71h-l, 71h-2,
    71h-3; 711-1, 711-2, 711-3; 92-4, 92-5, 92-5; 111-1, 111-2,
    111-3) receiving a rear conduction terminal of at least one first switch of each cell; and three second conductive zones (72h-l, 72h-2,
    72h-3; 741-1, 741-2, 741-3; 96-4, 96-5, 96-6; 96-4, 96-5, 96-6) for receiving connection wires to a conduction terminal before said first switch.
    [3" id="c-fr-0003]
    3. Module according to claim 1, in which the second level comprises:
    first three conductive zones (81h-l, 81h-2,
    81h-3; 811-1, 811-2, 811-3; 101-1, 101-2, 111-3; 111-1, 111-2, 111-3) respectively plumb with the first switches; and at least a second conductive zone (82h; 821;
    102; 112-1, 112-2, 112-3) directly above the second switches.
    [4" id="c-fr-0004]
    4. Module according to claim 2 or 3, wherein the first level further comprises:
    B15574 - DD17530MR a third central conductive zone (91) for receiving a rear conduction terminal of the second switches of the three cells; and three fourth conductive zones (95-1, 95-2, 95-3) for receiving wires for connection to a rear conduction terminal of said second switches.
    [5" id="c-fr-0005]
    5. Module according to claim 4, wherein the second level further comprises three third conductive areas (103-1, 103-2, 103-3), each connected by vias (97) to a second (96-4, 96-5, 96-6) and a fourth (95-1, 95-2, 95-3) conductive zone of the first level.
    [6" id="c-fr-0006]
    6. Module according to claim 4 or 5, wherein said third conductive area (91) of the first level in a Y shape, each branch receiving one of said second switches.
    [7" id="c-fr-0007]
    7. Module according to any one of claims 4 to 6, registering in a triangular shape.
    [8" id="c-fr-0008]
    8. Module according to any one of claims 4 to 7, of which a third level of the substrate, between the first and second levels, comprises:
    first conductive zones (117-1, 117-2, 117-3) plumb with each first switch; and a second conductive zone (114) extending under the three second switches.
    [9" id="c-fr-0009]
    9. Module according to claim 8, of which a fourth level of the substrate between the second and third levels, comprises:
    first conductive zones (119-1, 119-2, 119-3) plumb with each first switch; and a second conductive zone (118) extending under the three second switches.
    [10" id="c-fr-0010]
    10. Module according to claim 2 or 3, wherein the first conductive zones (71h-l, 71h-2, 71h-3; 711-1, 711-2, 711-3) of the first level receive respective conduction terminals second switches, the first level
    B15574 - DD17530MR further comprising three third conductive zones (74h-l, 74h-2, 74h-3; 731-1, 731-2, 731-3) for receiving connection wires to respective front conduction terminals of the second switches.
    [11" id="c-fr-0011]
    11. Module according to claim 10, in its attachment to claim 3, wherein the second conductive zones (72h-l, 72h-2, 72h-3; 741-1, 741-2, 741-3) of the first level are each connected, via vias (73h-l, 73h-2, 73h-3; 731-1, 731-2, 731-3), to one of said first conductive zones (81h-l, 81h-2, 81h- 3; 811-1, 811-2, 811-3) of the second level.
    [12" id="c-fr-0012]
    12. Module according to claim 10 or 11, wherein said first conductive zones (81h-l, 81h-2, 81h-3; 811-1, 811-2, 811-3) of the second level describe a hexagonal ring.
    [13" id="c-fr-0013]
    13. Module according to any one of claims 10 to 12, registering in a hexagonal shape.
    [14" id="c-fr-0014]
    14. Module according to any one of claims 1 to 13, wherein said switches are MOS transistors.
    [15" id="c-fr-0015]
    15. Module according to any one of claims 1 to 14, wherein the substrate is an insulated metallic substrate, multilevel, preferably on ceramic.
    [16" id="c-fr-0016]
    16. Module according to any one of claims 1 to 15, in which the substrate is a multilevel printed circuit.
    [17" id="c-fr-0017]
    17. Three-phase current inverter, comprising two modules (2h, 21) according to any one of claims 1 to 16.
    [18" id="c-fr-0018]
    18. The inverter as claimed in claim 17, in which the cells (3h-1, 3h-2, 3h-3; 31-1, 31-2, 31-3) of the two modules (2h, 21) are electrically connected two to two, the interconnection nodes defining three phase terminals (15, 16, 17).
    B 15574 DD17530
    1/7
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    法律状态:
    2018-01-02| PLFP| Fee payment|Year of fee payment: 2 |
    2018-07-06| PLSC| Publication of the preliminary search report|Effective date: 20180706 |
    2019-12-31| PLFP| Fee payment|Year of fee payment: 4 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 5 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
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    FR1663513A|FR3061626B1|2016-12-29|2016-12-29|THREE PHASE SWITCHING MODULE|
    FR1663513|2016-12-29|FR1663513A| FR3061626B1|2016-12-29|2016-12-29|THREE PHASE SWITCHING MODULE|
    EP17210537.1A| EP3344024A1|2016-12-29|2017-12-22|Three-phase switching module|
    US15/855,288| US10873267B2|2016-12-29|2017-12-27|Three-phase switching unit|
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