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    • 专利摘要:
    The invention relates to a method for manufacturing a vertical transistor (1), comprising the steps of: -providing a substrate (100) surmounted by a stack (10) of first, second and third layers, respectively in first, second and third semiconductor materials, said second semiconductor material being different from the first and third materials; horizontally growing first, second and third dielectric layers (310, 320, 330) by oxidation, from the first, second and third layers (11, 12, 13) of semiconductor materials respectively, with a second dielectric layer ( 320) whose thickness is different from the thickness of said first and third dielectric layers; -drawing the second dielectric layer (320) so as to form a recess (25) self-aligned vertically with the second semiconductor layer (12), positioned vertically between first and second blocks formed vis-à-vis the first and third semiconductor layers (11, 13); forming a gate stack (42) in said self-aligned recess (25).
    公开号:FR3060850A1
    申请号:FR1662566
    申请日:2016-12-15
    公开日:2018-06-22
    发明作者:Shay REBOH；Emmanuel Augendre；Remi COQUAND
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Holder (s): COMMISSIONER OF ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.
    Extension request (s)
    Agent (s): INNOVATION COMPETENCE GROUP.
    METHOD FOR MANUFACTURING A VERTICAL CHANNEL NANOCOUCHER TRANSISTOR
    FR 3 060 850 - A1
    Ms The invention relates to a method for manufacturing a vertical transistor (1), comprising the steps of:
    -providing a substrate (100) surmounted by a stack (10) of first, second and third layers, respectively of first, second and third semiconductor materials, said second semiconductor material being different from the first and third materials;
    -grow horizontally first, second and third dielectric layers (310, 320, 330) by oxidation, from the first, second and third layers (11, 12, 13) of semiconductor materials respectively, with a second dielectric layer ( 320) whose thickness is different from the thickness of said first and third dielectric layers;
    -removing the second dielectric layer (320) so as to form a recess (25) vertically self-aligned with the second semiconductor layer (12), positioned vertically between first and second blocks arranged opposite the first and third semiconductor layers (11, 13);
    -forming a grid stack (42) in said self-aligned recess (25).

    METHOD FOR MANUFACTURING A VERTICAL CHANNEL NANOCOUCHER TRANSISTOR
    The invention relates to vertical channel transistors, and in particular the methods of manufacturing such transistors.
    The increase in the performance of integrated circuits due to the miniaturization of field effect transistors is faced with a technological and scientific obstacle. One of the issues is the increase in static and dynamic power in integrated circuits. In order to reduce this power consumption, new architectures and new materials which will make it possible to obtain a low operating voltage are today intensively studied.
    In particular, for technological nodes below 50 nm, the electrostatic control of the channel by the gate becomes a predominant operating parameter for the operation of the transistor. To improve this electrostatic control, various technologies of multi-gate transistors are the subject of developments, in particular the transistors with nanowires with a covering gate. However, the very reduced gate length available for transistors with a covering grid makes them difficult to manufacture and limits the ability to obtain strong currents in the on state.
    In order to allow longer gate lengths while maintaining a planar integration density similar to that of the coating gate transistors, structures of vertical channel nanolayer transistors have been proposed. The difficulty for such transistors stems from their very great structural difference with planar field effect transistors. These structural differences imply very different manufacturing processes. The sources of manufacturing dispersions are thus very different, the rules for dimensional control of the vertical transistor are also very different during its configuration, which makes the industrialization of such transistors still problematic. In particular, the usual manufacturing methods for such transistors carry out sequentially deposition, lithography and etching steps of the different layers of the vertical transistor. Each deposit is usually carried out by epitaxy and followed by shaping, so as to form a source / channel / drain stack. One of the difficulties is to ensure good vertical alignment of the grid relative to the channel.
    The invention aims to solve one or more of these drawbacks. The invention thus relates to a method for manufacturing a vertical transistor, comprising the steps of:
    ICG011127 FR Text Depot
    -providing a substrate surmounted by a vertical stack of first, second and third layers, respectively in first, second and third semiconductor materials, said second semiconductor material being different from the first and third semiconductor materials;
    -grow horizontally the first, second and third dielectric layers by oxidation, from the first, second and third layers of semiconductor materials respectively, the oxidation inducing a second dielectric layer whose thickness along said horizontal direction is different from l thickness of said first and third dielectric layers, or a second dielectric layer whose composition is different from the composition of said first and third dielectric layers;
    -removing the second dielectric layer so as to form a vertically self-aligned recess with the second semiconductor layer, said recess being positioned vertically between first and second blocks arranged opposite the first and third semiconductor layers respectively;
    -forming a grid stack in said self-aligned recess.
    The invention also relates to the following variants. Those skilled in the art will understand that each of the characteristics of the following variants can be combined independently with the above characteristics, without however constituting an intermediate generalization.
    According to a variant, said oxidation induces a second dielectric layer, the thickness of which is different from that of the first and third dielectric layers, said method comprising a step of etching the first to third dielectric layers with the same thickness, so as to remove the second dielectric layer and to retain at least a portion of the first and third dielectric layers, either so as to remove the first and third dielectric layers and to retain at least a portion of the second dielectric layer.
    According to a variant, said oxidation induces a second dielectric layer whose thickness is strictly less than that of the first and third dielectric layers, in which said recess is formed between said first and third dielectric layers forming said first and second blocks respectively.
    According to another variant, said oxidation induces a second dielectric layer whose thickness is strictly greater than that of the first and third dielectric layers, the method comprising a step of forming a fourth and fifth dielectric layer against the first and third
    ICG011127 EN Depot Text semiconductor layers after the first and third dielectric layers have been removed, said recess is formed between said fourth and fifth dielectric layers forming said first and second blocks respectively.
    According to yet another variant, said first to third semiconductor layers are silicon-based layers, said second semiconductor layer having a phosphorus concentration different from that of the first and third semiconductor layers.
    According to yet another variant, said first to third semiconductor layers are silicon-based layers, said second semiconductor layer having a Germanium concentration different from that of the first and third semiconductor layers.
    According to a variant, said oxidation induces a second dielectric layer whose composition is different from the composition of said first and third dielectric layers, said method comprising either a step of selective etching of the second dielectric layer with respect to the first and third dielectric layers so removing the second dielectric layer and keeping at least part of the first and third dielectric layers, that is a step of selective etching of the first and third dielectric layers with respect to the second dielectric layer so as to remove the first and third dielectric layers and to keep at least part of the second dielectric layer.
    According to yet another variant, the method comprises a selective etching of the first and third dielectric layers with respect to the second dielectric layer so as to remove the first and third dielectric layers and to preserve at least part of the second dielectric layer, the method comprising a step of forming the sixth and seventh dielectric layers against the first and third semiconductor layers after the removal of the first and third dielectric layers, said recess is formed between said sixth and seventh dielectric layers forming said first and second blocks respectively.
    According to another variant, the formation of the grid stack comprises the formation of a layer of grid insulation in said recess and the formation of a conductive material on said layer of grid insulation.
    According to another variant, said recess formed surrounds said second layer of semiconductor material.
    According to yet another variant, said first semiconductor layer has an upper part and a lower part, said lower part extending laterally beyond said upper part for the substrate supplied,
    ICG011127 EN Depot Text said growth by oxidation inducing vertical growth of a lateral part of the first dielectric layer from said lower part of the first semiconductor layer, said grid stack being formed on said lateral part of the first dielectric layer.
    According to a variant, said supply step is preceded by the steps of: forming a hard mask pattern on the third layer of semiconductor material;
    anisotropic etching of the first to third layers of semiconductor materials according to the pattern of the hard mask.
    According to yet another variant, the method further comprises steps of: forming a seventh dielectric layer against a side face of said grid stack, the seventh dielectric layer being made of a material different from the hard mask;
    formation of an eighth dielectric layer against a lateral face of the seventh dielectric layer, the eighth dielectric layer being in a material different from the hard mask and from the seventh dielectric layer; -forming an engraving pattern by photolithography;
    - successive selective etchings according to said etching pattern of the hard mask, of the eighth dielectric layer and of a part of the seventh dielectric layer, so as to form respective recesses;
    -deposition of conductive material in said recesses so as to form drain, source and gate contacts respectively.
    According to a variant, said step of horizontal growth of the first, second and third dielectric layers is implemented by thermal oxidation.
    According to another variant, said step of horizontal growth of the first, second and third dielectric layers is carried out by wet oxidation.
    Other characteristics and advantages of the invention will emerge clearly from the description given below, by way of indication and in no way limitative, with reference to the appended drawings, in which:
    FIG. 1 is a schematic perspective view of a stack of nanowires for a vertical channel field effect transistor, illustrating dimensional parameters of the channel;
    FIGS. 2 to 13 are cross-section views during different stages of a method for manufacturing vertical channel field effect transistors according to an example of a first embodiment of the invention;
    ICG011127 FR Text Depot
    FIGS. 14 to 16 are cross-sectional views at different locations after etching steps for the formation of transistor contacts;
    FIGS. 17 to 32 are views in cross section during different stages of a process for manufacturing vertical channel field effect transistors according to an example of a second embodiment of the invention;
    FIGS. 33 to 40 are views in cross section during different stages of a process for manufacturing vertical channel field effect transistors according to an example of a third embodiment of the invention;
    FIG. 41 illustrates a step of an alternative manufacturing method which can be implemented according to the first embodiment of the invention.
    FIG. 1 is a schematic perspective view of a stack 10 of layers of nanowires or nanolayers, which can serve as the basis for a vertical channel field effect transistor 1. A layer 11 of a first semiconductor material, a layer 12 of a second semiconductor material and a layer 13 of a third semiconductor material are superimposed in the stack 10, formed on a substrate 100. Although not illustrated, the substrate 100 and the stack 10 can be separated through a box and / or deep insulation trenches. Layers 11 to 13 are layers of nanowires or nanolayers. The layer 13 is covered with one (or more) layer of dielectric 21 forming a hard mask. The layers 11 and 13 are intended to form first and second conduction electrodes of the transistor, the layer 12 being intended to form the channel zone of this transistor. The semiconductor material of layer 12 is different from that of layers 11 and 13.
    The layers 11 and 13 are advantageously made from the same semiconductor material. The layers 11 and 13 typically include doping in order to optimize their electrical properties. By way of example, the substrate 100 is of the solid substrate type, for example made of silicon. The layers 11 and 13 are for example initially made of a silicon-germanium alloy (for example doped SiGe, such as B-doped SiGe), and the layer 12 can be made of unintentionally doped silicon (or having for example a doping intended to modify the threshold voltage of the transistor to be formed). The dielectric layer 21 is for example made of SiN. Other materials can of course be envisaged in the context of the invention. We can for example consider making layers 11 and 13 in Silicon (or in doped Silicon, for example in P-doped Silicon) and in making layer 12 in Silicon alloy ICG011127 FR Depot Texte
    Germanium. It is also possible to envisage making layers 11 to 13 in III-V type semiconductor materials (for example InGaAs, InP, etc.).
    FIG. 1 illustrates the dimensional parameters of the channel zone of the transistor 1 produced with a stack 10. Considering that the layer 12 corresponds to the final shape of the channel zone of the transistor, such a transistor has a gate length or length of channel gl (dimension along the normal to substrate 100) corresponding to the thickness of layer 12, a width of channel cw corresponding to the length (dimension along the longitudinal direction) of layer 12, and a thickness of channel and corresponding to the width (dimension in the transverse direction) of the layer 12. In order to have both a current in the large on state and good electrostatic control of the channel, the value cw is advantageously at least equal to 2 times the value and.
    Figures 2 to 13 are cross-sectional views of an example of transistor 1 at different stages of an example of a first embodiment of a manufacturing method according to the invention. The manufacturing process illustrated here aims to manufacture two vertical transistors whose sources are electrically connected but can be applied to the manufacture of other configurations of transistors. The first embodiment aims to grow a thermal oxide laterally on a channel layer, with a smaller thickness compared to a thermal oxide at the source and the drain, in order to be able to benefit from a self-alignment of the grid. .
    In FIG. 2, a substrate 100 is provided as detailed above. The substrate 100 is here topped with a layer of semiconductor material 101, used as a box. A box can also be formed by ion implantation in the substrate 100. The layer of semiconductor material 101 is here surmounted by a stack 10 of layers of semiconductor materials. The invention also applies in the absence of such a layer 101 between the substrate 100 and the stack 10.
    The stack 10 here comprises a layer 11 of SiliconGermanium alloy (overlying the layer 101), a layer 12 of Silicon formed on the layer 11, and a layer 13 of Silicon-Germanium alloy formed on the layer 12. The stack 10 is here formed for the production of a pMOS type transistor 1.
    The layer 11 here comprises the superposition of a layer 111 formed on the layer 101, and of a layer 112 formed on the layer 111. The layers 111 and 112 for example advantageously have different Germanium concentrations. Layer 111 can also advantageously have
    ICG011127 EN Depot Text a different composition (for example a doping difference) of the layer 112, so that the etching stop on the layer 111 can be effective during subsequent process steps. The layer 112 here has the same composition as the layer 13. The invention also applies of course to a layer 11 having a homogeneous composition. The silicon-germanium alloy can have a doping with boron having for example a concentration of between 5 × 10 19 cm ′ 3 and 5 × 10 20 cm ′ 3 (or beyond if technology allows), preferably equal to 2 × 10 20 cm ' 3 .
    The stacking of layers 11 to 13 can be obtained beforehand by epitaxy growth stages, in a manner known per se. The materials of layers 11 to 13 are selected according to the electrical performance desired for transistor 1, and so as to be able to grow laterally a thermal oxide from layer 12 with a growth rate different from that of thermal oxides formed laterally layers 11 and 13. The type of doping of layer 101 is advantageously opposite to that of layer 111, in order to limit leaks towards the substrate 100.
    The stack of layers 11 to 13 here has a thickness typically between 10 and 300 nanometers. The layer 12 has a thickness typically between 5 and 100 nm (for example 30 nm), the definition of its thickness facilitating the definition of the electrical length of the channel. The layers 11 and 13 can have identical or different thicknesses, for example in order to adjust their electrical resistances. The layers 11 and 13 typically have respective thicknesses between 5 and 100 nm (for example 30 nm). In order to reduce the resistance at the source or the drain of a transistor 1, their thickness is advantageously at most equal to 25 nm. A reduced value of the respective thicknesses of layers 11 to 13 also facilitates the subsequent formation of spacers.
    The layer 13 is covered by a dielectric layer 21. The dielectric layer 21 is typically made of SiN, S1O2 or a combination of these two materials. Layer 21 forms a hard mask for stacking. The layer 21 here has a width of between 10 and 100 nanometers (for example 40 nm), corresponding to the width and which we want to define for the stack.
    In FIG. 3, the dielectric layer 21 was used to carry out an anisotropic etching (for example a reactive ion etching known as RIE) of the layers 13, 12 and 112, so that they have substantially the same length and the same width, corresponding to the pattern of the dielectric layer 21. The etching is interrupted when the layer 111 is exposed on the side of the stacks 10.
    ICG011127 FR Text Depot
    In FIG. 4, a step of growth of dielectric material by thermal oxidation has been implemented on the sides of the layers 112, 12 and 13. A vertical growth of dielectric material is also carried out on the layer
    111. The dielectrics are formed by thermal oxidation of layers 111, 112, 12 and 13 respectively (for example a rapid thermal oxidation known as RTO in English, with a process temperature typically between 750 and 1150 ° C.). At the end of this step, a dielectric layer 330 is formed laterally on the layer 13, a dielectric layer 320 is formed laterally on the layer 12, and a dielectric layer 310 is formed laterally on the layer 112 and vertically on layer 111.
    The growth rates of dielectric oxides from a layer of Silicon-Germanium alloy increase with the Germanium content of this layer. The document 'Needs of low thermal budget Processing in SiGe Technology', by U. Kônig and Alias, provides in particular results of growth rates of oxide layers by rapid thermal oxidation processes, as a function of the temperature of oxidation and the proportion of germanium in a silicon-Germanium alloy. The growth rate of the oxide for each of the layers may also depend on the pressure, temperature and oxygen content during the oxidation (and possibly other experimental factors).
    With a layer 12 having a zero proportion of germanium or a much lower proportion than that of layers 13, 111 and 112, the growth rate of the dielectric by thermal oxidation on the side of layer 12 is much lower than the growth rate of dielectric by thermal oxidation on the side of layers 13 and 112. Thus, at the end of the thermal oxidation step, the dielectric layer 320 has a thickness (dimension in the horizontal direction) less than that of the layer of dielectric 330 or of that of the dielectric layer 310. One can for example consider forming a dielectric layer 320 having a thickness between 1 and 5 nm, for a dielectric layer 330 having a thickness of 10 nm. The difference in growth rate is observable at the interface between layer 12 with layers 112 and 13 respectively. Consequently, layer 320 is vertically self-aligned with the interfaces of layer 12 with layers 13 and 112 respectively. With a layer 13 and a layer 112 of the same compositions, the lateral growth rate of the dielectric layers 310 and 330 is identical.
    In FIG. 5, an isotropic etching of the layers 310, 320 and
    330:
    ICG011127 FR Text Depot
    -on a thickness sufficiently reduced to retain part of the dielectric layers 310 and 330;
    -on a thickness sufficient to remove the dielectric layer 320, and form a recess 25 between the dielectric layers 310 and 330.
    Spacers 331 have thus been formed on either side of the layer 13, and a spacer layer 311 on either side of the layer 112. A vertical recess 312 is formed in the spacer 311. The etching is for example a dry etching of the atomic layer etching type (ALE) or of a reactive ion etching type (RIE). An isotropic etching process can be used for which the etching speed is substantially identical for the different dielectric layers 310, 320 and 330.
    In FIG. 6, a conformal deposition of a dielectric layer has been produced.
    420. In this example, the dielectric material of layer 420 is of the Hk type, that is to say that it has a dielectric constant at least equal to 6. The dielectric material of layer 420 is for example HfO2 (for example a deposit by atomic layer). The dielectric material of layer 420 is for example deposited over a thickness of at most 3 nm. Advantageously, an interface layer (not shown here) can be deposited beforehand, for example in Si O2 having a thickness of between 1 and 2 nm. The layer 420 then covers in particular the lateral faces of the layer 12. The layer 420 is intended to form the gate insulator.
    In FIG. 7, a conductive layer 421 is deposited properly. In this example, the gate material, corresponding to layer 421, is TiN. The material of layer 421 is for example deposited over a thickness of at least 3 nm. The layer 421 is notably deposited on the layer 420. The layer 421, forming the grid material, is for example deposited with a deposition process by atomic layer. The step illustrated in FIG. 7 can be preceded by an anisotropic etching of the layer 420, so as to keep the layer 420 only on either side of the layer 12.
    In FIG. 8, an etching of the layer 421 and of the layer 420 is carried out, advantageously so as to uncover the upper face of the dielectric layer 21 and so as to uncover the spacer layers 311 on both sides. other of the stacks 10. The layer 421 is kept on either side of the layers 12 and 13. A grid 42 is then provided on either side of the layer 12 (on the lateral faces of the layer 12). Each grid 42 is extended by a contact portion 411, vertically upwards, on either side of the layer
    11. Each grid 42 is electrically isolated from the layer 111 by means of the spacer layers 311. For a layer 421 of sufficient thickness, an isotropic etching can be carried out. If the layer 421 is made of TiN, we can by
    ICG011127 FR Depot Text example carry out an isotropic etching of the RIE or ICP type. The grid 42 thus obtained thus has vertical self-alignment with respect to the layer 12.
    The process can be implemented so as to form a gate 42 encircling the entire layer 12. It is thus possible to form a transistor 1 with a covering gate, the entire channel area then being surrounded by the gate 42. The gate 42 can thus be polarized at the same potential all around the layer 12 forming the channel zone.
    In FIG. 9, a conformal deposition of a dielectric layer 51 has been carried out. The layer 51 is typically a layer of SiBCN. Each stack 10 is thus encapsulated in the layer 51. Likewise, the gate 42 and the contact portion 411 of a transistor 1 are encapsulated in the layer 51. The layer 51 has for example a thickness of 10 nm. SiN can for example be deposited by an atomic layer deposition process.
    In FIG. 10, an anisotropic etching step of the layer 51 has been carried out, to a thickness sufficient to reveal the upper face of the layer 21 and of the spacer layer 311, while retaining this layer 51 on both sides. other of the stacks 10.
    In FIG. 11, a thick dielectric layer 52 was deposited, then a chemical mechanical polishing until the upper face of the layer 21 was discovered. The layer 52 is for example made of S1O2 or TEOS . S1O2 can for example be deposited by an atomic layer deposition process. The layer 52 thus forms a separation between the different stacks 10.
    In FIG. 12, a selective wet etching (for example with sulfuric acid) has been carried out of the upper part of the contact portions 411. This etching is advantageously carried out to withdraw the contact portions 411 up to the level of the layer 13, and advantageously before reaching the level of layer 12. Recesses 412 are thus formed above the grids 42.
    In FIG. 13, the recesses 412 have been filled with a dielectric material, preferably the same as that of the layer 51. As illustrated in FIG. 13, it is then possible to have a dielectric layer 51 extending above the grids 42 up to the stack 10, so as to form a protection for the grids 42 covered by this dielectric layer 51.
    Advantageously, the materials of layer 21, of layer 51 and of layer 52 are different and can be etched in a dissociated manner by selective etchings. Thus, one can define the geometry of the accesses to layer 13 (to form a drain contact), the geometry of accesses to layer 12 (to form a gate contact), and the geometry of accesses to layer 111 (for
    ICG011127 FR Text Depot form a source contact) through successive stages of lithography and selective etching.
    Figures 14 to 16 are cross-sectional views of the transistors 1, in different planes, after having implemented the selective etchings.
    In the section illustrated in FIG. 14, part of the layer 21 has been removed to form a recess 22, until the upper face of the layer is discovered.
    13.
    In the section illustrated in FIG. 15, part of the layer 52 has been removed to form a recess 23, until the upper face of the layer 111 is discovered, between the stacks 10.
    In the section illustrated in FIG. 16, part of the layer 51 has been removed to form a recess 24, until the upper part of the contact portions 411 is uncovered.
    In subsequent stages, the same metallization can be carried out to fill the recesses 22 to 24, then carry out mechanical chemical polishing to obtain the shape of the drain, gate and source ports. Metallization is typically carried out with a material chosen from the group consisting of Cu, Co, W, Al, Ti.
    It is thus possible to form accesses in electrical contact with respective drains, accesses in electrical contact with respective grids, and accesses in electrical contact with the layer 111, and therefore in electrical contact with the source of two transistors 1.
    The source access is isolated from the gate access and the drain access by layer 51. The gate access is isolated from the drain access by layer 21, and isolated from the access of source through layer 52.
    The first embodiment has been detailed more specifically for the formation of pMOS transistors. For the formation of an nMOS transistor, it is possible, for example, to replace layers 11 and 13 with layers of silicon with N-type doping, for example doping with phosphorus. By using a layer 12 having an N-type doping at a concentration significantly lower than that of layers 11 and 13, the growth rate of dielectric by thermal oxidation is significantly lower on the side of layer 12, compared to that of the layers. 11 and 13. The other steps of the method, subsequent to the growth of the thermal oxide for the first embodiment, can be implemented in a similar manner for the formation of the nMOS transistors with this type of layers 11 to 13. A strong doping in Phosphorus of layers 11 and 13 makes it possible to reduce their resistance to access.
    ICG011127 FR Text Depot
    The document entitled 'Thermal oxidation of heavily Phosphorus-doped Silicon' by CPHo and Alias describes in particular different growth rates by thermal oxidation, according to the proportion of Phosphorus in a layer of Silicon, and according to the temperature of the growth process by thermal oxidation. One can for example consider forming an oxide layer with a thickness of 10 nm by a thermal oxidation process implemented at 800 ° C for a period of 10 minutes, for a layer of silicon doped with a concentration of 3.10 20 cm ' 3 of Phosphorus. Under the same temperature conditions, a duration of 60 minutes would be necessary to obtain the same thickness of oxide with a layer of silicon doped with a concentration of 1.10 15 cm 3 of phosphorus.
    Figures 17 to 32 are cross-sectional views of an example of transistor 1 at different stages of an example of a second embodiment of a manufacturing method according to the invention. The manufacturing process illustrated here aims to manufacture two vertical transistors whose sources are connected but can be applied to the manufacture of other configurations of transistors. The second embodiment aims to grow a thermal oxide laterally on a channel layer, with a greater thickness compared to a thermal oxide at the source and the drain, in order to be able to benefit from a self-alignment of the wire rack.
    In FIG. 17, a substrate 100 is provided. The substrate 100 is here topped with a layer of semiconductor material 101, used as a box. The layer of semiconductor material 101 is here surmounted by a stack 10 of layers of semiconductor materials. The invention also applies in the absence of such a layer 101 between the substrate 100 and the stack 10.
    The stack 10 here comprises a layer 11 of silicon (overlying the layer 101), a layer 12 of silicon-germanium alloy formed on the layer 11, and a layer 13 of silicon formed on the layer 12.
    The layer 11 here comprises the superposition of a layer 111 formed on the layer 101, and of a layer 112 formed on the layer 111. The layers 111 and 112 for example advantageously have different concentrations of doping material, for example in view reduce the access resistance to the source of transistor 1 to be formed. The layer 112 here has the same composition as the layer 13. The invention naturally applies to a layer 11 having a homogeneous composition. The silicon-Germanium alloy of layer 12 can have a doping with boron having for example a concentration of between 5 × 10 19 cm -3 and 5 × 10 20 cm -3 , preferably equal to 2 × 10 20 cm -3 .
    ICG011127 FR Text Depot
    The stacking of layers 11 to 13 can be obtained beforehand by epitaxy growth stages, in a manner known per se. The materials of layers 11 to 13 are selected according to the electrical performance desired for transistor 1, and so as to be able to grow laterally a thermal oxide from layer 12 with a growth rate different from that of thermal oxides formed laterally layers 11 and 13. The type of doping of layer 101 is advantageously opposite to that of layer 111, in order to limit leaks towards the substrate 100.
    The stack of layers 11 to 13 here has a thickness typically between 10 and 300 nanometers. The layer 12 has a thickness typically between 5 and 100 nm (for example 15 nm), the definition of its thickness facilitating the definition of the electrical length of the channel. The layers 11 and 13 can have identical or different thicknesses, for example in order to adjust their electrical resistances. The layers 11 and 13 typically have respective thicknesses between 3 and 100 nm (for example 20 nm). In order to reduce the contact resistance at the source or the drain of a transistor 1, their thickness is advantageously at most equal to 15 nm. A reduced value of the respective thicknesses of layers 11 to 13 also facilitates the subsequent formation of spacers.
    The layer 13 is covered by a dielectric layer 21. The dielectric layer 21 is typically made of SiN, S1O2 or a combination of these two materials. Layer 21 forms a hard mask for stacking. The layer 21 here has a width of between 10 and 100 nanometers (for example 40 nm), corresponding to the width and which we want to define for the stack.
    In FIG. 18, the dielectric layer 21 was used to produce an anisotropic etching of the layers 13, 12 and 112, so that they have substantially the same length and the same width, corresponding to the pattern of the dielectric layer. 21. An RIE type etching of the same type as that used to etch the stack of layers 11, 12 and 13 can be produced. The etching is interrupted when the layer 111 is discovered on the side of the stacks 10.
    In FIG. 19, a step of growth of dielectric material has been implemented by thermal oxidation on the sides of the layers 112, 12 and 13. A vertical growth of dielectric material is also carried out on the layer
    111. The dielectrics are formed by thermal oxidation of layers 111, 112, 12 and 13 respectively (for example rapid thermal oxidation, with a process temperature typically between 750 and 1150 ° C). At the end of this step, a dielectric layer 330 is formed laterally
    ICG011127 EN Text Depot on layer 13, a dielectric layer 320 is formed laterally on layer 12, and a dielectric layer 310 is formed laterally on layer 112 and vertically on layer 111.
    With a layer 12 having a much higher proportion of Germanium than that of layers 13, 111 and 112, the growth rate of the dielectric by thermal oxidation on the side of the layer 12 is much higher than the growth rate of dielectric by oxidation thermal on the side of layers 13 and 112. Thus, at the end of the thermal oxidation step, the dielectric layer 320 has a thickness (dimension in the horizontal direction) strictly greater than that of the dielectric layer 330 or to that of the dielectric layer 310. One can for example consider forming a dielectric layer 320 having a thickness of 10 nm, for a dielectric layer 330 having a thickness between 1 and 5 nm. The difference in growth rate is observable at the interface between layer 12 with layers 112 and 13 respectively. Consequently, layer 320 is vertically self-aligned with the interfaces of layer 12 with layers 13 and 112 respectively. With a layer 13 and a layer 112 of the same compositions, the lateral growth rate of the dielectric layers 310 and 330 is identical.
    In FIG. 20, an isotropic etching of the layers 310, 320 and
    330:
    -on a thickness sufficient to remove the dielectric layers 310 and
    330;
    on a sufficiently reduced thickness to preserve a part of the dielectric layer 320. Thus sacrificial spacers 322 have been formed on either side of the layer 12.
    An isotropic etching process can be used for which the etching speed is substantially identical for the different dielectric layers 310, 320 and 330.
    In FIG. 21, a conformal deposition of a dielectric layer has been carried out
    53. In this example, the dielectric material of the layer 53 is for example SiN. The dielectric material of the layer 53 is for example deposited over a thickness of between 5 and 10 nm. The layer 53 then covers in particular the lateral faces of the layers 112 and 13. The layer 53 is intended to form spacers for the layers 112 and 13.
    In FIG. 22, an anisotropic etching of the layer 53 has been carried out so as to uncover the upper face of the dielectric layer 21 and so as to uncover the upper face of the layer 111 on either side of the stacks 10. The layer 53 is kept on either side of the layers 112
    ICG011127 EN Text Depot and 13. Spacers 531 and 533 are provided on either side of layers 112 and 13 respectively. A fairly anisotropic type of RIE-ICP etching can be performed using the dielectric layer 21 as an etching mask. The spacers 531, 533 and the sacrificial spacers 322 are horizontally self-aligned with the dielectric layer 21 after this etching.
    In FIG. 23, a non-conformal deposition of a dielectric material was carried out to form a layer 54 on the layer 111, over a height corresponding substantially to that of the spacers 531. Such a deposition can for example be of the PVD type. The dielectric material of the layer 54 is advantageously identical to that of the layer 53. The layer 54 deposited on the stacks 10 has here been removed by a chemical mechanical polishing step.
    In FIG. 24, the sacrificial spacers 322 were removed by selective etching. There are then recesses 25 self-aligned vertically with the layer 12. The recesses 25 are of course also self-aligned with the layer 13 and the spacers 533 on the one hand, and the layer 112 and the layer 54 including the spacers 531 on the other hand. The etching of the sacrificial spacers 322 is for example a dry etching of the atomic layer etching type (ALE) or of a reactive ion etching type (RIE).
    In FIG. 25, a conformal deposition of a dielectric layer has been carried out
    420. In this example, the dielectric material of layer 420 is of the Hk type, that is to say that it has a dielectric constant at least equal to 6. The dielectric material of layer 420 is for example HfO2 (for example a deposit by atomic layer). The dielectric material of layer 420 is for example deposited over a thickness of at most 3 nm. Advantageously, an interface layer (not shown here) can be deposited beforehand, for example in Si O2 having a thickness of between 1 and 2 nm. The layer 420 then covers in particular the lateral faces of the layer 12, in the recesses 25. The layer 420 is intended to form the gate insulator. In the configuration illustrated in FIG. 25, an anisotropic etching was also carried out so as to remove the layer 420 from all the surfaces outside the recesses 25 (for example a plasma etching including Ar, BCb, or CI2 ).
    In FIG. 26, a conformal deposition of a conductive layer has been carried out.
    421. In this example, the grid material, corresponding to layer 421, is TiN. The material of layer 421 is for example deposited over a thickness of at least 3 nm. The layer 421 is notably deposited on the layer 420. The layer 421, forming the grid material, is for example deposited with a deposition process by atomic layer.
    In FIG. 27, an etching of the layer 421 has been carried out, so as to uncover the upper face of the dielectric layer 21 and so as to
    ICG011127 FR Text Depot discover the layer 54 on either side of the stacks 10. The layer 421 is kept on either side of the layers 12 and 13. A grid 42 is then provided on either side of the layer 12 (on the lateral faces of the layer 12). Each grid 42 is extended by a contact portion 411, vertically upwards, on either side of the layer 11. Each grid 42 is electrically isolated from the layer 111 by means of the dielectric layer
    54. For a layer 421 of sufficient thickness, an isotropic etching can be carried out. If the layer 421 is made of TiN, it is for example possible to produce an isotropic etching of the RIE or ICP type. The grid 42 thus obtained thus has vertical self-alignment with respect to the layer 12.
    The process can be implemented so as to form a gate 42 encircling the entire layer 12. It is thus possible to form a transistor 1 with a covering gate, the entire channel area then being surrounded by the gate 42. The gate 42 can thus be polarized at the same potential all around the layer 12 forming the channel zone.
    According to an optional variant illustrated in FIG. 41, at the end of the step illustrated with reference to FIG. 27, an upper part of the contact portion 411 can be removed, in order to facilitate the formation of a spacer extending above this contact portion 411.
    In FIG. 28, at the end of the step illustrated with reference to FIG. 27, a conformal deposition of a dielectric layer 55 was carried out. The layer 55 is for example a layer of SiBCN, for example in a material identical to that of layer 21. Each stack 10 is thus encapsulated in the layer
    55. Likewise, the gate 42 and the contact portion 411 of a transistor 1 are encapsulated in the layer 55. The layer 55 has for example a thickness of 10 nm and can for example be deposited by a deposition process by layer atomic.
    In FIG. 29, an anisotropic etching step of the layer 55 was carried out, over a thickness sufficient to reveal the upper face of the layer 21 and of the dielectric layer 54, while retaining this layer 55 on both sides. other stack 10.
    In FIG. 30, a thick dielectric layer 56 has been deposited, then a chemical mechanical polishing until the upper face of the layer 21 is discovered. The layer 56 is for example made of S1O2 or TEOS . S1O2 can for example be deposited by an atomic layer deposition process. The layer 56 thus forms a separation between the different stacks 10.
    In FIG. 31, a selective wet etching (for example with sulfuric acid) has been carried out of the upper part of the contact portions 411. This
    ICG011127 FR Depot Text etching is advantageously carried out to remove the contact portions 411 up to the level of layer 13, and advantageously before reaching the level of layer 12. Recesses 413 are thus formed above the grids 42.
    In FIG. 32, the recesses 413 have been filled with a dielectric material, preferably the same as that of the layer 55. As illustrated in FIG. 32, it is then possible to have a dielectric layer 55 extending above the grids 42 up to the stack 10, so as to form a protection for the grids 42 covered by this layer of dielectric 55.
    The subsequent steps for forming the respective accesses to the drain, the source and the gate of each transistor 1 will not be described further and may, for example, be implemented in a similar manner to the first embodiment.
    Figures 33 to 40 are cross-sectional views of an example of transistor 1 at different stages of an example of a third embodiment of a manufacturing method according to the invention. The manufacturing process illustrated here aims to manufacture two vertical transistors whose sources are connected but can be applied to the manufacture of other configurations of transistors. The third embodiment aims to grow a thermal oxide laterally on a channel layer, with a composition different from that of thermal oxides at the source and the drain. By a selective etching according to the materials of the different oxides, one can benefit from a self-alignment of the grid.
    In FIG. 33, a substrate 100 is provided. The substrate 100 is here topped with a layer of semiconductor material 101, used as a box. The layer of semiconductor material 101 is here surmounted by a stack 10 of layers of semiconductor materials. The invention also applies in the absence of such a layer 101 between the substrate 100 and the stack 10.
    The stack 10 here comprises a layer 11 of SiGe (overlying the layer 101), a layer 12 of Si formed on the layer 11, and a layer 13 of SiGe formed on the layer 12. The SiGe and the Si naturally result in lateral growths of thermal oxides of different natures. The document 'Selective GeOx-Scavenging from Interfacial Layer on Si1-xGex Channel for High Mobility Si / Si1-xGex CMOS Application', published by CH Lee and alias in 2016 Symposium on VLSI Technology Digest of Technical Papers, describes training parameters of interfacial layers on silicon alloy layers having different Germanium concentrations.
    ICG011127 FR Text Depot
    The layer 11 here comprises the superposition of a layer 111 formed on the layer 101, and of a layer 112 formed on the layer 111. The layers 111 and 112 for example advantageously have different concentrations of doping material, for example in view reduce the access resistance to the source of transistor 1 to be formed. The layer 112 here has the same composition as the layer 13. The invention obviously applies to a layer 11 having a homogeneous composition.
    The stacking of layers 11 to 13 can be obtained beforehand by epitaxy growth stages, in a manner known per se. The materials of layers 11 to 13 are selected according to the electrical performance desired for transistor 1, and so as to be able to grow laterally a thermal oxide from layer 12 with a composition different from that of thermal oxides formed laterally from the layers 11 and 13. The differences in composition of the thermal oxides must make it possible to selectively etch one of the thermal oxides with respect to the other. The type of doping of the layer 101 is advantageously opposite to that of the layer 111, in order to limit the leaks towards the substrate 100.
    The stack of layers 11 to 13 here has a thickness typically between 10 and 300 nanometers. The layer 12 has a thickness typically between 5 and 100 nm (for example 15 nm), the definition of its thickness facilitating the definition of the electrical length of the channel. The layers 11 and 13 can have identical or different thicknesses, for example in order to adjust their electrical resistances. The layers 11 and 13 typically have respective thicknesses between 3 and 100 nm (for example 20 nm). In order to reduce the contact resistance at the source or the drain of a transistor 1, their thickness is advantageously at most equal to 15 nm. A reduced value of the respective thicknesses of layers 11 to 13 also facilitates the subsequent formation of spacers.
    The layer 13 is covered by a dielectric layer 21. The dielectric layer 21 is typically made of SiN, S1O2 or a combination of these two materials. Layer 21 forms a hard mask for stacking. The layer 21 here has a width of between 10 and 100 nanometers (for example 40 nm), corresponding to the width and which we want to define for the stack.
    In FIG. 34, the dielectric layer 21 was used to produce an anisotropic etching of the layers 13, 12 and 112, so that they have substantially the same length and the same width, corresponding to the pattern of the dielectric layer. 21. RIE reactive ion etching can
    ICG011127 FR Depot Text in particular to be implemented. Etching is interrupted when the layer
    111 is found on the side of the stacks 10.
    In FIG. 35, a step of growth of dielectric material has been implemented by thermal oxidation on the sides of the layers 112, 12 and 13. A vertical growth of dielectric material is also carried out on the layer
    111. The dielectrics are formed by thermal oxidation of layers 111, 112, 12 and 13 respectively (for example rapid thermal oxidation, with a process temperature typically between 750 and 1150 ° C). At the end of this step, a dielectric layer 330 is formed laterally on the layer 13, a dielectric layer 320 is formed laterally on the layer 12, and a dielectric layer 310 is formed laterally on the layer 112 and vertically on the layer 111. The layer 320 has a composition different from that of the dielectric layers 310 and 330. The layer 320 and the layers 310 and 330 can be the subject of selective etching because of their differences in composition. The layers 310, 320 and 330 here have identical thicknesses, it can also be envisaged that these thicknesses are distinct.
    In FIG. 36, a selective etching of the layers 310 and 330 has been carried out, so as to preserve the dielectric layer 320, forming sacrificial spacers 322 on either side of the layer 12.
    In FIG. 37, a conformal deposition of a dielectric layer 53 has been produced. In this example, the dielectric material of the layer 53 is for example SiN. The dielectric material of the layer 53 is for example deposited over a thickness of between 5 and 10 nm. The layer 53 then covers in particular the lateral faces of the layers 112 and 13. The layer 53 is intended to form spacers for the layers 112 and 13.
    In FIG. 38, anisotropic etching of the layer 53 has been carried out so as to uncover the upper face of the dielectric layer 21 and so as to uncover the upper face of the layer 111 on either side of the stacks 10. The layer 53 is kept on either side of the layers 112 and 13. Spacers 531 and 533 are provided on either side of the layers
    112 and 13 respectively. A fairly anisotropic type of RIE-ICP etching can be performed using the dielectric layer 21 as an etching mask. The spacers 531, 533 and the sacrificial spacers 322 are horizontally self-aligned with the dielectric layer 21 after this etching.
    In FIG. 39, a non-conformal deposition of a dielectric material was carried out to form a layer 54 on the layer 111, over a height corresponding substantially to that of the spacers 531. The dielectric material of the layer 54 is advantageously identical to that of layer 53. The
    ICG011127 EN Depot Text layer 54 deposited on the stacks 10 has here been removed by a chemical mechanical polishing step.
    In FIG. 40, the sacrificial spacers 322 were removed by selective etching. There are then recesses 25 self-aligned 5 vertically with the layer 12. The recesses 25 are of course also self-aligned with the layer 13 and the spacers 533 on the one hand, and the layer 112 and the layer 54 including the spacers 531 on the other hand. The etching of the sacrificial spacers 322 is for example a dry etching of the atomic layer etching type (ALE) or of a reactive ion etching type (RIE).
    The subsequent steps of forming the gate, and of forming the respective accesses to the drain, the source and the gate of each transistor 1 will not be described further and may, for example, be implemented in a similar manner to the second embodiment. .
    In the examples detailed above, horizontal growths of the dielectric layers by thermal oxidation have been described. Other modes of growth of the dielectric layers by oxidation can be envisaged, for example wet oxidation, for example by means of a mixture of water and peroxide, or by means of water with degassing of ozone .
    ICG011127 FR Text Depot
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    1. Method for manufacturing a vertical transistor (1), characterized in that it comprises the steps of:
    -providing a substrate (100) surmounted by a vertical stack (10) of first, second and third layers (11, 12, 13), respectively in first, second and third semiconductor materials, said second semiconductor material being different from the first and third semiconductor materials;
    -grow horizontally first, second and third dielectric layers (310, 320, 330) by oxidation, from the first, second and third layers (11, 12, 13) of semiconductor materials respectively, the oxidation inducing a second dielectric layer (320) whose thickness in said horizontal direction is different from the thickness of said first and third dielectric layers, or a second dielectric layer (320) whose composition is different from the composition of said first and third dielectric layers;
    -removing the second dielectric layer (320) so as to form a recess (25) vertically self-aligned with the second semiconductor layer (12), said recess being positioned vertically between first and second blocks arranged opposite the first and third semiconductor layers (11, 13) respectively;
    -forming a grid stack (42) in said self-aligned recess (25).
    [2" id="c-fr-0002]
    2. A method of manufacturing a vertical transistor (1) according to claim 1, wherein said oxidation induces a second dielectric layer (320) whose thickness is different from that of the first and third dielectric layers (310,330), said method comprising a step of etching the first to third dielectric layers with the same thickness, either so as to remove the second dielectric layer and to keep at least part of the first and third dielectric layers (331, 333), or so as to remove the first and third dielectric layers and retaining at least a portion of the second dielectric layer (322).
    [3" id="c-fr-0003]
    3. A method of manufacturing a vertical transistor (1) according to claim 2, wherein said oxidation induces a second dielectric layer (320) whose thickness is strictly less than that of the first and third dielectric layers (310,330), in which said recess (25) is formed between said first and third dielectric layers (310, 330) forming said first and second blocks respectively.
    [4" id="c-fr-0004]
    4. A method of manufacturing a vertical transistor (1) according to claim 2, wherein said oxidation induces a second dielectric layer (320) whose thickness is strictly greater than that of the first and third dielectric layers (310, 330) , the method comprising a step of forming a fourth and fifth dielectric layer (531,533) against the first and third semiconductor layers after the removal of the first and third dielectric layers, wherein said recess (25) is formed between said fourth and fifth dielectric layers (531,533) forming said first and second blocks respectively.
    [5" id="c-fr-0005]
    5. A method of manufacturing a vertical transistor (1) according to any one of claims 2 to 4, wherein said first to third semiconductor layers (11,12,13) are silicon-based layers, said second layer semiconductor (12) having a different phosphorus concentration than that of the first and third semiconductor layers (11, 13).
    [6" id="c-fr-0006]
    6. Method for manufacturing a vertical transistor (1) according to any one of claims 2 to 4, in which said first to third semiconductor layers (11,12,13) are silicon-based layers, said second layer semiconductor (12) having a Germanium concentration different from that of the first and third semiconductor layers (11, 13).
    [7" id="c-fr-0007]
    7. A method of manufacturing a vertical transistor (1) according to claim 1, in which said oxidation induces a second dielectric layer (320) whose composition is different from the composition of said first and third dielectric layers (310, 330), said method comprising either a step of selective etching of the second dielectric layer with respect to the first and third dielectric layers so as to remove the second dielectric layer (320) and to preserve at least part of the first and third dielectric layers, or a step selectively etching the first and third dielectric layers relative to the second dielectric layer so as to remove the first and third dielectric layers and retain at least a portion of the second dielectric layer (322).
    [8" id="c-fr-0008]
    8. A method of manufacturing a vertical transistor (1) according to claim 7, wherein the method comprises a selective etching of the first and third dielectric layers (310,330) relative to the second dielectric layer (320) so as to remove the first and third dielectric layers and at
    5 retaining at least part of the second dielectric layer (322), the method comprising a step of forming a sixth and seventh dielectric layer (531, 533) against the first and third semiconductor layers after the first and third dielectric layers have been removed, wherein said recess (25) is formed between said sixth and
    Seventh dielectric layers (531,533) forming said first and second blocks respectively.
    [9" id="c-fr-0009]
    9. A method of manufacturing a vertical transistor (1) according to any one of the preceding claims, in which the formation of the gate stack
    15 includes the formation of a grid insulator layer in said recess and the formation of a conductive material on said grid insulator layer.
    [10" id="c-fr-0010]
    10. A method of manufacturing a vertical transistor (1) according to any one of the preceding claims, wherein said recess formed belt
    Said second layer of semiconductor material (12).
    [11" id="c-fr-0011]
    11. Process for manufacturing a vertical transistor (1) according to any one of the preceding claims, in which said first semiconductor layer (11) has an upper part (112) and a lower part
    25 (111), said lower part extending laterally beyond said upper part for the substrate (100) supplied, said growth by oxidation inducing vertical growth of a lateral part of the first dielectric layer (310) from said lower part (111) of the first semiconductor layer, said grid stack (42) being formed on said part
    30 side of the first dielectric layer (310).
    [12" id="c-fr-0012]
    12. Method of manufacturing a vertical transistor (1) according to any one of the preceding claims, in which the said supply step is preceded by the steps of:
    35 - formation of a hard mask pattern (21) on the third layer (13) of semiconductor material;
    anisotropic etching of the first to third layers of semiconductor materials (11-13) according to the pattern of the hard mask.
    [13" id="c-fr-0013]
    13. Method for manufacturing a vertical transistor (1) according to claim 12, further comprising the steps of:
    forming a seventh dielectric layer (51) against a side face of said grid stack (42), the seventh dielectric layer being made of a material different from the hard mask (21);
    formation of an eighth dielectric layer (52) against a side face of the seventh dielectric layer (51), the eighth dielectric layer being made of a material different from the hard mask (21) and from the seventh dielectric layer (51);
    -forming an engraving pattern by photolithography;
    successive selective etchings according to said etching pattern of the hard mask (21), of the eighth dielectric layer and of a part of the seventh dielectric layer, so as to form respective recesses;
    -deposition of conductive material in said recesses so as to form drain, source and gate contacts respectively.
    [14" id="c-fr-0014]
    14. Method for manufacturing a vertical transistor (1) according to any one of the preceding claims, in which said step of horizontal growth of the first, second and third dielectric layers (310, 320, 330) is carried out by oxidation thermal.
    [15" id="c-fr-0015]
    15. A method of manufacturing a vertical transistor (1) according to any one of claims 1 to 13, wherein said step of horizontal growth of the first, second and third dielectric layers (310, 320, 330) is implemented by wet oxidation.
    1/14
    02 ^ 2020 $
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1662566|2016-12-15|
    FR1662566A|FR3060850B1|2016-12-15|2016-12-15|PROCESS FOR MANUFACTURING A VERTICAL CHANNEL NANOCOUCHES TRANSISTOR|FR1662566A| FR3060850B1|2016-12-15|2016-12-15|PROCESS FOR MANUFACTURING A VERTICAL CHANNEL NANOCOUCHES TRANSISTOR|
    US15/842,245| US10134875B2|2016-12-15|2017-12-14|Method for fabricating a transistor having a vertical channel having nano layers|
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