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    • 专利摘要:
    The invention relates to a CMOS pixel comprising: a photodiode (101) having a terminal connected to a GND potential and another terminal connected to a read node (SN) by a first MOS transistor (103); a second MOS transistor (105) connecting the read node (SN) to a potential VDDH; and a third MOS transistor (307) whose gate (407) is connected to the read node (SN), the transistors (103, 105, 307) having the same gate insulator thickness, wherein the third transistor (307) ) has a smaller gate length and / or gate width than the first (103) and second (105) transistors, in that the difference VDDH-GND is greater than the nominal voltage of the third MOS transistor (307), and the body or drain region of the third transistor (307) is connected to a potential VL between the potentials VDDH and GND.
    公开号:FR3058857A1
    申请号:FR1661107
    申请日:2016-11-16
    公开日:2018-05-18
    发明作者:Arnaud PEIZERAT
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    (57) The invention relates to a CMOS pixel comprising: a photodiode (101) having a terminal connected to a GND potential and another terminal connected to a read node (SN) by a first MOS transistor (103); a second MOS transistor (105) connecting the read node (SN) to a potential VDDH; and a third MOS transistor (307) whose gate (407) is connected to the read node (SN), the transistors (103, 105, 307) having the same thickness of gate insulator, in which the third transistor (307 ) has a gate length and / or width that is less than that of the first (103) and second (105) transistors, in that the difference VDDH-GND is greater than the nominal voltage of the third MOS transistor (307), and that the body or drain region of the third transistor (307) is connected to a potential VL between the potentials VDDH and GND.
    B15523 - DD17538ST
    REDUCED NOISE CMOS IMAGE SENSOR
    Field
    The present application relates to the field of CMOS image sensors. It aims in particular at a reduced noise CMOS image sensor, adapted to operate in low light conditions.
    Presentation of the prior art
    Conventionally, a CMOS image sensor comprises pixels arranged in a matrix in rows and columns. Each pixel has a photodiode used in reverse, the junction capacity of which is discharged by a photocurrent as a function of a received light intensity. At the end of a period known as image acquisition or integration, before and after which the pixel is reset by recharging its photodiode, the photogenerated charges accumulated in the photodiode are transferred to a capacitive node for reading the pixel . The measurement of the level of illumination received by the pixel is carried out by measuring the variation of the potential of the pixel reading node, caused by the transfer, onto this node, of the photogenerated charges in the photodiode of the pixel.
    In practice, various sources of noise are likely to affect the measurement, which can be problematic when the quantity of photogenerated charges in the photodiode is small,
    B15523 - DD17538ST especially when the sensor is used in low light conditions.
    There is a need for a CMOS image sensor overcoming all or part of the disadvantages of existing sensors. More particularly, there is a need for a reduced noise CMOS image sensor, suitable for operating in low light conditions.
    summary
    Thus, one embodiment provides a CMOS image sensor comprising at least one pixel comprising:
    a photodiode, a first terminal of which is connected to a node for applying a first reference potential;
    a first MOS transistor connecting a second terminal of the photodiode to a pixel read node;
    a second MOS transistor connecting the read node to an application node of a second reference potential; and a third MOS transistor mounted as a follower source, the gate of which is connected to the read node and the source of which is intended to be connected to a read circuit, the first, second and third transistors having the same thickness of gate insulator, wherein the third transistor has a gate length less than the gate lengths of the first and second transistors and / or a gate width less than the gate widths of the first and second transistors, the difference between the first and second reference potentials is greater at the maximum voltage that can be applied between two terminals of the third MOS transistor, and the body region or the drain region of the third transistor is connected to a node for applying a third reference potential comprised between the first and second potentials .
    According to one embodiment, the body region of the third transistor is isolated from the body region of the first transistor and the third reference potential applied to the
    B15523 - DD17538ST body region of the third transistor is different from the potential applied to the body region of the first transistor.
    According to one embodiment, the third transistor is a P-channel transistor.
    According to one embodiment, the first and second transistors are N-channel transistors, the body regions of the first and second transistors being connected to the application node of the first reference potential, the body region of the third transistor being connected to the application node of the second reference potential, and the drain region of the third transistor being connected to the application node of the third reference potential.
    According to one embodiment, the pixel further comprises a fourth MOS transistor connecting the source of the third transistor to an output track of the pixel.
    According to one embodiment, the fourth transistor has a gate length greater than that of the third transistor and / or a gate width greater than that of the third transistor.
    According to one embodiment, the fourth transistor is a transistor of the same type of conductivity as the third transistor.
    According to one embodiment, the photodiode is a pinched diode comprising an N-type doped accumulation region, formed in a P-type doped substrate, and a P-type doped layer coating the accumulation region, said layer having a doping level higher than that of the substrate.
    According to one embodiment, the first, second and third transistors are N-channel transistors, the body regions of the first and second transistors being connected to the application node of the first reference potential, the body region of the third transistor being connected to the application node of a fourth reference potential, and the drain region of the third transistor being connected to an application node of a fifth reference potential.
    B15523 - DD17538ST
    According to one embodiment, the sensor is produced in a technological process making it possible to form on the same chip MOS transistors having a first thickness of gate insulator and MOS transistors having a second thickness of gate insulator greater than the first thickness, and the first, second and third transistors have the second thickness of gate insulator.
    According to one embodiment, the sensor further comprises a peripheral control circuit comprising at least one MOS transistor having a thickness of gate insulator less than that of the first, second and third transistors.
    Brief description of the drawings
    These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures, among which:
    Figure 1 is an electrical diagram of an example of a pixel of a CMOS image sensor;
    Figure 2 is a simplified sectional view of the pixel of Figure 1;
    FIG. 3 is an electrical diagram of an example of an embodiment of a pixel of a CMOS image sensor; and FIG. 4 is a schematic sectional view illustrating an exemplary embodiment of the pixel of FIG. 3.
    detailed description
    The same elements have been designated by the same references in the different figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed. In particular, the peripheral circuits for reading and controlling the image sensors described have not been detailed, the production of such circuits being within the reach of those skilled in the art from the functional indications of the present description. In the following description, when we do
    B15523 - DD17538ST reference to qualifiers of absolute position, such as the terms front, rear, etc., or relative, such as the terms above, below, upper, lower, etc., reference is made to the orientation of the views in section of FIGS. 2 and 4, it being understood that, in practice, the devices described can be oriented differently. Unless specified otherwise, the expressions approximately, appreciably, and of the order of mean to 10%, preferably to 5%.
    FIG. 1 is an electrical diagram representing an example of a pixel 100 of a CMOS image sensor. The pixel 100 comprises a photodiode 101, an accumulation node K formed by the cathode of the photodiode 101, and a read node SN. The anode of photodiode 101 is connected to a node for applying a low reference potential GND, for example ground. The pixel 100 further comprises a transfer transistor 103, the conduction nodes (source / drain) of which are connected respectively to the node K and the node SN, a reset transistor 105, the conduction nodes of which are respectively connected to the node SN and to a node for applying a high reference potential VDDH, a read transistor 107 mounted as a tracking source (known by the name “source follower”), the gate of which is connected to the node SN and the drain of which is connected to a node for applying a reference potential, and a selection transistor 109, the conduction nodes of which are respectively connected to the source of the read transistor 107 and to an output conductive track 111, generally called a column, which can be common to several pixels of the sensor.
    In the example shown, the transistors 103, 105, 107 and 109 are N-channel MOS transistors, and the transistor 107, mounted as a tracking source (or common drain assembly), has its drain connected to an application node. of a high reference potential, the VDDH potential in this example.
    In operation, the potential variations of the node SN are transferred to the source of the transistor 107 substantially identically, that is to say without amplification or with a gain of
    B15523 - DD17538ST the order of 1. Pixel 100 receives control signals TX, RT and RS applied respectively to the gates of transistors 103, 105 and 109.
    As an example, pixel 100 can be controlled as follows:
    - During a pixel integration phase (preceded by a reset step of the photodiode 101), the transfer transistor 103 can be kept non-conducting (signal TX at a low state in this example) to isolate the node from accumulation K of the reading node SN. The electric charges generated in photodiode 101 under the effect of light then cause a gradual decrease in the potential of node K.
    - Before the end of the integration phase, the reset transistor 105 can be turned on (signal RST at a high state in this example) so as to reset the potential of the read node SN to the potential VDDH, then the transistor 105 can be opened in order to isolate the node SN from the node VDDH.
    - After the reset step of the node SN, the potential of the node SN can be read and stored during a first reading step, so as to constitute a reference for a later step of measuring the discharge level of the photodiode. For this, the selection transistor 109 is turned on (signal RS at a high state in this example), so that the potential of the node SN is transferred to the output track 111, via the transistors 107 and 109. The potential of track 111 can then be read and stored, via a reading circuit not shown.
    - After the first reading step, the transfer transistor 103 can be closed (signal TX in the high state in this example) so as to cause the transfer of the photogenerated charges accumulated in the photodiode on the reading node SN. The potential of the node SN then decreases by a value representative of the quantity of photogenerated charges accumulated in the photodiode, and therefore of the light intensity received by the photodiode, during integration.
    B15523 - DD17538ST
    - The potential of the node SN, transferred to the output track 111 by the transistors 107 and 109, can then be read again during a second reading step, by a reading circuit not shown.
    - The pixel output value is for example equal to the difference between the reference potential Vqu ^] _ read on track 111 during the first reading step, and the potential Vqu ^ 2 read on track 111 during second reading step.
    An advantage of this reading process, generally designated in the art by the acronym CDS, from the English Correlated Double Sampling - is that it makes it possible to at least partially overcome certain sources of noise, such as the reset noise introduced by the transistor 105.
    Other reading methods can be used to reduce noise, for example a reading method of the type generally designated in the art by the acronym CMS, from the English Correlated Multiple Sampling - including correlated multiple sampling. several successive samples of the pixel output value, which increases the signal to noise ratio.
    FIG. 2 is a simplified sectional view illustrating an exemplary embodiment of the pixel 100 in FIG. 1. In this example, the pixel 100 is formed in and on a portion of a semiconductor substrate 201 (for example made of silicon) doped with type P.
    The photodiode 101 is formed near the upper surface or front face of the substrate 201, and comprises an N-type doped region 203, surmounted by a P-type doped region 205 with a doping level higher than that of the substrate 201. The region 203 defines an area for the accumulation of photogenerated charges. In this example, the photodiode 101 is a pinned diode, or buried photodiode. In the absence of photogenerated charges, the potential of the accumulation region 203 is defined by the doping levels of regions 201, 203 and
    B15523 - DD17538ST
    205, and is for example equal to 1.5 V. The use of a pinched diode makes it possible to significantly reduce the noise of the pixel, and more particularly the noise linked to the dark currents and the reset noise.
    The transistor 103 comprises an N-type doped region 207, for example with a doping level higher than that of the region 203, separated from the photodiode by a region of the substrate 201, and an insulated gate 209 covering the surface of the substrate 201 between the photodiode 101 and the region 207. The region 207 defines the drain of the transistor 103, and the region 203 defines the source of the transistor 103. The portion of the substrate 201 located under the gate 209, between the regions 203 and 207, defines the region of body, or channel forming region, of transistor 103.
    The transistor 105 comprises an N-type doped region 211, for example of the same doping level as the region 207, separated from the region 207 by a portion of the substrate 201, and an insulated gate 213 covering the surface of the substrate 201 between the region 207 and the region 211. The region 207 defines the source of the transistor 105, and the region 211 defines the drain of the transistor 105. The portion of the substrate 201 located under the gate 213, between the regions 207 and 211, defines the body region , or channel forming region, of transistor 105.
    The transistor 107 comprises an N-type doped region 215, for example of the same doping level as the region 207, separated from the region 211 by a portion of the substrate 201, and an insulated gate 217 coating the surface of the substrate 201 between the region 211 and the region 215. The region 215 defines the source of the transistor 107, and the region 211 defines the drain of the transistor 107. The portion of the substrate 201 situated under the gate 217, between the regions 211 and 215, defines the body region , or channel forming region, of transistor 107.
    The transistor 109 comprises an N-type doped region 219, for example of the same doping level as the region 207, separated from the region 215 by a portion of the substrate 201, and an insulated gate 221 coating the surface of the substrate 201 between the region
    B15523 - DD17538ST
    215 and region 219. Region 219 defines the source of transistor 109, and region 215 defines the drain of transistor 109. The portion of substrate 201 located under gate 221, between regions 215 and 219, defines the body region , or channel forming region, of transistor 109.
    In this example, the gate 209 of the transistor 103 is connected to a node for applying the signal TX, the gate 213 of the transistor 105 is connected to a node for applying the signal RT, the gate 217 of the transistor 107 is connected to the node SN, the gate 221 of the transistor 109 is connected to a node for applying the signal RS, the region 207 is connected to the node SN, the region 211 is connected to a node for applying the high reference potential VDDH, the substrate 201 (and consequently the anode of the diode 101 as well as the body regions of the transistors 103, 105, 107 and 109) is connected to a node for applying the low reference potential GND, and the region 219 is connected to the exit track 111.
    A problematic noise source in applications with low illumination level is the read noise produced by the read transistor mounted as a follower source, and more particularly the 1 / f component of the read noise, also called flickering noise. This noise source remains significant even when a CDS or CMS type reading is implemented, and can become predominant in low light conditions.
    Patent application EP2966687 previously filed by the applicant teaches that the variance Q 2 (in [Coulomb ^]) of the 1 / f component of the read noise reported at the input, introduced by the read transistor mounted as a follower source , can be expressed as follows:
    Q 2 = a CMS c 0X 2 WL ^ SN + Cgs ^^ + C CD ^) 2 (U,
    K being a parameter proportional to kT depending on the technology considered (where k is the Boltzman constant and T
    B15523 - DD17538ST is the absolute temperature), apMS being a noise reduction factor independent of the pixel structure and dependent solely on the product of the bandwidth of the circuit by the time separating the successive steps of reading the samples (in the case of 'a CMS type reading), as well as the number of samples accumulated to generate the pixel output value, C ox being the grid-substrate surface capacitance formed by the gate oxide of the reading transistor mounted as a follower source, W and L being respectively the gate width (dimension orthogonal to the direction of flow of the source-drain current) and the gate length (dimension parallel to the direction of flow of the source-drain current) of the read transistor, Cg ^ being the capacity of the read node SN, depending in particular on the parasitic capacities of the reset transistor and the transfer transistor, and cgg and cgp being respectively the gate-source surface capacitance and the gate-drain linear capacitance of the read transistor.
    To reduce the 1 / f component of the read noise, the aforementioned patent application EP2966687 proposes a pixel in which the read transistor mounted as a follower source has a thickness of gate oxide less than that of the other transistors of the pixel.
    In fact, in a given die for manufacturing integrated circuit chips in CMOS technology, there are generally two different thicknesses of gate oxide for producing MOS transistors. Conventionally, in an image sensor comprising pixels with four MOS transistors of the type described in relation to FIGS. 1 and 2, the four transistors of the pixel (transistors 103, 105, 107 and 109) are oxide transistors thick. The thick oxide transistors can indeed operate at nominal voltages greater than the nominal operating voltages of the thin oxide transistors, and thus make it possible to produce pixels having a greater dynamic range (or measurement range). The use of thick oxide transistors is all
    B15523 - DD17538ST particularly suitable when the photodiode is a pinched diode of the type described in relation to FIG. 2. This type of photodiode has an open circuit voltage (in the absence of photogenerated charges) which can be relatively high, for example close to the nominal operating voltage of MOS thin oxide transistors. Using only thin oxide transistors would therefore not allow a sufficient dynamic range of operation of the pixel to be obtained.
    The pixel described in patent application EP2966687 comprises a photodiode, a read node, a transfer transistor, a reset transistor, and a read transistor mounted as a follower source, the transfer transistor and the reset transistor being transistors. with thick oxide, and the read transistor being a transistor with thin oxide. The use of a thin oxide read transistor makes it possible to increase the surface capacitance grid-substrate C ox formed by the gate oxide of the read transistor with respect to a pixel in which all the transistors are oxide transistors. thick. This makes it possible to significantly reduce the 1 / f component of the pixel read noise. In addition, an additional advantage is that the thin oxide MOS transistors can be dimensioned to have a gate area (WL) less than the minimum gate area which can be given to thick oxide transistors. This again contributes to reducing the 1 / f component of the reading noise (as appears from equation (1) above in which the surface WL is squared in the numerator).
    In the aforementioned patent application EP2966687, so as not to lose dynamics with respect to a pixel in which all the transistors are thick oxide, the body region of the read transistor is isolated from the body regions of the transfer and reset transistors . The body and drain regions of the read transistor are polarized so that the read transistor can receive on its gate the entire potential excursion of the read node SN
    B15523 - DD17538ST (going from the reset potential to the saturation potential of the pixel), without the gate-drain or gate-body voltage of the read transistor exceeding the nominal operating voltage VDDL of a MOS transistor with thin oxide. The body and drain regions of the read transistor are for example polarized so that the body-drain voltage of the read transistor is equal to the nominal operating voltage VDDL of the MOS thin oxide transistors. The transfer and reset transistors remain polarized at a voltage preferably equal to the nominal operating voltage VDDH of the thick oxide MOS transistors to maximize the range of possible measurement values.
    The solution described in the aforementioned patent application EP2966687, however, has limitations, in particular in the advanced CMOS manufacturing dies, typically in the dies in which the shortest possible gate length of the MOS transistor is less than or equal to 130 nm.
    In fact, the inventors have found that, in advanced systems, the pixel described in patent application EP2966687 is subject not only to the aforementioned 1 / f noise, but also to another source of noise which could be neglected in the systems older, related to the flow of a leakage current through the gate oxide of the read transistor mounted as a follower source. This leakage noise, also called shot noise in English, or shot noise, is linked to the significant reduction in the thickness of the gate oxide of the thin oxide transistors in advanced technologies, leading to the flow of d 'a tunneling current from the read node SN to the body and / or the drain of the read transistor, through the gate oxide of the read transistor. The variance Q 2 (in [Coulomb ^]) of the leakage noise reported at the input, introduced by the read transistor mounted as a follower source, can be expressed as follows:
    Q 2 = 2a stl otqIiTs (2),
    B15523 - DD17538ST
    I L being the mean value of the total leakage current through the gate oxide of the read transistor, q being the charge in electrons on the read node, T s being the duration between the successive read steps of the read process with correlated multiple sampling, and a s p o p being a constant parameter function of the number M of successive reading steps of the reading process with correlated multiple sampling (substantially equal to 0.5 for M = 2, that is to say - say in the case of a correlated double sampling reading).
    This leakage noise is added to the aforementioned 1 / f noise, expressed by equation (1).
    Depending on the technological sector considered, the leakage noise can become significant, even preponderant, canceling out the advantages described above linked to the use of a thin oxide read transistor.
    According to one aspect of an embodiment, a pixel is provided comprising a photodiode, a read node, a transfer transistor, a reset transistor, and a read transistor mounted as a tracking source, in which the transfer transistor, the reset transistor and the read transistor have substantially the same thickness of gate oxide, and in which the read transistor has a gate length L less than the smallest of the gate lengths of the transfer and reset transistors, and / or a gate width W less than the smallest of the gate widths of the transfer and reset transistors.
    The provision of a read transistor of reduced L and / or W dimensions compared to the transfer and reset transistors makes it possible to reduce the component in 1 / f of the read noise of the pixel. Preferably, the transistors are thick oxide transistors, which also makes it possible to significantly reduce, and even make negligible, the component of the reading noise linked to the leakage in the gate oxide of the reading transistor.
    B15523 - DD17538ST
    In a given die chip manufacturing integrated circuits in CMOS technology, for a given gate oxide thickness, and for a nominal voltage of given operating, there is typically a minimum gate length Lmin e t a minimum gate width W m j_ n below which it is advisable not to descend in order not to risk a breakdown of the transistor.
    According to one aspect, provision is made here to give the pixel read transistor a gate length L less than the minimum gate length L m -j_ n which the transfer and reset transistors can accept at their nominal operating voltage VDDH, and / or a gate width W less than the minimum gate width W m -j_ n which the transfer and reset transistors can accept at their nominal operating voltage VDDH. The maximum voltage VDDL 'that the read transistor can support, or nominal operating voltage of the read transistor, is then lower than the nominal operating voltage VDDH of the transfer and reset transistors.
    In order not to lose dynamics with respect to a pixel in which all the transistors are thick oxide and can operate at the voltage VDDH, the body region of the read transistor is isolated from the body regions of the transfer and reset transistors. The body and drain regions of the read transistor are polarized so that the read transistor can receive on its gate the entire potential excursion of the read node SN (ranging from the reset potential to the saturation potential of the pixel ), without the gate-drain or gate-body voltage of the read transistor exceeding the voltage VDDL '. The body and drain regions of the read transistor are for example polarized so that the body-drain voltage of the read transistor is equal to the voltage VDDL '. The transfer and reset transistors remain polarized at a voltage preferably equal to their nominal voltage of
    B15523 - DD17538ST VDDH operation, to maximize the range of possible measurement values.
    FIG. 3 is an electrical diagram of an exemplary embodiment of a pixel 300 of a CMOS image sensor. The pixel 300 includes, like the pixel 100 of the example of FIG. 1, a photodiode 101, an accumulation node K formed by the cathode of the photodiode 101, and a read node SN. The anode of photodiode 101 is connected to a node for applying a low reference potential GND, for example ground. The pixel 300 further comprises, as in the example of FIG. 1, a transfer transistor 103 connecting the node K to the node SN, and a reset transistor 105 connecting the node SN to a node for applying a potential of reference high VDDH. The pixel 300 further comprises a read transistor 307 mounted as a tracking source, the gate of which is connected to the node SN and the drain of which is connected to a node for applying an intermediate reference potential VL, and a selection transistor 309, the conduction nodes of which are respectively connected to the source of the read transistor 307 and to an output conductive track 111, which may be common to several pixels of the sensor.
    In the example shown, the transistors 103 and 105 are N-channel MOS transistors, and the transistors 307 and 309 are P-channel MOS transistors. In this example, the transistors 103, 105, 307 and 309 are transistors with thick oxide. The transistors 103 and 105 have dimensions W and L such that they can withstand without degradation the bias voltage VDDH of the pixel. In other words, the nominal operating voltage of the transistors 103 and 105 is greater than or equal to the bias voltage VDDH of the pixel. The transistor 307, on the other hand, has a reduced gate length and / or a reduced gate width, where it follows that the maximum voltage VDDL 'that the transistor 307 can withstand is lower than the bias voltage VDDH of the pixel.
    Transistors 103 and 105 have their body regions connected to a low reference potential application node
    B15523 - DD17538ST
    GND, and transistors 307 and 309 have their body regions connected to a node for applying the high reference potential VDDH. The read transistor 307 has its drain connected to a node for applying an intermediate reference potential VL, comprised between the low reference potential GND and the high reference potential VDDH. As a variant, the body region of the read transistor 307 can be connected to the source of this same transistor.
    In operation, the potential variations of the node SN are transferred to the source of the transistor 307 substantially identically. The pixel 300 receives control signals TX, RT and RS applied respectively to the gates of the transistors 103, 105 and 309.
    By way of example, the pixel 300 can be controlled substantially in the same way as the pixel 100 in FIG. 1, by adapting the level of the logic signals according to the type of conductivity of the transistors.
    The voltage VDDH (taken with respect to the ground GND) is for example substantially equal to the nominal operating voltage of the transistors 103 and 105. The intermediate potential VL applied to the drain of the transistor 307 can be chosen so that, under conditions normal usage of the pixel, the transistor 307 never sees a voltage higher than the maximum voltage VDDL '(taken with respect to the ground) which it can support taking into account the reduction in its dimensions. By way of example, the voltage difference VDDH-VL corresponds to the nominal operating voltage VDDL 'of transistor 307.
    By way of illustrative example (not limiting), we consider a technological sector in which the thick oxide MOS transistors are designed to operate at voltages up to 3.3 V as long as their gate length is not less than a value L ^ n = 0.5 pm and that their gate width is not less than a value W m -j_ n less than 0.4 pm. Provision is then made to give transistor 307 a gate length of the order of 0.3 μm and a width of
    B15523 - DD17538ST gate of the order 0.3 μm, where it follows that the maximum voltage which the transistor 307 can support is of the order of 2.5 V. The low reference potential GND is for example equal to 0 V, and the high reference potential VDDH at 3.3 V. The intermediate reference potential VL applied to the drain of the read transistor 307 is then chosen to be greater than or equal to 0.8 V so that the transistor 307 does not see never a voltage greater than 2.5 V between any two of its four terminals (grid, source, drain, body).
    If the open circuit voltage Vpin of the photodiode is of the same order of magnitude as the nominal supply voltage VDDL 'of transistor 307, then the range of variation of the potential (or voltage taken with respect to ground) Vg ^ of the node reading has an amplitude substantially equal to VDDL '. More precisely, the potential Vg ^ varies between a value Vpin and the maximum reset voltage of the node SN, which is equal to VDDH-Vp n , where Vp n is the threshold voltage of the reset NMOS transistor. If the amplitude of variation at the node SN, equal to VDDH-Vtn-Vpin, is less than the voltage VDDL 'then it is possible to find a reference potential VL of the read transistor which makes it possible to respect the maximum voltage accepted between two terminals of the read transistor.
    The selection transistor 309 is preferably a MOS transistor with dimensions greater than or equal to the minimum dimensions W m -j_ n and L m -j_ n to be observed in order to hold the voltage VDDH. Indeed, the use of a selection transistor of reduced dimensions would require controlling the gate of this transistor with a control voltage having a controlled excursion so as not to damage the transistor. In the case of the example described above, in relation to FIG. 3, the control voltage of the gate of the selection transistor 309, if the latter had reduced dimensions such that its nominal operating voltage is equal to VDDL ', could for example oscillate between a low level equal to the reference potential VL and the high reference potential VDDH. The implementation of such
    B15523 - DD17538ST control, however, makes it more complex to produce the peripheral sensor control circuits.
    In addition, it is preferable that the selection transistor 309 is of the same type of conductivity as the read transistor 307, so that the potential level present on the source of the read transistor is correctly transmitted on the output conductive track 111 of the pixel.
    FIG. 4 is a simplified sectional view illustrating an exemplary embodiment of the pixel 300 of FIG. 3. In this example, the pixel 300 is formed in and on a portion of a semiconductor substrate 201 (for example made of silicon) doped with type P. The photodiode 101, the transistor 103 and the transistor 105 are substantially identical to what has been described in relation to FIG. 2, and the transistors 307 and 309 are produced in the same N type doped well 401, formed in an upper part of the substrate 201.
    The transistor 307 comprises two P-type doped regions 403 and 405, formed in an upper part of the box 401 and separated by a portion of the box 401. The transistor 307 further comprises an insulated gate 407 coating the surface of the box 401 between the region 403 and the region 405. The region 403 defines the drain region of the transistor 307, and the region 405 defines the source region of the transistor 307. The portion of the well 401 located under the gate 407, between the regions 403 and 405, defines the body region, or channel-forming region, of transistor 307.
    The transistor 309 comprises a P-type doped region 409, for example of the same doping level as the regions 403 and 405, separated from the region 405 by a portion of the well 401, and an insulated gate 411 coating the surface of the well 401 between region 405 and region 409. Region 405 defines the drain region of transistor 309, and region 409 defines the source region of transistor 309. The portion of well 401 located under gate 411, between regions 405 and 409 , defines the body region, or channel forming region, of transistor 309.
    B15523 - DD17538ST
    In this example, the gate 209 of the transistor 103 is connected to a node for applying the signal TX, the gate 213 of the transistor 105 is connected to a node for applying the signal RT, the gate 407 of the transistor 307 is connected to the node SN, the gate 411 of the transistor 309 is connected to a node for applying the signal RS, the region 207 is connected to the node SN, the region 211 is connected to a node for applying the high reference potential VDDH, the substrate 201 (and consequently the anode of the diode 103 as well as the body regions of the transistors 103 and 105) is connected to a node for applying the low reference potential GND, the well 401 (and consequently the body regions of the transistors 307 and 309) is connected to a node for applying the high reference potential VDDH, the region 403 is connected to a node for applying the intermediate reference potential VL, and the region 409 is connected to the output track 111 .
    In the example shown, the transistors 103, 105 and 309 have substantially the same gate length, greater than the gate length of the transistor 307.
    Advantageously, in the case of an image sensor with several pixels, neighboring pixels can share the same box 401 for forming the transistors 307 and 309, which makes it possible to reduce the size of the sensor.
    Particular embodiments have been described. Various variants and modifications will appear to those skilled in the art.
    In particular, a person skilled in the art will know how to adapt the embodiments described in the case where the read transistor mounted as a follower source is an MOS transistor of type N. In this case, the body region of the read transistor can be isolated from the body regions of the transfer and reset transistors using a triple box structure, in order to be able to isolate the body region of the read transistor from the substrate 201, so that they can be polarized at different voltages. The body region of the read transistor can
    B15523 - DD17538ST then be connected to an application node with an intermediate reference potential VrefLow which is preferably less than or equal to the minimum voltage that can be present on the source of the read transistor, ie Vpin-Vtl (where Vtl is the threshold voltage of the reading transistor of reduced dimensions), for example 1.5V-0.5V = IV. The drain region of the read transistor is then connected to a node for applying a reference potential VrefHigh, which preferably does not exceed VrefLow + VDDL '. The reference potentials VrefLow and VrefHigh are thus preferably chosen so that the read transistor never sees at its terminals a voltage greater than the voltage VDDL '.
    Such an embodiment with an NMOS type read transistor requires the use of a triple box structure which is bulky and reduces the pixel density. In addition, two voltage references VrefLow and Vrefhigh, different from the supply voltages and from the ground, may prove to be necessary in practice to comply with the voltage constraints of the transistor of reduced dimensions. For this last point, it is possibly conceivable to bias the drain of the reset transistor 105 to the same voltage Vrefhigh as that applied to the drain of the NMOS selection transistor because the maximum level that can pass through the NMOS transistor is equal to VDDH- Vtn2 (Vtn2 being the threshold voltage of the NMOS reset transistor), ie for example 3.3V-0.5V = 2.8V.
    In addition, the inventors have found in practice that the use of an NMOS transistor as a read transistor does not make it possible to have as good results for noise in 1 / f as with a PMOS transistor.
    Thus, in the case of a photodiode of the pinched diode type associated with an NMOS transfer transistor, the preferred embodiment is that described in relation to FIG. 3, with transfer and reset transistors of the NMOS type, a transistor PMOS type readout of reduced dimensions, and a PMOS type selection transistor.
    B15523 - DD17538ST
    Although the use of a pinched photodiode of the opposite type to that shown in FIG. 3 is relatively rare, one could have an N + / P / N photodiode, on an N type substrate, associated with a PMOS type transfer transistor. . In this case, one could consider having only PMOS type transistors, the read transistor having reduced dimensions compared to the transfer and reset transistors, and preferably, compared to the selection transistor. In addition, in the case of such an N + / P / N photodiode, the cathode would be connected to the high reference potential VDDH and the anode would be connected to the transfer transistor.
    Furthermore, although the above examples show transfer and reset transistors of the same type, they could be different. However, for reasons of density and also of limitation of the surfaces of boxes liable to create parasitic diodes, it is preferable to use the same type of transistors.
    Furthermore, the embodiments described are not limited to the digital examples of bias potentials mentioned above.
    In addition, the embodiments described are not limited to the particular case described above, in which the photodiode is a pinched diode.
    B15523 - DD17538ST
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    1. CMOS image sensor comprising at least one pixel (300) comprising:
    a photodiode (101), a first terminal of which is connected to a node for applying a first reference potential (GND);
    a first MOS transistor (103) connecting a second terminal of the photodiode (101) to a pixel read node (SN);
    a second MOS transistor (105) connecting the read node (SN) to a node for applying a second reference potential (VDDH); and a third MOS transistor (307) mounted as a tracking source, the gate (407) of which is connected to the read node (SN) and the source of which is intended to be connected to a read circuit, the first (103), second ( 105) and third (307) transistors having the same thickness of gate insulator, characterized in that the third transistor (307) has a gate length less than the gate lengths of the first (103) and second (105) transistors and / or a gate width less than the gate widths of the first (103) and second (105) transistors, in that the difference between the first (GND) and second (VDDH) reference potentials is greater than the maximum voltage that can be applied between two terminals of the third MOS transistor (307), and in that the body region or the drain region of the third transistor (307) is connected to an application node of a third reference potential (VL) included Between the first (GND) and second (VDDH) potentials.
    [2" id="c-fr-0002]
    2. The sensor of claim 1, wherein the body region of the third transistor (307) is isolated from the body region of the first transistor (103) and the third reference potential (VL) applied to the body region of the third transistor (307) is different from the potential applied to the body region of the first transistor (103).
    B15523 - DD17538ST
    [3" id="c-fr-0003]
    3. The sensor of claim 1 or 2, wherein the third transistor (307) is a P channel transistor.
    [4" id="c-fr-0004]
    4. The sensor of claim 3, wherein the first (103) and second (105) transistors are N-channel transistors, the body regions of the first (103) and second (105) transistors being connected to the application node of the first reference potential (GND), the body region of the third transistor (307) being connected to the application node of the second reference potential (VDDH), and the drain region of the third transistor (307) being connected to the node application of the third reference potential (VL).
    [5" id="c-fr-0005]
    5. Sensor according to any one of claims 1 to 4, wherein said at least one pixel (300) further comprises a fourth MOS transistor (309) connecting the source of the third transistor (307) to an output track (111 ) of the pixel.
    [6" id="c-fr-0006]
    6. The sensor of claim 5, wherein the fourth transistor (309) has a gate length greater than that of the third transistor (307) and / or a gate width greater than that of the third transistor (307).
    [7" id="c-fr-0007]
    7. The sensor of claim 5 or 6, wherein the fourth transistor (309) is a transistor of the same type of conductivity as the third transistor (307).
    [8" id="c-fr-0008]
    8. Sensor according to any one of claims 1 to 7, in which the photodiode (101) is a pinched diode comprising an N-type doped accumulation region (203) formed in a P-type doped substrate (201) , and a P-type doped layer (205) coating the accumulation region (203), said layer (205) having a doping level higher than that of the substrate (201).
    [9" id="c-fr-0009]
    9. The sensor of claim 2, wherein the first (103), second (105) and third transistors are N-channel transistors, the body regions of the first (103) and second (105) transistors being connected to the node d application of the first reference potential (GND), the body region of the third transistor (307) being connected to the application node
    B15523 - DD17538ST of a fourth reference potential (Vreflow), and the drain region of the third transistor (307) being connected to an application node of a fifth reference potential (Vrefhigh).
    [10" id="c-fr-0010]
    10. Sensor according to any one of claims 1 5 to 9, produced in a technological sector making it possible to form on the same chip MOS transistors having a first thickness of gate insulator and MOS transistors having a second thickness of insulator of grid greater than the first thickness, in which the first (103), second (105) and third (307)
    10 transistors have the second thickness of gate insulator.
    [11" id="c-fr-0011]
    11. Sensor according to any one of claims 1 to 10, further comprising a peripheral control circuit comprising at least one MOS transistor having a thickness of gate insulator less than that of the first (103), second
    [12" id="c-fr-0012]
    15 (105) and third (307) transistors.
    B 15523 DD 17538ST
    1/1
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    同族专利:
    公开号 | 公开日
    EP3324612B1|2020-01-29|
    US10249671B2|2019-04-02|
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    EP3324612A1|2018-05-23|
    FR3058857B1|2018-12-07|
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    US10225499B2|2016-04-11|2019-03-05|Semiconductor Components Industries, Llc|Backside illuminated global shutter pixel with active reset|
    FR3058857B1|2016-11-16|2018-12-07|Commissariat A L'energie Atomique Et Aux Energies Alternatives|CMOS IMAGE SENSOR WITH REDUCED NOISE|FR3058857B1|2016-11-16|2018-12-07|Commissariat A L'energie Atomique Et Aux Energies Alternatives|CMOS IMAGE SENSOR WITH REDUCED NOISE|
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    法律状态:
    2017-11-30| PLFP| Fee payment|Year of fee payment: 2 |
    2018-05-18| PLSC| Search report ready|Effective date: 20180518 |
    2018-11-29| PLFP| Fee payment|Year of fee payment: 3 |
    2020-10-16| ST| Notification of lapse|Effective date: 20200910 |
    优先权:
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    FR1661107A|FR3058857B1|2016-11-16|2016-11-16|CMOS IMAGE SENSOR WITH REDUCED NOISE|
    FR1661107|2016-11-16|FR1661107A| FR3058857B1|2016-11-16|2016-11-16|CMOS IMAGE SENSOR WITH REDUCED NOISE|
    EP17200203.2A| EP3324612B1|2016-11-16|2017-11-06|Reduced noise cmos image sensor|
    US15/810,342| US10249671B2|2016-11-16|2017-11-13|Low-noise CMOS image sensor|
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