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    • 专利摘要:
    The invention relates to a system (100) comprising: a first memory (101) comprising several portions (Si) of one or more pages (Pi, j) each, this memory (101) comprising first (PTR) and second ( PTW) ports for accessing at the same time, respectively read and write, two pages (Pi, j) of portions (Si) distinct from the memory (101); and a control circuit (103) adapted to perform write operations in pages (Pi, j) of the memory (101), each write operation in a page (Pi, j) of the memory (101) comprising a step of reading an old data in this page (Pi, j) via the first port (PTR), followed by a step of writing a new data in this page (Pi, j) via the second port (PTW) taking into account the old data.
    公开号:FR3015103A1
    申请号:FR1362469
    申请日:2013-12-12
    公开日:2015-06-19
    发明作者:Michel Harrand
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] B12956 - DD14847ST 1 DATA WRITING SYSTEM IN A MEMORY Domain The present application relates to the field of electronic memories. BACKGROUND OF THE PRIOR ART In the present application, the term "memory", "memory device" or "electronic memory" denotes a device comprising a plurality of elementary storage cells, each cell being able to be programmed to store one or more data bits. In practice, a memory can contain a very large number of elementary cells, typically several million to several hundreds of billions. Of particular interest are so-called resistive memories, that is to say in which each elementary storage cell comprises an element whose resistance can be modified by applying a bias voltage to it. Among the most widespread resistive memories, there may be mentioned: phase change memories, generally referred to in the art by the acronym PCM (Phase Change Memory), in which the resistive element is made using a material whose crystalline state B12956 - DD14847ST 2 can be changed and therefore the resistivity, by varying its temperature during writing; conductive bridge memories, generally designated in the art by the acronym CBRAM (Conductive Bridge Random Access Memory), in which the resistive element is made using an insulating material in which a conductive filament can be created or removed by applying a bias voltage; and oxidation-reduction memories, generally referred to in the art by the acronym OxRRAM (of the English "Oxide-based Resistive Random Access Memory"), in which the resistive element is also realized with the aid of an insulating material in which a conductive filament can be created or removed by applying a bias voltage. A disadvantage of resistive memories is that they have a relatively short life or endurance. As an illustrative example, the number of writes that can typically support an elementary cell of a resistive memory is of the order of 108, while this number is almost infinite, for example of the order of 1016, for a cell of a volatile capacitive memory of the DRAM type. Another disadvantage of resistive memories is that writing a bit in a memory cell requires a relatively large amount of electrical energy. To increase the lifetime of a PCM type memory and to reduce its power consumption, it has been proposed in the article entitled "Durable and Energy Efficient Main Memory Ping Zhou Zhou Change of Memory Technology" et al. at each write operation of a new piece of data in the memory, to start by reading the data contained in the area of the memory that one wishes to write, then to write in the memory only the bits of the new data whose value differs from the bits of the old data. The wear of the memory and the electrical energy consumed during a reading step being relatively small compared to the wear of the memory and to the electrical energy consumed during a step of FIG. writing, this increases the lifetime of the memory and reduce its power consumption by avoiding redundant writes.
    [0002] However, a disadvantage of this solution is that the reading step that precedes each write step during a write operation in the memory, causes a significant increase in write times in the memory.
    [0003] SUMMARY Thus, an embodiment provides a system comprising: a first memory comprising several portions of one or more pages each, this memory comprising first and second ports for access at the same time, respectively read and write, to two pages of distinct portions of the memory; and a control circuit adapted to perform write operations in pages of the memory, each write operation in a page of the memory comprising a step of reading an old data in this page via the first port, followed a step of writing a new data in this page via the second port taking into account the old data. According to one embodiment, the first memory is a resistive memory.
    [0004] According to one embodiment, the system further comprises a second memory, and, for performing first and second consecutive write operations in first and second pages of distinct portions of the first memory, the control circuit is adapted to, successively: read a first old data in the first page via the first port and write this data in the second memory; read a second old data in the second page via the first port and write this data in the second memory, and, simultaneously, write a first new data in the first page via the second port taking into account the B12956 - DD14847ST 4 first old given; and write a second new data in the second page via the second port taking into account the second old data. According to one embodiment, the second memory is an SRAM. According to one embodiment, the second memory contains a table comprising a number of lines equal to the number of pages of a portion of the first memory. According to one embodiment, each line of the second memory contains a first field adapted to contain an address of a portion of the first memory, a second field adapted to contain the content of a page of the first memory, a third field adapted to contain the contents of a page of the first memory, and a fourth field adapted to contain a bit of validity. According to one embodiment, each page of the first memory comprises several elementary data storage cells, and the control circuit is adapted to each write operation of a new datum in a page 20 of the first memory, when of the write step of this write operation, to compare the old data read in the page and the new data, and to write only in the cells of the page whose content must be modified to record the new data . According to one embodiment, each page of the first memory comprises at least first and second words each comprising one or more elementary data storage cells, and a set of one or more elementary data storage cells adapted to contain an error correction code protecting data contained in the first and second words. According to one embodiment, the control circuit is adapted, at each write operation in a page of the memory, to read in the page an old data item comprising the contents of the first and second words of the page and the code of B12956 - DD14847ST correction of errors protecting them, to correct if necessary the contents of the first and second words using the error correction code, to replace in the old data the contents of at least one of the first and second words by the new user data, to recalculate the error correction code to account for the new user data, then to write in the page the new data and the new error correction code. BRIEF DESCRIPTION OF THE DRAWINGS These features and their advantages, as well as others, will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying figures in which: Figure 1 schematically shows and partially an example of an embodiment of a system having a memory and means for performing write operations in the memory; FIG. 2 represents in more detail an embodiment of the memory of the system of FIG. 1; And FIG. 3 shows another exemplary embodiment of the memory of the system of FIG. 1. DETAILED DESCRIPTION For the sake of clarity, the same elements have been designated with the same references in the various figures. In addition, only the elements useful for understanding the described embodiments have been shown and will be detailed later. FIG. 1 schematically and partially shows an example of an embodiment of a system 100 comprising a memory 101, for example a resistive memory, and means for performing write operations in the memory 101. The memory 101 comprises a plurality of elementary cells (not shown) distributed in several portions B12956 - DD14847ST 6 or segments Si, with i integer ranging from 1 to s and s integer greater than 1. The elementary cells of each Si portion are distributed in one or more pages Pi, j, with j integer ranging from 1 to p and p integer greater than or equal to 1, of several cells each. In this example, a page corresponds to the largest amount of readable or write addressable memory in a single memory cycle, i.e., the largest group of elementary cells that can be read or written in a single cycle. in the memory.
    [0005] As a nonlimiting illustrative example, the memory 101 is a 1-gigabyte memory organized in 512 segments, each segment comprising 4096 pages of 64 bytes each. According to one aspect of the embodiment of FIG. 1, the memory 101 has an architecture allowing simultaneous read access to a first page of the memory and writing to a second page of the memory, provided that the first and second pages belong to separate Si portions of the memory. In this example, the memory 101 includes a first access port PTR allowing read access to the pages of the memory, and a second access port PTW allowing write access to the pages of the memory, the ports PTR. and PTW allowing to address simultaneously, that is to say during the same memory cycle, two pages If separate portions of the memory. At each operating cycle of the memory 101, it is thus possible to read in a page of a portion of the memory 101 via the port PTR, and to write in a page of another portion of the memory 101 via the PTW port. The system 100 further comprises a control circuit 103 (CTRL), for example comprising a microcontroller or a specific circuit using for example a finite state machine. The circuit 103 is adapted to receive memory access requests from a user (USER) of the memory, and to respond to these requests, by accessing pages Pi, j for the memory via its ports. PTR and PTW access. The B12956 - DD14847ST 7 circuit 103 is particularly adapted to perform write operations in pages of the memory, each write operation in a page Pi, j of the memory comprising a step of reading an old data contained in the page Pi, j via the port PTR, followed by a step of writing a new data in the page Pi, j via the port PTW taking into account the old data. For example, during a write operation in a page Pi, j, the circuit 103 begins by reading the old data contained in the page Pi, j, compares this old data with the new data provided by the user, then writes in the page Pi, j only the bits of the new data that differ from the bits of the old data. For this, by way of nonlimiting example, an EXCLUSIVE OR can be realized bit by bit between the old data and the new data. For each bit of the page addressed, if the result of the EXCLUSIVE OR is a 1, it means that the value that one wishes to write is different from the value already contained at the same position in the page. In this case, the write amplifier of the corresponding cell is controlled to write the new value in the cell. If, on the contrary, the result of the EXCLUSIVE OR is a 0, it means that the value that one wishes to write is identical to the value already contained at the same position in the page. In this case, the write amplifier of the corresponding cell is blocked or deactivated, and the write operation is not performed. In practice, the new data provided by the user can be applied to a data entry of the memory, and the result of the EXCLUSIVE OR between the old data and the new data can be applied at the same time to a control input of the data. memory writing amplifiers. This makes it possible to suppress redundant cell writes and thus to increase the lifetime of the memory and / or to reduce its power consumption, in particular if the memory is a memory that wears out more when it is written than when it is read, and / or if the memory consumes more power when it is written than when it is read. An advantage of the system 100 of FIG. 1 results from the fact that the steps of reading and writing the same write operation are carried out via distinct PTR and PTW ports of the memory. This makes it possible, from the point of view of the user, to reduce the access time to the data of the memory compared to existing systems. Indeed, when a write operation required by the user is performed by the control circuit 103, the circuit 103 can: during a first memory cycle, perform the step of reading the write operation via the PTR port and perform, via the PTW port, a step of writing another operation, for example a step of writing a previous write operation; and during a second memory cycle, perform the step of writing the write operation via the PTW port and perform, via the PTR port, a step of reading another operation, for example a step of reading a next write operation. Thus, although a write operation is performed in two memory cycles, the system 100 of FIG. 1 makes it possible, from the point of view of the user, to process a memory cycle write operation, the duration of the memory operation. memory cycle being conditioned by the longest time of reading and writing in the memory. In the example of FIG. 1, in order to manage the consecutive user accesses to the same portion Si of the memory 101, the system 100 comprises, in addition to the memory 101, a buffer memory 105 in which the control circuit 103 can read and write. The memory 105 is adapted to store a table of p lines Lj, with j integer ranging from 1 to p and p integer greater than or equal to 1, that is to say a table comprising a number of lines Lj equal to the number of pages Pi, j in each segment Si of the memory 101. In this example, each line Lj of the buffer memory 105 comprises a first subset of B12956 - DD14847ST 9 bits or AS field that can contain an address of a segment of the 101, a second subset of bits or field DATAI, for example of the size of a page Pi, j of the memory 101, which may contain a first data item read or to be written in a page of the memory 101, a third subset of bits or field DATA2, for example the size of a page Pi, j of the memory 101, which can contain a second piece of data read or to be written in a page of the memory 101, and a bit or field of validity V indicating whether or not the fields AS, DATA 'and DATA2 of the line P'j contain values s valid. The memory 105 may be a different technology memory from the memory 101, for example a memory having read and write access times shorter than the memory 101, for example an SRAM ("Static 15") memory. Random Access Memory "- static random access memory. By way of example, the memory 105 and the control circuit 103 on the one hand, and the memory 101 on the other hand, can be clocked by clocks of different frequencies. In the example shown, the memory 105 and the control circuit 103 receive a first clock signal clk1 of a first frequency, and the memory 101 receives a second clock signal clk2 of lower frequency than the first signal clk1, the signal clk2 being generated by the control circuit 103 by frequency division of the signal clkl. Alternatively, the fast clock signal clk1 may be generated by frequency multiplication of the slow clock signal clk2 used to clock the memory 101, for example by means of a phase locked loop. A non-limiting example of operation of the system 100 of FIG. 1 will now be described. Upon initialization of the system 100, all the validity fields V of the buffer memory 105 are initialized to an invalid state. When a write operation in a page Pi, of the memory 101 is required by the user, the control circuit B12956 - DD14847ST 103 consults the row table Lj of the buffer memory 105, at the address page of the user request, that is to say, it looks at the line Lj of the same rank j in the memory table 105 as the page Pi, j in the segment Si.
    [0006] If the validity field V of the line Lj is in a valid state, the control circuit 103 checks whether the segment address field AS of the line Lj contains the same segment address as the user request. If the validity field V of the line Lj is at a valid state and the AS field of the line Lj contains a different segment address than the user request, the control circuit 103 determines, taking into account the data. contained in the fields DATA '(old data) and DATA2 (new data) of the line Lj, the data that should be written in the page PiT, j of the memory 101 whose address is defined by the address segment contained in the AS field of the data Lj and by the page address of the user request, then writes this data in the page PiT, j via the port PTW (i 'being the rank of the segment whose address is contained in the AS 20 field of line Lj). In the case where the system 100 implements the abovementioned wear reduction mechanism, the data written in the page PiT, j is the data contained in the field DATA2 without modification, but only the bits of this data which differ from each other. the data contained in the field DATA 'are actually written. For this, the control signal to be applied to the write amplifiers of the memory 101 is calculated by executing an EXCLUSIVE OR bit by bit between the data contained in the fields DATA 'and DATA2. The result of the EXCLUSIVE OR is sent to the memory 101 at the same time as the data DATA2. In parallel with this writing step, the control circuit 103 reads the data contained in the page Pi, j of the memory 101, writes this data in the field DATA 'of the line 35 Lj, writes the new user data (contained in the B12956 - DD14847ST 11 user request) in the DATA2 field of the line Lj, and writes the segment address of the user request in the AS field of the line Lj. If the validity field V of the line Lj is at a valid state and the AS field of the line Lj contains the same segment address as the user request, the control circuit 103 writes directly to the DATA2 field of the line Lj, the new user data to write in the page Pi, j. In this case, the processing of the write operation does not include a step of reading an old datum in the page Pi, j of the memory 101, this old datum already being contained in the DATAI field of the line Lj. If the validity field V of the line Lj is in an invalid state, the control circuit 103 reads the data contained in the page Pi, j of the memory 101, writes this datum in the field DATAI of the line Lj, writes the new user data in the DATA2 field of the line Lj, writes the segment address of the user request in the AS field of the line Lj, and sets the validity field V of the data of the line Lj to the valid state . It will be noted that in this example, the step of determining the data to be written in a page Pi, j of the memory, taking into account the old data contained in this page and the new data provided by the user. , is performed just before the step of writing the new data in page Pi, j. Alternatively, this step can be performed further upstream, just after reading the old data contained in the page Pi, j. In particular, in the aforementioned example of operation, instead of writing the new user data in the field DATA2 of the line Lj (after having read the old data contained in the page Pi, j), it is possible to combine the old data and the new data and directly write the result of this combination in the field DATA2 of the line Lj, or write the new data and the result of the combination (for example the result of the EXCLUSIVE OR between the old and the new datum) in the field B12956 - DD14847ST 12 DATA2 in the case where the abovementioned wear reduction mechanism is implemented. Note that in this case, in each line Lj of the buffer memory 105, the field DATA2 can be the size of two pages Pi, j of the memory 101, so as to be able to contain both a new user data to be written. in a page of the memory, and the result of the combination between this new data and an old data, for example the result of the EXCLUSIVE OR between this new data and an old data. This variant embodiment is particularly advantageous when the steps of writing in the memory 101 are longer than the reading steps in the memory 101. When a reading operation in a page Pi, j of the memory 101 is required by the user, the control circuit 103 consults the rows table Lj of the buffer memory 105, at the address page of the user request, that is to say that he consults the line Lj of the same rank j in the table of the memory 105 as the page Pi, j in the segment Si. If the validity field V of the line Lj is at a valid state, and if the segment address field AS of the line Lj contains the same segment address as the user request, it means that the data targeted by the user is in the line Lj of the buffer. The control circuit 103 then determines, taking into account where appropriate data contained in the fields DATA 'and DATA2 of the line Lj, the data to be sent back to the user and transmits this data to the user. In the aforementioned example of application to a mechanism for reducing wear and / or consumption of the memory, the data returned to the user by the circuit 103 can be directly the data contained in the DATA2 field of FIG. line Lj. If the validity field V of line Lj is at a valid state, and if the segment address field AS of line Lj does not contain the same segment address as the request B12956 - DD14847ST 13 user, or if the validity field V of the line Lj is at an invalid state, the control circuit 103 reads the targeted data directly into the memory 101 and does not write to the buffer memory 105.
    [0007] As a variant, it is also possible, at each read operation, to store the data read in the buffer memory 105 so that this data can subsequently be read again more quickly and with a lower power consumption in the case where the pages of the memory are, statistically, called to be read more often than they are written. For this, a second bit or validity field V '(not shown) is introduced into each line Lj of the buffer memory 105, which is initially in an invalid state and is set to a valid state when a new data item is to be written. from a user request is written in the DATA2 field of line Lj. When a read operation in a page Pi, j of the memory 101 is required by the user, the control circuit 103 consults the row table Lj of the buffer memory 105, at the page address of the user request. . If the validity field V of the line Lj is in the valid state, and if the segment address field AS of the line Lj contains the same segment address as the user request, the control circuit 103 checks whether the validity field V 'of the line Lj is in the valid state. If the field V 'of the line Lj is in the valid state, the control circuit 103 proceeds as before, that is to say that it determines, taking into account the data contained in the fields DATAI and DATA2 line Lj, the data to be returned to the user and provides this data to the user. If the field V 'of the line Lj is in the invalid state, the control circuit 103 directly supplies the user with the data contained in the DATAI field of the line Lj, without taking into account the data contained in FIG. in the DATA2 field of the line L. If the validity field V of the line Lj is in the valid state, and if the segment address field AS of the line Lj contains a segment address different from the address of segment of the user request, the control circuit 103 checks whether the validity field V 'of the line Lj is in the valid state. If the field V 'of the line Lj is in the valid state, it means that a write step in the memory 101 is waiting. The control circuit 103 then determines, taking into account the data contained in the fields DATA 'and DATA2 of the line Lj, the data to be written in the page PiT, j of the memory 101 whose address is defined by the address segment contained in the AS field of the line Lj and by the page address of the user request, then writes this data in the page PiT, j via the PTW port. In parallel with this writing step, the control circuit 103 reads the data contained in the page Pi, j of the memory 101, writes this data in the DATA field of the line Lj, provides this data to the user, and sets the field V 'of the line Lj to the invalid state. If the field V 'of the line Lj is in the invalid state, the control circuit 103 reads the data contained in the page Pi, j of the memory 101, writes this data in the field DATAI of the line Lj, provides this given to the user, and leaves the field V 'of the line Lj to the invalid state. If the field V of the line Lj is in the invalid state, the control circuit 103 reads the data contained in the page Pi, j of the memory 101, writes this data in the field DATA 'of the line Lj, provides this given to the user, and sets the field V of the line Lj to the valid state and the field V 'of the line Lj to the invalid state. When a write operation in a page P1, j of the memory 101 is required by the user, the control circuit 103 performs the operations described in the above example B12956 - DD14847ST and additionally sets the V bit. 'from the line Lj to the valid state. In the case where the buffer memory 105 is a volatile memory and where the main memory 101 is a non-volatile memory, mechanisms can be provided to avoid, at the power off of the system, a possible loss of data that would be recorded in the memory. buffer 105 but not yet written in the main memory 101. For example, before a power failure, the user system can send a stop instruction to the control circuit 103. The control circuit 103 can then browse all rows of the buffer 105 and perform the write operations in the memory 101 that have not yet been performed. In this case, all the validity fields V or V and V 'of the buffer memory can be initialized in the invalid state each time the system is powered up. Alternatively, buffer memory 105 may be coupled to additional non-volatile memory, not shown, in which all data in buffer memory 105 is transferred before the system is powered down. This additional nonvolatile memory may or may not be included in the main memory 101. When the system is powered back up, the data of the additional nonvolatile memory may be retransferred to the buffer memory 105. By way of example, each cell storage buffer 105 may be coupled to a nonvolatile storage element so that the contents of the memory 105 can be fully transferred to the nonvolatile storage elements in a single cycle before powering off the system . The validity fields V or V and V 'of the buffer memory 105 are then for example initialized in the invalid state only at the first power up of the system.
    [0008] B12956 - DD14847ST It will be noted that the described embodiments are not limited to the particular example mentioned above of use of the system of FIG. 1 for the implementation of a mechanism for reducing wear and / or the consumption of the memory 101, in which each write operation of a new piece of data in the memory 101 comprises a step of reading an old piece of data in the memory, followed by a step of writing to the same address of the only memory cells whose state must be modified to save the new data.
    [0009] More generally, the system 100 of FIG. 1 is compatible with any application in which an operation for writing a new datum in a memory, resistive or of another type, for example a capacitive memory, comprises a reading step. of an old datum in the memory, 15 followed by a step of writing the new datum, to the same address of the memory, taking into account the old datum. As an example of application, consider the case where, in each page Pi, j of the memory 101, the elementary cells of the page are divided into several words Mi, j, k 20 (with k integer ranging from 1 at m and m integer greater than 1) of several cells each, for example 32-bit words, and other elementary cells of the memory are assigned to the storage of error correction codes, for example Hamming codes, to protect the data contained in the words of the page against a possible failure of a cell of the page, for example due to alpha particles. In this example, the same error correction code is assigned to the protection of several words of the page (two or more). Subsequently, for simplicity, we consider the case where each page Pi, j contains a single error correction code protecting all the words of the page. Those skilled in the art will, however, be able to adapt the operation described in the case where a page contains several distinct groups of at least two words each, and an error correction code per group.
    [0010] B12956 - DD14847ST 17 When, during an operation to write a new piece of data in a page, the user wishes to modify only part of the words of the page, for example a single word of the page, one could consider write the new user data in this word of the page in a single write step, disabling the write amplifiers of the other cells of the page to not affect their content. However, this solution does not make it possible to update the error code of the page to take account of the new written data. Thus, during a write operation, it is possible to read the old content of the page, to correct, if necessary this content using the error correction code of the page, to modify this content inserting the new user data therein and modifying the correcting code to account for the new user data, then writing the new content in the page. Each operation of writing a new datum in a page thus comprises a step of reading an old datum in the page, followed by a step of writing the new datum in the page taking into account the old data. It will therefore be understood that using the system 100 of FIG. 1 to perform such write operations advantageously makes it possible, from the point of view of the user, to reduce the access times to the data contained in the memory. FIG. 2 schematically and partially shows an exemplary embodiment of a memory 101 compatible with the system of FIG. 1. In this example, the memory 101 comprises a plurality of memory portions 201i, with i integer ranging from 1 at s and s integer greater than 1, of several pages (not visible in Figure 2) each. In this example, each portion 201i of the memory 101 corresponds to a segment Si 35 of the memory.
    [0011] The memory 101 includes a first access port PTR allowing read access to the pages of the memory 101, and a second access port PTW allowing write access to the pages of the memory 101, the PTR and PTW ports allowing simultaneous access to any two pages of the memory 101, provided that these pages belong to separate portions 201 i of the memory. By access port is meant here a set of input and / or output terminals adapted to receive an address signal, to receive an input data signal, and / or to provide an output data signal. . An access port may in particular comprise a multi-bit address input adapted to receive an address signal, a multi-bit data input adapted to receive a data signal to be written into the memory, and / or a multi-bit data output adapted to provide a data signal read from the memory. The data entry and the data output may possibly be confused. In the example of FIG. 2, the access port PTR of the memory 101 includes an address entry adR adapted to receive an address of a page to be read in the memory, and a data output dR adapted to transmit. the content of a page read in the memory, and the access port PTW includes an address entry adW adapted to receive an address of a page to be written in the memory, and a data entry dW adapted to receive a content to write in a page of memory. In the case where a wear reduction mechanism of the aforementioned type is implemented, the write access port PTW may further comprise a cmdw input (not shown) for controlling the memory write amplifiers, for example. example of the same size as the data input dW, this control input being adapted to receive a control data of the write amplifiers, for example the result of the EXCLUSIVE OR between a new user data to be written in the memory via the dW input and an old data read at the same address in the memory.
    [0012] B12956 - DD14847ST 19 In this example, each memory portion 201i comprises an input CS adapted to receive an activation / deactivation signal of the portion 201i, an R / W input adapted to receive a read or write command signal. of the portion 201i, an input CK adapted to receive a clock signal, an input A adapted to receive an address of a page of the memory portion 201i, a din input adapted to receive data (the size of one page) to be written in the address page A of the memory portion 201i, and an output 10 dout adapted to provide a piece of data (of the size of a page) read in the address page A of the portion of the memory. memory 201i. In this example, each portion 201i of the memory 101 has its activation input CS connected to the output of an OR gate 203i with two inputs a and b, its R / W operating mode control input connected to the input. input b of the OR gate 203i, and its din data input connected to the data input dW of the PTW access port. In the case where a wear reduction mechanism of the aforementioned type is implemented, each portion 201i of the memory may further comprise a cmdin input (not shown) for controlling its write amplifiers, connected to the cmdw command input (not shown) from the PTW port. The memory 101 includes a read address decode circuit DECR, comprising an input connected to the address input adR of the access port PTR of the memory and s binary outputs respectively connected to the inputs to the OR gates 2031 at 203s. The memory 101 further comprises a write address decode circuit DECW, comprising an input connected to the address input adW of the PTW access port of the memory and binary outputs connected respectively to the inputs b of the memory. OR gates 2031 to 203s. The decoder DECR is adapted to determine in which portion 201i of the memory 101 is the word addressed by the address input adR, and to apply an activation signal on the input a of the OR gate 203i connected to this 35 portion of memory. Decoder DECW is adapted to determine B12956 - DD14847ST 20 in which portion 201i of memory 101 is the word addressed by address input adW, and to apply an activation signal on input b of the door OR 203i connected to this portion of memory. Thus, decoders DECR and DECW can simultaneously activate two separate memory portions 201i. In practice, among the address bits applied to the adR and adW inputs, it is sufficient to transmit to the decoders DECR and DECW only the bits indicating the numbers of the memory portions in which the addressed pages are located. In this example, each portion 201i of the memory 101 has its addressing input A connected to the output of a multiplexer 205i from two inputs to an output. Each multiplexer 205i has a first input connected to the address input adR of the PTR port and a second input connected to the adW address input of the PTW port. In this example, each multiplexer 205i also has a selection input connected to the input b of the OR gate 203i connected to the memory portion 201i. The operation of the multiplexers 205i is such that: when a memory portion 201i is activated by the decoder DECR, the address supplied by the multiplexer 205i on the input A of the memory portion 201i is that transmitted by the input d adR address; and when a memory portion 201i is activated by the decoder DECW, the address provided by the multiplexer 205i on the input A of the memory portion 201i is that transmitted by the address entry adW. In practice, among the address bits transmitted by the address inputs adR and adW, it is sufficient to transmit to the multiplexers 205i only the bits defining the position of the page addressed inside the memory portion 201i in which she is. In this example, the memory 101 further comprises a multiplexer MUX of s inputs to an output, the output of which is connected to the data output dR of the port PTR. The inputs 35 of the multiplexer MUX are respectively connected to the outputs B12956 - DD14847ST 21 given all portions 201i of the memory 101. In this example, the multiplexer MUX has a control or selection input connected to the input of adR address of the access port PTR of the memory. The operation of the multiplexer MUX is such that, when a memory portion 201i is activated by the decoder DECR, the data supplied by the multiplexer MUX on the data output dR is that supplied by the memory portion 201i at its output End. In practice, among the address bits applied to the address input adR, it is sufficient to transmit to the multiplexer MUX only the bits indicating the numbers of the memory portions in which the pages addressed are located. In this example, the inputs CK of the different portions 201i of the memory 101 are connected to the same node clk 15 for applying a clock signal. By way of example, the different portions 201i of the memory 101, and the elements 203i, 205i, DECR, DECW and MUX can be integrated in the same semiconductor chip. An advantage of the memory 101 is that it allows simultaneous read and write accesses to words distinct from the memory, while having a footprint barely larger than that of a single-port memory. FIG. 3 schematically and partially shows another exemplary embodiment of a memory 101 compatible with the system of FIG. 1. The memory 101 of FIG. 3 comprises many elements common to the memory 101 of FIG. These elements will not be described again in detail below. In the following, only the differences between the memories of Figures 2 and 3 will be highlighted. The memory 101 of FIG. 3 comprises, as in the example of FIG. 2, a first read access port PTR comprising an address entry adR of a page to be read, and an output dR of data read. in one page, and a second PTW access port having an address input adW of a page to be written, a dW input of data to be written to a page, and, if appropriate, an entry B12956 - DD14847ST 22 an entry cmdw (not shown) for controlling the memory write amplifiers. In addition, the memory 101 of FIG. 3 comprises, as in the example of FIG. 2, a plurality of memory portions 201i, with i integer ranging from 1 to s and s integer greater than 1, identical or similar to those of the memory of FIG. 2. In the memory 101 of FIG. 3, the selection mechanisms of the portions 201i, via the decoders DECR and DECW and the OR gates 203i, the page addressing mechanisms in the portions 201i, via the multiplexers 205i, and the input data delivery mechanisms to the portions 201i, via the write input dW, are identical or similar to those in the memory of FIG. 2, and will not be described again.
    [0013] The memory 101 of FIG. 3 differs from the memory of FIG. 2 mainly by the circuits used to multiplex the data outputs dout of the different memory portions 201i, towards the data output dR of the PTR port. In the memory 101 of FIG. 3, each portion 201i of the memory has its output connected by a switch Sli to an output data bus 301 connected to the data output dR of the memory. In this example, each switch Sli has a control node connected to the input a of the OR gate 203i connected to the memory portion 201i. When a memory portion 201i is activated in reading by the decoder DECR, the data output dout of the memory portion 201i is connected to the data output dR of the memory by closing the switch Sli. Thus, in the memory 101 of FIG. 3, the multiplexer MUX of FIG. 2 is replaced by a distributed multiplexing circuit distributed at the level of the different memory portions 201i. The switches Sli are for example made by MOS transistors. Each switch Sli is for example disposed in the vicinity of the memory portion 201i of the same rank. In addition, the output data bus 301 preferably passes near the different memory portions 201i.
    [0014] B12956 - DD14847ST 23 An advantage of the variant embodiment of FIG. 3 is that it makes it possible, compared to the example of FIG. 2, to reduce the number of cables or tracks connecting the outputs dout of the different memory portions 201i. at the data output dR of the memory (and thus to reduce the area and the cost of the memory). Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art.
    [0015] In particular, the embodiments described are not limited to the particular examples described with reference to FIGS. 2 and 3 of memories allowing simultaneous read and write accesses to separate pages of the memory. The embodiments described are in particular compatible with a dual port memory allowing simultaneous read and write access to any two pages of the memory (which corresponds to the case where each segment of the memory comprises a single page). In this case, the realization of the system 100 of FIG. 1 is simplified, in particular because the buffer memory 105 of FIG. 1 can be reduced to a register of a single line L1. In this case, the AS segment address field of line L1 may contain the entire page address of the user request. In addition, the embodiments described above are not limited to the examples of means and mechanisms described in connection with FIG. 1 for managing the consecutive user accesses to the same segment Si of the memory.
    权利要求:
    Claims (9)
    [0001]
    REVENDICATIONS1. System (100) comprising: a first memory (101) comprising several portions (Si, 201i) of one or more pages (Pi, j) each, this memory (101) comprising first (PTR) and second (PTW) ports enabling two pages (Pi, j) of distinct portions (Si, 201i) of the memory (101) to be read and read at the same time; and a control circuit (103) adapted to perform write operations in pages (Pi, j) of the memory (101), each write operation in a page (Pi, j) of the memory (101) ) comprising a step of reading an old data in this page (Pi, j) via the first port (PTR), followed by a step of writing a new data in this page (Pi, j) via the second port (PTW) taking into account the old data. 15
    [0002]
    The system (100) of claim 1, wherein the first memory (101) is a resistive memory.
    [0003]
    The system (100) of claim 1 or 2, further comprising a second memory (105), wherein for performing first and second consecutive write operations in first and second pages (Pi, j) of Portions (Si, 201i) distinct from the first memory (101), the control circuit (103) is adapted to, successively: read a first old data in the first page via the first port (PTR) and write this data in the Second memory (105); read a second old data in the second page via the first port (PTR) and write this data in the second memory (105), and simultaneously write a first new data in the first page via the second port (PTW) 30 in taking into account the first old data; and write a second new data item in the second page via the second port (PTW) taking into account the second old data. B12956 - DD14847ST 25
    [0004]
    The system (100) of claim 3, wherein the second memory is an SRAM.
    [0005]
    The system (100) of claim 3 or 4, wherein the second memory (105) contains a table having a number (m) of lines (Lb) equal to the number (m) of pages (Pi, j) of a portion (Si, 201i) of the first memory (101).
    [0006]
    The system (100) of claim 5, wherein each line (Lb) of the second memory (105) contains a first field (AS) adapted to contain an address of a portion (Si, 201i) of the first memory, a second field (DAMA ') adapted to contain the content of a page (Pi, j) of the first memory (101), a third field (DATA2) adapted to contain the content of a page (Pi, j ) of the first memory (101), and a fourth field (V) adapted to contain a validity bit. 15
    [0007]
    The system (100) according to any one of claims 1 to 6, wherein each page (Pi, j) of the first memory (101) comprises a plurality of elementary data storage cells, and wherein the control circuit ( 103) is adapted, at each write operation of a new datum in a page (Pi, j) of the first memory (101), during the writing step of this write operation, to be compared the old data read in the page (Pi, j) and the new data, and to write only in the cells of the page (Pi, j) whose contents must be modified to record the new data.
    [0008]
    The system (100) according to any one of claims 1 to 6, wherein each page (Pi, j) of the first memory (101) comprises at least first and second words each having one or more elementary cells of 30. storing data, and a set of one or more elementary data storage cells adapted to contain an error correction code protecting data contained in the first and second words.
    [0009]
    The system (100) of claim 8, wherein the control circuit (103) is adapted, at each write operation, to a page (Pi, j) of the memory (101), to read in the page (Pi, j) an old data item containing the contents of the first and second words of the page (Pi, j) and the error correction code protecting them, to correct if necessary the contents of the first and second words using the error correction code, to replace in the old data the content of at least one of the first and second words by the new user data, to recalculate the error correction code to take account of the new user data, then write in the page (Pi, j) the new data and the new error correction code.
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    同族专利:
    公开号 | 公开日
    WO2015086845A1|2015-06-18|
    FR3015103B1|2017-05-26|
    US20160314837A1|2016-10-27|
    US9543012B2|2017-01-10|
    EP3080812A1|2016-10-19|
    EP3080812B1|2018-08-01|
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    法律状态:
    2015-12-23| PLFP| Fee payment|Year of fee payment: 3 |
    2016-12-29| PLFP| Fee payment|Year of fee payment: 4 |
    2018-01-02| PLFP| Fee payment|Year of fee payment: 5 |
    2019-09-27| ST| Notification of lapse|Effective date: 20190906 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1362469A|FR3015103B1|2013-12-12|2013-12-12|DATA WRITING SYSTEM IN A MEMORY|FR1362469A| FR3015103B1|2013-12-12|2013-12-12|DATA WRITING SYSTEM IN A MEMORY|
    US15/103,274| US9543012B2|2013-12-12|2014-12-12|System for writing data in a memory|
    EP14812468.8A| EP3080812B1|2013-12-12|2014-12-12|Memory data writing circuit|
    PCT/EP2014/077651| WO2015086845A1|2013-12-12|2014-12-12|System for writing data in a memory|
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