• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Field Effect Transistor (MOSFET) and its manufacturing procedure. The invention encompasses a high power diamond metal-oxide-field effect semiconductor (MOSFET) transistor as well as the manufacturing method by selective/lateral growth. The combination of the growth on the substrate of the first layers in a standard vertical manner with the use of selective lateral growth on the engraved table structure gives the MOSFET device a novel three-dimensional structure. This avoids the edge effects of metal contacts and high internal electric fields, improves the crystalline quality of the diamond and reduces the time, costs and size of the device, giving it, in turn, greater versatility for its implementation on more complex architectures. (Machine-translation by Google Translate, not legally binding)
    公开号:ES2763702A1
    申请号:ES201831162
    申请日:2018-11-29
    公开日:2020-05-29
    发明作者:Vieira Fernando Lloret；Gay Daniel Araujo；Philippe Godignon；David Eon；Julien Pernot；Etienne Bustarret
    申请人:Consejo Superior de Investigaciones Cientificas CSIC；Universidad de Cadiz；
    IPC主号:
    专利说明:

    [0002] FIELD EFFECT TRANSISTOR (MOSFET) AND MANUFACTURING PROCEDURE THEREOF
    [0004] TECHNICAL SECTOR
    [0006] The invention falls within the industrial sector of power electronics and microelectronics.
    [0008] STATE OF THE ART
    [0010] Semiconductor silicon power devices have guided the development of power electronics allowing their continuous improvement with a large number of implications in the industry, especially in the transmission and distribution of large-scale electrical energy (T&D). Great efforts have recently been made in the development of SiC devices, giving SiC its application niche. However, the requirements of the new power electronics exceed the physical limits of both SiC and silicon. Therefore, the new generation of power devices must be developed in a new semiconductor material. In this sense, synthetic diamond clearly expands the limits of technology in Silicon and SiC thanks to its spectacular electrical and thermal properties. Its resistance to dielectric breakdown is three times higher than that of SiC and more than thirty times better than that of Si. Furthermore, the mobility of carriers in diamond is very high for both electrons and holes and its thermal conductivity is unmatched.
    [0012] In the current context, the Si semiconductor power switches used in 90% of the power applications market are MOS gate control devices (VDMOS, IGTB). Furthermore, thyristor based structures are still widely used for high frequency and voltage applications mainly due to the lack of equivalent MOS-controlled devices. This is something that SiC, with breakdown voltages less than 10kV, and Diamond or Ga2O3, with breakdown voltages greater than 10kV, could solve.
    [0014] The biggest advantage of MOS-controlled switches is the low impulse energy required to switch the circuit and the simplification in the circuit that this associated. Furthermore, devices controlled by MOS gates do not have a current flow when the gate is not normally-off, thus preventing short circuits in the electrical load in case of power failure.
    [0016] Diamond is theoretically the ideal semiconductor for the manufacture of single-pole power semiconductors. However, the starting material is expensive and the size of the wafers is really small (2.25 cm2 maximum). Furthermore, the density of defects in substrates is still high and varies greatly from one sample to another, even coming from the same batch from a single supplier. The surface quality also varies greatly from one substrate to another and it is usual that they require extra polishing. To these drawbacks inherent in the starting material, we must add the problems due to technological processing, more specifically those related to local doping and interface passivation.
    [0018] The commercial availability of electronic grade monocrystalline diamond became a reality with the growth of chemical vapor deposition (CVD) diamond in the 1990s. Thus, diamond substrates up to one inch are available today and up to two inches will be available soon. Recently, Shin-Etsu and TIT published a high performance in a diamond Schottky diode manufactured on a silicon based diamond substrate and in March 2016, the Namiki group (Japanese industrial group) announced the marketing of the first long diameter diamond substrate grown by heteroepitaxy. This proves that it is possible to have large area wafers with electronic quality. The price of these substrates in high volume purchases should not vary from that of other materials with long bandwidth prohibition (WBG), such as SiC. However, diamond electronic devices are still under investigation and have not resulted in commercial products. The main reason for this is the very poor performance they offer caused by a very faulty diamond / metal contact interface. This problem was recently solved by the Institut Néel using a surface treatment on the diamond prior to the manufacture of the Schottky contact, thus allowing the realization of rectifiers with low active resistance (ON) and very high blocking voltage [CNRS patent: PCT / US No. 14/786130, FR No. 13/53647]. The combination of this new achievement together with recent progress in wafer processing opens the door to the manufacture of devices that benefit from the exceptional properties of diamond.
    [0019] As a consequence of its very compact crystalline structure, diamond is a very hard material and sensitive to the generation of defects during the incorporation into its crystalline network of impurities for doping. This fact emphasizes the importance of controlling the spread of defects in the active layers. It has recently been tested how growth conditions, more specifically the molar ratio of methane to hydrogen, in chemical deposition of microwave plasma activated vapor (MPCVD) defines the preferential growth orientation [F. Lloret et al., Phys. Status Solidi A 210, 2570 (2016)]. In this way it is possible to perform selective homoepitaxial diamond growth on engraved substrates. Said selective lateral growth plays a main role allowing the in-situ manufacturing (in the same growth chamber) of 3D architectures, minimizing the photolithography process and controlling the generation of dislocations by allowing growth on optimal planes in this regard [M.P. Alegre et al., Appl. Phys. Lett. 105, 1731303 (2014)].
    [0021] These properties offer the possibility of electronic devices with far superior performance in terms of high frequency, energy efficiency, power density properties, losses, cooling and robustness in polluted environments [D. Chamund et al., Proceedings of the 7th WSEAS Inst.Conf. Electronics, Hardware, Wireless and Optical Communications, Cambridge, UK, ISNB 973-960-6766-40-4, ISSN 1790-5117, February 2008].
    [0023] Currently, some authors have echoed the advances that this type of device represents. This is the case of patent EP2884525A1, which refers to the creation of a FET device on a diamond substrate, or WO2010001705A1, which covers the formation of a diamond pn junction. In both cases CVD lateral diamond growth is used to design the 3D structures. Said lateral growth consists of selective growth carried out in different directions from the orientation of the substrate. However, it has been shown that the curvature of the field lines for horizontal and pseudo-vertical designs, such as the ones referenced, induce high electric fields inside, mainly at the edges and surroundings of the door contact [Thesis by Aurelien Marechal, Université Grenoble-Alpes, 2015]. However, a design that includes a highly doped first layer at the bottom that acts as a drain allows completely vertical behavior without curvature of the field lines and, therefore, without generating abnormally high electric fields.
    [0024] DESCRIPTION OF THE INVENTION
    [0026] The present invention corresponds to a completely new MOSFET structure, based on the combination of standard processing with selective regrowth of epilayers (epitaxially grown layers). Entirely designed in monocrystalline diamond, this structure solves the different technological problems existing until now in the manufacture of commercial diamond devices. Among them: selective growth of n-type and p-type doped layers, termination design and passivation for high voltage capacity. This is achieved by improving processing and technological manufacturing. On the one hand, the architecture has been designed so that the clean room processing steps are minimized. The structure comprises a series of layers and does not contain acute angles for the field lines, thus avoiding the generation of areas with intense electric fields inside the device. In addition, lateral growth not only prevents the generation of new defects, but deflects those that may exist in a way that avoids short-circuiting the door and drain, thus acting as a filter for dislocations. Said structure also allows a long arbitrary field and, as has been anticipated, substantially reduces the number of photolithography processes. In addition, the combination of faces oriented in different directions allows optimization of doping and growth rates, improving the efficiency of the device and reducing manufacturing times.
    [0028] On the other hand, the use of CVD techniques for growth allows a high crystalline quality with relatively low deposition times. The device has been designed to minimize cleanroom steps by achieving three-dimensional structure with only two engraving stages. An initial stage in which lateral faces are generated on which to grow, and a second stage for the manufacture of ohmic contacts. The design of the device allows none of these engravings to be critical to the operation of the device.
    [0030] On a (100) -oriented electronically grade diamond substrate and suitably polished, a first layer is grown by CVD which is highly boron-doped diamond, p +, thicker than 50nm. On this first layer, it is deposited between 5 and 20pm of diamond with very low boron doped, p "; in such a way that a second layer is defined
    [0031] After this first step, the second layer is engraved once it has been deposited, p ", using ionic engraving techniques; to generate table- type structures with a depth between 200 nm and 15 pm, depending on the thickness of this second layer .
    [0033] A third layer is selectively grown on these structures, which is made of diamond preferably doped with phosphorus (n-type doped) so that it covers the engraved height (its thickness therefore being dependent on the chosen engraving depth). Thanks to the three-dimensional structure of the substrate and the preferential growth of the n-type diamond on the lateral faces, that is, on <111> and proximal orientations, selective growth is achieved without the need for the use of masks or other techniques. On this third layer, of n-type doped diamond, a fourth layer is deposited that will be thinner than said third layer and of p + doped semiconductor diamond. As it was advanced in the state of the art, by using an adequate methane / hydrogen ratio, selective growth is achieved by MPCVD, thus achieving that the fourth layer, of p + doped semiconductor diamond, is only deposited on the lateral faces type n doped.
    [0035] Before manufacturing the contacts, a second and last engraving is made at the ends of the structure so that they reach the first deposited p + layer. The depth of this engraving will depend on the previously chosen thickness, but in any case it will be several microns. This fact, however, does not suppose a disadvantage for the device because, although the engraving was not ideal, the distance in this respect from the active layers of the MOSFET does not influence the correct operation of the device. Finally, on this final structure the contacts are manufactured.
    [0037] This design avoids the following underlying problems in today's diamond-based power devices:
    [0038] - Edge effects of metal contacts:
    [0039] - High internal electric fields: The geometry of the design reduces the curvature of the field lines, favoring a homogeneous distribution of the electric field.
    [0040] - Problems associated with engraving near active areas of the device: Engraving for the drain is carried out at a great distance from the rest of the contacts so that the usual defects associated with these long engraving periods have no effect on the behavior of the device.
    [0041] - Dislocations and "killer defecís": The reticular defects generated during the growth of the different layers are counteracted thanks to the lateral growth. Furthermore, this design provides:
    [0042] - Improvements in crystal quality: The design of the device in monocrystalline diamond ensures the absence of defects due to lattice mismatches typical of heteroepitaxial structures. Furthermore, lateral / selective growth decreases the density of crystalline defects.
    [0043] - Reduction of manufacturing times and costs. Selective and lateral growth reduces the engraving steps and the associated time and cost costs.
    [0044] - Reduction of the size of the device: the three-dimensional design allows a greater miniaturization of the system.
    [0045] - Greater design versatility: The use of selective growth opens the design to its implementation on more complex architectures.
    [0047] DESCRIPTION OF THE CONTENTS OF THE DRAWINGS
    [0049] Figure 1: Growth on a substrate (100) -oriented of electronic quality diamond and suitably polished, of a layer of doped diamond p + and of a layer of undoped diamond, p-.
    [0051] Figure 2: Partial engraving of the last layer, thus making three-dimensional table-type structures.
    [0053] Figure 3: Selective growth of n-type doped diamond layer and p + doped diamond layer.
    [0055] Figure 4 : Engraving on the ends of the structure that reach the first layer of doped diamond p +.
    [0057] Figure 5 : Manufacture of the drain, D, gate, G, and source, S contacts.
    [0059] METHOD OF CARRYING OUT THE INVENTION
    [0061] On a (100) -oriented electronically grade diamond substrate and suitably polished, a first layer, of diamond, is grown by MPCVD doping p + (1017 <[B] <1024 cm "3). This growth is followed by the deposition of undoped diamond, p" (1012 <[B] <1017cm "3) generating a second diamond layer, which is insulating diamond.An engraving process is carried out on the second layer through which three-dimensional structures are made, preferably table-type (a table-structure in electronics means that the device is raised above the substrate) .On these three-dimensional structures it grows selectively a third layer is made of doped diamond n and on it, a fourth layer is made of p + doped diamond. The architecture is finished with an engraving on the ends of the structure that reach the first p + layer. On this structure the Ohmic contacts are manufactured and Schottky.
    [0063] A manufacturing example of the device is presented in detail below: By MPCVD, a 500 nm layer of boron-doped diamond is deposited onto a monocrystalline diamond grade of electronic quality and orientation (100). The following growth conditions are used for this: methane as a precursor gas with a molar ratio of 0.5% CH4 / H2, diborane for doping with a boron-to-carbon ratio of 14000 ppm, a controlled pressure at 33 Torr during growth, a power in the plasma of 300W and a temperature on the substrate of 900 ° C. 12 pm of unintentionally doped diamond, p ", are deposited on this layer, using the following growth conditions: methane as a precursor gas with a molar ratio of 0.75% CH4 / H2, oxygen to minimize residual doping with a proportion of 0.3% O2 / H2, a controlled pressure at 33Torr during growth, a plasma power of 300W and a temperature on the substrate of 900 ° C. These two growths give rise to a structure as represented in figure 1.
    [0065] A lift-off photolithography process is carried out on the sample in which aluminum masks with rectangular geometry are drawn. By ICP engraving, rectangular table- type structures with a depth of 700 nm are manufactured (Figure 2).
    [0066] A layer of n-doped diamond approximately 800 nm thick and a final layer of doped diamond p + 200 nm are selectively grown on these structures (Figure 3). Both layers are deposited by MPCVD and using methane as the diamond precursor, the growth conditions of the first will be as follows: Phosphine for doping n with a proportion of 50% PH3 / CH4, the methane on the other hand will be in a proportion of 0.05% on hydrogen Pressure, temperature and power will be maintained at 33Torr, 900 ° C and 300 W respectively. For the second The same pressure, temperature and power conditions will be used for the layer, but the proportion of gases will be 0.1% methane on hydrogen and 20,000 ppm of boron on carbon. These low methane conditions ensure selective lateral growth in both layers.
    [0068] The architecture is finalized with ICP stapling at the ends of the structure that reach the first p + layer (Figure 4). This engraving requires great depths (15 pm) but, as it remains distant from the active layers, it is not a critical step for the correct operation of the device.
    [0070] The Ohmic and Schottky contacts are manufactured on this structure (figure 5). The ohmic contacts consist of a first deposition of titanium 30nm thick due to the good adhesion of the titanium carbide layer that forms at the interface with the diamond. 50 nm of platinum are deposited on it to avoid diffusion through contact of the 40 nm of gold that is deposited as the last layer. This gold guarantees good thermal stability (> 600 ° C) and low contact resistivity.
    [0072] For the manufacture of the MOS structure, a passivation surface treatment is first carried out, consisting of exposing the surface in an oxygen saturated vacuum to ultraviolet light (VUV technique). After this, 40 nm Aluminum is deposited by atomic layer deposition (ALD) at 380 ° C to achieve the formation of Al2O3. 50 nm of platinum and 40 nm of gold are deposited on said layer, which has the same function as those described in the section corresponding to ohmic contacts.
    [0074] The sample is annealed 30 minutes at 500 ° C to create the titanium carbide and alumina layer of the MOS.
    [0076] INDUSTRIAL APPLICATION
    [0078] The possibilities offered by the new design geometry presented in this invention makes this design and manufacturing method of great interest in any industrial sector that makes use of power electronics, especially in the energy sector due to the interest that the Diamond awakens for current converters and other devices that require working at high voltages.
    [0079] The use of devices designed and manufactured as here exposed would suppose big energetic savings and a great miniaturization of the dimensions.
    权利要求:
    Claims (10)
    [1]
    1. - Field effect transistor (MOSFET), characterized by comprising:
    a) a polished diamond oriented substrate (100)
    b) a first layer of diamond, where the diamond is p + type doped semiconductor.
    c) a second diamond layer, located on the first layer, where the diamond is p-type insulator, and which comprises on its surface a series of three-dimensional structures,
    d) a third layer, of diamond, located on the second layer, where the diamond is n-type doped semiconductor grown on the slopes second layer,
    e) a fourth layer, of diamond, located on the third layer where the diamond is p + type doped semiconductor grown laterally on the lateral face of the third layer, and
    f) engravings on the ends of all layers until the first layer is reached, with a depth up to the first layer of p + type semiconductor diamond.
    [2]
    2. - Field effect transistor (MOSFET), according to claim 1, characterized in that the substrate and layer diamond is monocrystalline diamond.
    [3]
    3. - Field effect transistor (MOSFET), according to claims 1 or 2, characterized in that the second diamond layer comprises an engraving on its surface so that it exhibits three-dimensional structures with side faces.
    [4]
    4. - Field effect transistor (MOSFET), according to any one of the preceding claims, characterized in that the first layer comprises a boron concentration in the range 1017 <[B] <1024 cm-3.
    [5]
    5. - Field effect transistor (MOSFET), according to any one of the preceding claims, characterized in that the second layer of diamond comprises a concentration of boron in the range 1012 <[B] <1017cm-3.
    [6]
    6. - Field effect transistor (MOSFET), according to any one of the preceding claims, characterized in that the contacts comprise:
    - drain contacts are located on the first p + type diamond layer,
    - source contacts are made on the last p + type diamond layer, and - door contacts located on the n type diamond layer.
    [7]
    7. - Field effect transistor (MOSFET), according to any one of the preceding claims, characterized in that the substrate (100) has a surface roughness <1 nm.
    [8]
    8. - Method of manufacturing the field effect transistor (MOSFET) according to any one of claims 1 to 7, characterized in that it comprises the following steps carried out on a polished substrate (100):
    a) perform a growth of the first diamond layer,
    b) perform a growth of the second diamond layer,
    c) make an engraving of the second diamond layer to generate the three-dimensional structures,
    d) perform lateral growth of the third diamond layer on the slopes of the three-dimensional structures,
    e) performing lateral growth of the fourth diamond layer on the third diamond layer, and
    f) make an engraving on the fourth layer in those regions outside the three-dimensional structures where the engraving has such a depth that it reaches the first grown layer.
    [9]
    9. - Procedure, according to claim 8, characterized in that the growth of the third layer is carried out laterally.
    [10]
    10. - Procedure, according to claim 8 or 9, characterized in that the growth of the fourth layer is carried out laterally.
    类似技术:
    公开号 | 公开日 | 专利标题
    JP2015099932A|2015-05-28|Semiconductor device
    KR20100110295A|2010-10-12|Semiconductor device and semiconductor device manufacturing method
    US10418475B2|2019-09-17|Diamond based current aperture vertical transistor and methods of making and using the same
    JP2016051796A|2016-04-11|Semiconductor element and manufacturing method of the same
    CN101536192A|2009-09-16|Silicon carbide semiconductor device and process for producing the same
    KR20150044914A|2015-04-27|Diamond Semiconductor Device and Method for Manufacturing Same
    JP2003234301A|2003-08-22|Semiconductor substrate, semiconductor element and method for manufacturing the same
    Dutta et al.2016|Demonstration of diamond-based Schottky pin diode with blocking voltage> 500 V
    Davis1989|Epitaxial growth and doping of and device development in monocyrstalline β-SiC semiconductor thin films
    CN109873038B|2020-12-08|Field effect transistor and preparation method thereof
    TWI534910B|2016-05-21|Method of manufacturing semiconductor device
    JP6560117B2|2019-08-14|Manufacturing method of semiconductor device
    Carey et al.2019|Comparison of dual-stack dielectric field plates on β-Ga2O3 Schottky rectifiers
    JP2000133819A|2000-05-12|Silicon carbide schottky barrier diode and manufacture thereof
    ES2763702B2|2020-10-28|FIELD EFFECT TRANSISTOR | AND PROCEDURE FOR MAKING THE SAME
    CN110010471A|2019-07-12|A kind of power device and preparation method thereof
    Kato et al.2012|Maskless selective growth method for p–n junction applications on |-oriented diamond
    CN103928524A|2014-07-16|Silicon carbide UMOSFET device with N-type drifting layer table face and manufacturing method
    CN103928346B|2016-08-24|It is epitaxially-formed the UMOSFET device preparation method of N-type heavy doping drift layer table top
    CN109378312B|2020-08-18|Body-doped diamond-based normally-off field effect transistor and preparation method thereof
    CN109285894B|2021-01-19|Diamond-based multi-channel barrier regulation field effect transistor and preparation method thereof
    CN106876256B|2020-05-12|SiC double-groove UMOSFET device and preparation method thereof
    US10573716B2|2020-02-25|Method of manufacturing a silicon carbide semiconductor device including depositing a second silicon carbide semiconductor on an etched silicon carbide base region
    CN104992972A|2015-10-21|Transverse nanowire interdigital-structure transistor based on SOI substrate and preparation method
    CN108493111B|2019-04-19|Method, semi-conductor device manufacturing method
    同族专利:
    公开号 | 公开日
    ES2763702B2|2020-10-28|
    WO2020109641A1|2020-06-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    EP2884525A1|2012-08-17|2015-06-17|National Institute of Advanced Industrial Science and Technology|Diamond semiconductor device and method for manufacturing same|
    法律状态:
    2020-05-29| BA2A| Patent application published|Ref document number: 2763702 Country of ref document: ES Kind code of ref document: A1 Effective date: 20200529 |
    2020-10-28| FG2A| Definitive protection|Ref document number: 2763702 Country of ref document: ES Kind code of ref document: B2 Effective date: 20201028 |
    优先权:
    申请号 | 申请日 | 专利标题
    ES201831162A|ES2763702B2|2018-11-29|2018-11-29|FIELD EFFECT TRANSISTORAND PROCEDURE FOR MAKING THE SAME|ES201831162A| ES2763702B2|2018-11-29|2018-11-29|FIELD EFFECT TRANSISTORAND PROCEDURE FOR MAKING THE SAME|
    PCT/ES2019/070812| WO2020109641A1|2018-11-29|2019-11-28|Field-effect transistorand method for manufacturing same|
    [返回顶部]