• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Integrated photonic device with quantum array of field programmable photonic gates. Quantum device and programmable circuits. The invention relates to a quantum system based on an integrated photonic circuit carried out by combining and interconnecting programmable photonic processing circuits, implemented on a photonic circuit capable of implementing one or multiple classical and quantum circuits with optical feedback elements and/or linear transformations of multiple ports, by programming their resources and selecting their input and output ports. The invention also relates to a quantum field-programmable photonic gate array (Q-FPPGA) quantum field reversible photonic gate array, comprising at least one programmable circuit based on Tunable optical power dividers with independent phase tuning capability and high-performance peripheral circuits enabling classic and quantum operations. (Machine-translation by Google Translate, not legally binding)
    公开号:ES2752086A1
    申请号:ES201931123
    申请日:2019-12-18
    公开日:2020-04-02
    发明作者:López Daniel Pérez；Francoy José Capmany
    申请人:Universidad Politecnica de Valencia；
    IPC主号:
    专利说明:

    [0001]
    [0002]
    [0003]
    [0004] OBJECT OF THE INVENTION
    [0005]
    [0006] The current invention relates to a quantum system based on an integrated photonic circuit carried out by combining and interconnecting programmatic photonic processing circuits, implemented on a photonic circuit capable of implementing one or multiple classical and quantum circuits with feedback elements. optics and / or linear transformations of multiple ports, by programming its resources and selecting its input and output ports. The invention also relates to a quantum field-programmable photonic gate array ( Q-FPPGA), field programmed reversible photonic gate array for quantum signal processing , comprising at least one programmable circuit based on Tuner optical power dividers with independent phase tuning capability and high-performance peripheral circuits enabling classic and quantum operations.
    [0007]
    [0008] BACKGROUND OF THE INVENTION
    [0009]
    [0010] Programmable Multifunctional Photonics (PMP) seeks to design hardware configurations based on integrated optics that implement a wide variety of applications and functionalities through the specific programming of its components. Several authors have tried theoretical works proposing different configurations and design principles related to programmable circuits based on the chaining and interconnection of optical power dividers or Mach-Zehnder interferometers (MZIs). Although these proposals offer versatile physical solutions to implement circuits, they do not define a complete architecture for a photonic device that can be programmed to implement simple and complex arbitrary circuits in isolation or simultaneously. Only a series of recent patent documents (US16 / 235,056, JP2018-247546, P201930410, P201831118) propose and consider the aforementioned details, resulting in the definition of a field programmable photonic device, from the English field programmable photonic. arrays ( FPGA).
    [0011]
    [0012] Additionally, the combination of optical basic processing units with the ability to program / tune / select the percentage of optical power division between its output ports and phase tuning has been proposed, resulting in meshed waveguide elements with different topologies and an unprecedented versatility in relation to its functionalities. In particular, some of the proposed architectures allow the recirculation of the optical signal within the mesh, allowing the formation of optical cavities, Sagnac-type loops and more complex circuits. Furthermore, a recent patent application (P201930410) also describes a technical improvement of waveguide meshes based on the combination of tuning units and basic processing, of the English Tunable Basic Unit ( TBU) that have the same spatial / angular orientation . This means that the longitudinal axes of the TBUs are parallel to each other, regardless of the interconnection topology used. This technical advantage mitigates manufacturing defects and improves the performance and scalability of manufactured circuits.
    [0013]
    [0014] In parallel, several authors have published integrated circuits that perform linear transformations of the guided modes at the input of a waveguide mesh. The proposed architectures require the combination and fixed interconnection of power dividers and phase actuators. Some publications employ these circuits to perform a limited set of operations that are used in the processing of quantum signals, most notably in the creation of transformation matrices describe the operation between the input and output modes.
    [0015]
    [0016] DESCRIPTION OF THE INVENTION
    [0017]
    [0018] The object of the invention described here solves the mentioned problems and allows the design of quantum and classic signal processing systems in a programmable way where all the mentioned components are connected to a reconfigurable optical nucleus that allows the implementation of reconfigurable linear transformations, conditioning of signal and dynamic interconnection between high-performance classical processing blocks, high-performance quantum signal processing blocks, couplers between chips and fiber-chip couplers.
    [0019] The object of the invention is based on the repetition, replication and interconnection of programmable analog processing photonic units and reconfigurable interconnections preferably implemented on a photonic chip. These components provide the basic building blocks for implementing basic analog signal optical operations (reconfigurable optical power and power split plus standalone phase configuration) and, by extension, reconfigurable 2x2 gates or rotation matrices. In a very broad sense, the processing performed can be considered to be reconfigurable, in the same way that programmable logic blocks carry out digital operations in electronic FPGAs or in configurable analog blocks, which carry out analog operations in matrices. analog programmers, from English (Field-Programmable Analog Array). In this way, and by virtue of what is proposed below, it can be seen that the object of the invention allows obtaining one or more simultaneous photonic circuits and / or multiport linear transformations through the specific programming of the resources and integrated components, is That is, of the programmable analog operation photonic blocks, classic high-performance signal processing blocks (High Performance Building-block, HPB) and quantum high-performance signal processing blocks (Quantum High Performance Building- block, QHPB), and the selection of the ports used. Thus, the essential contribution of this invention is the architecture, the workflow, the arrangement of technological layers and the technical description that allows the programming of multipurpose interconnection schemes for the performance of quantum signal processing and quantum signal processing in parallel to classic signal processing.
    [0020]
    [0021] The object of the invention is described in the set of claims, included herein by reference.
    [0022]
    [0023] Full quantum operation requires the circuit to be powered by a signal from a quantum generating source and to be detected at quantum signal detection elements. Altogether, although current systems or circuits are capable of performing reconfigurable linear transformations required for quantum operations, they do not offer the flexibility required to dynamically interconnect the different subsystems or processing blocks required by the processor.
    [0024] The quantum circuit-based quantum system, a field-programmable reconfigurable analogue gate photonic matrix for quantum signal processing, of the present invention offers a number of advantages inherent in field programming or in real time, expanded by the optical circuit topologies introduced by the invention. These include:
    [0025] • Reduction in production and market arrival times.
    [0026] • Shorter prototype development times and associated cost reduction.
    [0027] • Reduction of financial risks in the development of ideas and in their transfer to ASPICS.
    [0028] • Multifunctional and simultaneous or parallel operation circuits.
    [0029] • Optimization of circuits.
    [0030] • Reduction of manufacturing areas and refinement of a single and common architecture.
    [0031] • Better performance and reproducibility of programmable analog photonic blocks.
    [0032] • Greater number of alternative topologies not limited to geometric factors or fixed arrangements.
    [0033]
    [0034] The proposed chip (Q-FPPGA) of the current invention can be applied in the following fields:
    [0035]
    [0036] Classic applications:
    [0037] • Aerospace and defense (avionics, communications, security solutions, space).
    [0038] • Automotive (High-quality video resolution, image processing, communication between vehicles and connectivity).
    [0039] • Data centers (Servers, routers, switches, gateways)
    [0040] • High performance computing (Servers, supercomputers, SIGINT systems, long-range radials, beamforming systems, quantum computing, high-speed neural networks).
    [0041] • Integrated circuits design (Prototyping of specific application circuits, hardware emulation).
    [0042] • Wired and wireless communications (Optical transport networks, 5G connectivity interfaces, Mobile network)
    [0043] • Hardware accelerators.
    [0044] • Artificial intelligence, machine learning, and machine learning through deep neural networks.
    [0045] • Educational kits.
    [0046] DESCRIPTION OF THE DRAWINGS
    [0047]
    [0048] To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, according to a preferred example of practical embodiment thereof, a set of drawings is included as an integral part of said description. where, by way of illustration and not limitation, the following has been represented:
    [0049]
    [0050] Figure 1 shows a general schematic of the Q-FPPGA architecture with the core of the Q-FPPGA connected to optical ports, high performance processing blocks and high performance quantum processing blocks, where the illustration shows a detail of the three layers that describe the architecture from a hardware and software point of view.
    [0051]
    [0052] Figure 2a shows some non-limiting examples of a Q-FPPGA core embodiment example interconnection diagram, where the illustration shows a detail of the internal interconnection scheme using programmable photonic analog blocks or basic tuning units of the same orientation and forming a pattern. (a1): hexagonal uniform conventional distribution, (a2): proposed layout of units with the same orientation.
    [0053]
    [0054] Figure 2b shows some non-limiting examples of a Q-FPPGA core embodiment exemplary interconnection diagram, where the illustration shows a detail of the internal interconnection scheme using programmable photonic analog blocks or basic tuning units of the same orientation and forming a pattern. (b1): conventional uniform square distribution, (b2): proposed layout of units with the same orientation.
    [0055]
    [0056] Figure 2c shows some non-limiting examples of a Q-FPPGA core embodiment exemplary interconnection diagram, where the illustration shows a detail of the internal interconnection scheme using programmable photonic analog blocks or basic tuning units of the same orientation and forming a Pattern. (c1): conventional triangular uniform distribution, (c2): proposed layout of units with the same orientation.
    [0057]
    [0058] Figure 2d-e shows some non-limiting examples of a Q-FPPGA core embodiment example interconnection diagram, where the illustration shows a detail of the internal interconnection scheme using programmable photonic analog blocks or basic tuning units of the same orientation and forming a non-uniform pattern.
    [0059]
    [0060] Figure 3 shows a non-limiting example of the classification of different classical and quantum devices present in the Q-FPPGA architecture.
    [0061]
    [0062] Figure 4 shows in the left part, the main steps of the design / configuration flow of the integrated photonic device and quantum system of the current invention, and in the right part the software and hardware layers of the photonic circuit and the expanded scheme including the high-performance peripheral elements.
    [0063]
    [0064] Figure 5 shows the simultaneous implementation of a classic ring cavity based circuit, a Mach-Zehnder interferometer and a multiport 3x3 device using a reconfigurable Q-FPPGA core of the chip of the current invention.
    [0065]
    [0066] Figure 6 shows on the left-hand side a non-limiting example of the implementation of a quantum circuit with verification paths (in this case a CNOT-type gate with an arrangement shown on the right-hand side of the figure), where the state of The input and control photons ( heralded) are generated by QHPBs that generate photon pairs through nonlinear effects such as Spontaneous Four Wave Mixing (SFWM) and the output state and the control photons are detected by specific QHPBs blocks that implement counters of photons. The programmable mesh waveguides implement two tasks, that of filtering one of the two photons generated by (SFWM) and the linear unit transformation that the CNOT gate implements. QHPBs should ideally be on the same chip, but can be placed externally, within the Q-FPPGA by hybrid or heterogeneous integration. Note that unused HPB blocks and Q-FPPGA input and output ports not used in this case are not shown for simplicity. In addition, more circuits Complexes can be implemented by extending the concept shown and using a higher percentage of the resources, components and mesh portion, as well as extra QHPBs implementing additional sources and detectors.
    [0067]
    [0068] Figure 7 shows in the left part a non-limiting example of the implementation of a set of programmable quantum circuits that switch or share resources simultaneously. The example shows a triangular boson sampler and a Hadamard gate, the implementation of which is shown in the upper right and lower right, respectively. Both circuits share QHPBs that generate pairs of photons via SFWM, in addition to a common part of the nucleus formed by the waveguide mesh to implement their corresponding linear transformations. The commutation is carried out by tuning the Programmable Photonic Analog Block (PPAB), within the waveguide mesh to select the operation of one or the other circuit. Photon detection is performed in this example using unshared QHPBs.
    [0069]
    [0070] Figure 8 shows on the left a non-limiting example of simultaneous implementation of an independent quantum circuitry. Each circuit uses its own resources. In this specific case, QHPBs are used in preparation for detecting input and output signals respectively, and different sections of the waveguide mesh are used to implement photon filters and required linear unit transformations. The two circuits in this case are a Hadamard gate and a cascade of gates corresponding to the rotational X, Y, and Z transformations. The QHPB that implements the initial state of the Hadamard gate are photon pair sources that require post-filtering, while those that implement the initial state of cascaded rotation matrices are single photon sources.
    [0071]
    [0072] Figure 9 shows a non-limiting example of a programmable quantum circuit where the initial state is obtained externally to the chip by a set of optical input ports and the output state is sent to a set of output ports. The Q-FPPGA is programmed to perform a unit linear transformation. In the example, the transformation corresponds to a quantum Fourier transform.
    [0073]
    [0074] Figure 10 shows on the left a non-limiting example of the configuration simultaneous quantum and classical circuits. Part of the waveguide mesh is used to implement quantum gates (cascade rotations), while the other part implements a classic coupled cavity circuit, for the realization of a classic signal filter. The quantum circuit uses QHPBs for signal generation and detection, while the classical part uses two HPBs that consist of the integration of a DBF laser and an external modulator. The part on the right includes the diagrams of the implemented circuits.
    [0075]
    [0076] PREFERRED EMBODIMENT OF THE INVENTION
    [0077]
    [0078] Next, an embodiment of the invention according to the figures shown is detailed. In Figure 1, a Q-FPPGA is shown comprising at least one, but preferably a large number of programmer analog photon processing blocks (PPABs) implemented by a series of waveguide elements integrated into a photon circuit. These blocks have programmable characteristics and can propagate the optical signal in both directions. The design in Figure 1 does not consider any particular interconnection topology for the core of the Q-FPPGA, serving only as an illustrative example. Figure 2 shows different alternatives and design interconnection geometries for the implementation of the Q-FPPGA core. Although different configurations can be considered for the implementation of the PPAB, in this case we illustrate the design with basic units and 4 ports, such as those described in US 16 / 235,056, JP 2018 247546, P201930410, P201831118, included here for reference. . The function of the PPAB is to independently offer tunable power couplings and adjustable phase response settings, as explained below. In general, the waveguide mesh performs dynamic routing or switching between the different ports and areas of the Q-FPPGA and between classic and quantum high-performance processing blocks.
    [0079]
    [0080] Similar to modern families of FPGAs, Q-FPPGAs can include classic and quantum advanced processing blocks (HPB, QHPB) to expand their capabilities and include high-level functionality connected to the core of the chip. The right part of Figure 1 shows a schematic of the previous description. The availability of high-level functions and blocks on the chip reduces the area required by these functions compared to their implementation by means of the basic core blocks. Also, some of the functions cannot be divided and program using only the kernel. Some examples of these processing blocks include highly dispersive elements, spiral delay lines, generic photodetection and modulation subsystems, optical amplifiers, optical source subsystems, and high-performance filtering systems, among others. A special case of HPB is the one that comprises an element, interconnected with the optical nucleus, that comprises a multiplexing and demultiplexing subsystem, being able to be spectrally cyclic, or non-cyclic, allowing the processing of different spatial channels / modes, as well as different spectral channels defined by the frequency of the signal. However, the greatest technical advantage comes from the interconnection of quantum HPBs. These offer quantum functionality that can be efficiently divided, distributed, and programmed within the core of the Q-FPPGA in addition to being combined with HPBs and QHPBs, such as quantum sources, detectors, processing signals, and auxiliary detectors, among others. Figure 3 illustrates as a non-limiting example a set of components that may be present in the Q-FPPGA.
    [0081]
    [0082] PPABs are 2x2 photonic blocks or components that offer the ability to independently configure a common phase shift A fpAB and an optical power division ratio K = sinQ (0 <= K <= 1) between the input and output fields of your access waveguides.
    [0083]
    [0084] Through specific programming and concatenation of processing blocks, the Q-FPPQA can implement complex autonomous or parallel circuits, signal processing transformations, and quantum processing operations by dividing conventional optical processing circuits into photonic blocks of reconfigurable interconnect (English, RPIs) and PPAB units, and using advanced processing blocks. In particular, the Q-FPPGA core programming concept is illustrated by three generic designs, represented in Figure 5, respectively. Figure 5 (a) shows how the configuration of each processing unit leads to the programming of two optical filters based on a resonant ring and a Mach-Zehnder interferometer. Figure 5 (b) shows the programming of the core of a Q-FPPGA to obtain a multiport interferometer.
    [0085]
    [0086] The quantum field-programmable photonic gate array (Q-FPPGA), in accordance with the Invention is an array of independent elements that can be interconnected according to user specifications for the configuration of a wide variety of classical and quantum applications. The Q-FPPGA combines the programmability of the most basic reconfigurable photonic integrated circuits and quantum processing components into a scalable interconnect structure, allowing the programming of much higher density dynamic circuits. Thus, the programming of complex circuits is given by interconnectivity. Our proposed invention thus solves some of the problems associated with quantum circuits. Quantum and classical circuits are programmed using shared resources integrated on a chip offering the advantages inherent in direct programming devices (or in the field): reduction of the times to produce, develop and bring a solution to market, reduction of the times of prototyping and non-recurring engineering costs, reduction of financial risks in the development of ideas and their translation to ASPICs, multi-functional and multitasking operations, optimization of circuits, performance improvements and reproducibility of PPABs. Compared to FPPA or reconfigurable photonic circuits, the present invention incorporates dynamic quantum signal processing thanks to the incorporation of advanced processing blocks and workflow design and architecture.
    [0087]
    [0088] The left part of Figure 4 shows the main steps of the design flow, described below. Similar to photonic FPPA, the starting point of the design flow is the input of the application to be implemented. In this case, they can be quantum and / or classic applications. The specifications are then processed using an optimization procedure to improve the area used and the performance of the final circuit. The specifications are then transformed into a circuit compatible with the elements included in the Q-FPPGA (technology mapping process), optimizing the attributes such as delay, performance achieved or the number of elements used.
    [0089]
    [0090] The technology mapping phase transforms the optimized network into a circuit consisting of a restricted set of elements of the Q-FPPGA. This is done by selecting components and parts of the network that can be implemented by the elements available in the Q-FPPGA, and then specifying how the interconnection between these elements is carried out. This will determine the total number of processing components required by the objective implementation.
    [0091]
    [0092] Next, the location of the different parts of the circuit is decided by assigning them to a specific location in the Q-FPPGA. At that time, global routines are responsible for the selection of the processing elements that will operate as access roads. In contrast to an electronic FPGA, this structure does not have to be physically differentiated from the processing and interconnection elements. Then, the processing elements are configured accordingly and performance is calculated and design verification is performed. This process can be carried out physically by feeding all the configuration data to the programming units to configure the final chip or by using precise models of the Q-FPPGA. At each step, an optimization process is possible that might decide to reconfigure any of the previous steps.
    [0093]
    [0094] From the previous description, it can be seen that the Q-FPPGA involves not only the physical photonic and electronic control device, but also includes a software layer (see the right side of Figure 1 and Figure 4).
    [0095]
    [0096] The steps contained in the design flow can be performed automatically through the software layer, by the user, or by both parties, depending on the autonomy and capabilities of the Q-FPPGA. Also, a failure in any of the previous steps would require an iterative process until the specifications are satisfactorily met. A parallel optimization process provides robust operation in addition to manufacturing fault and defect tolerance capabilities and increased processing capabilities of the physical device.
    [0097]
    [0098] In addition, the Q-FPPGA can incorporate multiple independent cores that can be interconnected to each other and to advanced processing blocks to increase its processing capacity. These waveguide cores can be integrated on the same substrate or on different chips.
    [0099]
    [0100] OPERATION EXAMPLE
    [0101]
    [0102] Figures 6 to 10 show some examples where Q-FPPGAs of different types they are programmed for the emulation and simultaneous implementation of different quantum photonic circuits. The examples are representative of capabilities and are not intended to be exhaustive. Instead, they show simple configurations that can be extended to more complex circuits. Only relevant components such as optical input and output ports, HPBs, and QHPBs are shown in these diagrams. In each case, the figure includes the Q-FPPGA scheme with the active PPABs highlighted in the waveguide core and the schemes of the different circuits implemented.
    [0103]
    [0104] Figure 6 represents an operation case where the Q-FPPGA is programmed for the implementation of quantum gates. The case illustrated here corresponds to a C-NOT gate. The input state and control photons are generated using specific QHPBs that implement integrated photon pair sources based on Spontaneous Four Wave Mixing (SFWM). And the output state and detection of control photons require specific QHPBs that implement integrated photon counters. The waveguide mesh is programmed to carry out two tasks, a classic filter for the selection of one of the two photons generated by each SFWM source and the optical linear transformation required for the implementation of the CNOT gate operation.
    [0105]
    [0106] Figure 7 illustrates switch mode operation. Here two or more circuits are programmed in the resources available in the Q-FPPGA that shares in this case QHPBs, and specifically the independent photon sources. The example shows the programming of a Hadamard-type gate and a triangular boson sampler. The operation is selected by activating one or more elements of the waveguide mesh that in this case act as a circuit breaker.
    [0107]
    [0108] Figure 8 illustrates the shared mode operation where two or more circuits are configured simultaneously on the physical device defined by the waveguide mesh and the peripheral blocks. In this case, each circuit uses its own set of QHPBs, which are not shared. The example shows the implementation of a Hadamard gate and a waterfall of 3 2x2 gates that define rotations. The Hadamard gate uses for example QHPBs that implement photon pair sources using SFWM, which require additional photon filtering, while the Rotation matrix cascade uses QHPBs that directly provide independent photons.
    [0109]
    [0110] Figure 9 illustrates the case in which a state or quantum mode (dimension N) is inserted through the input of the QFPGA. Here, the QFPGA is programmed to perform a simple linear transformation and no additional QHPBs are used, unless the end state is measured. In the case of the example in Figure 9, the implementation of a quantum Fourier transform is represented. Finally, Figure 10 shows an example of mixed operation of classical and quantum signals. Here, part of the core formed by the waveguide mesh implements a quantum gate (cascade of rotation matrices), while another implements a classic coupled cavity filter (CROW) to process the classic signal generated by using two HPBs they consist of an integrated DBF and an external modulator.
    [0111]
    [0112] PHYSICAL IMPLEMENTATION
    [0113]
    [0114] The physical implementation of the Q-FPPGA device can be performed using integrated optics either in silicon photonics technology or other Group IV materials, or by hybrid or heterogeneous combinations together with other materials such as those from Group III-V.
    [0115]
    [0116] For PPAB elements, current integrated photonics technology allows the integration of phase tuning elements such as: MEMS, thermo-optical, opto-mechanical, electro-capacitive effects, phase change materials or non-volatile actuators. These phase actuators integrate into any interferometric or non-interferometric, resonant or non-resonant structure with more than two ports. Finally, as mentioned above, more complex Q-FPPGAs can be designed by configuring different block interconnection schemes. Some examples are shown in Figure 2.
    [0117]
    [0118] As described in Figure 1, the physical device (hardware) corresponding to the integrated optical circuit has to be integrated together with the electronic control systems to carry out programming tasks of the optoelectronic actuators and to carry out tasks of global optimizations of the circuit.
    权利要求:
    Claims (17)
    [1]
    1. A quantum field programmable photonic gate array (Q-FPPGA) characterized by comprising:
    - a reconfigurable core consisting of an array of field programmable photonic gates, and
    - at least one high-performance quantum processing block (QHPBB),
    where the at least one high performance quantum processing block (QHPBB) connects to the reconfigurable core.
    [2]
    2. The field programmable photonic gate quantum matrix (Q-FPPGA) according to claim 1, wherein the at least one programmable photonic gate quantum matrix (Q-FPPGA) further comprises at least one optical port and / or the minus a high performance quantum processing block (HPBB) connected to the core of the reconfigurable photonic gate quantum matrix.
    [3]
    The field programmable photonic gate quantum matrix (Q-FPPGA) according to either of claims 1 and 2, wherein the at least one field programmable photonic gate quantum matrix (Q-FPPGA) further comprises at least one Programmable Photonic Analog Block (PPAB) implemented by a series of photonic waveguides integrated into the photonic chip substrate.
    [4]
    4. The field programmable photonic gate quantum matrix (Q-FPPGA) according to claim 3, comprising at least two programmable analog processing photonic blocks (PPAB) integrated in the same orientation and following a uniform topology.
    [5]
    5. The field programmable photonic gate quantum matrix (Q-FPPGA) according to claim 4, wherein the uniform distribution topology is one of those selected from a hexagonal topology of waveguide meshes, square topology of meshes of waveguide and triangular topology of waveguide meshes.
    [6]
    6. The field programmable photonic gate quantum matrix (Q-FPPGA) of according to claim 3, which comprises at least two programmable analog processing photonic blocks (PPAB) integrated in the same orientation and following a non-uniform topology.
    [7]
    7. The field programmable photonic gate quantum matrix (Q-FPPGA) according to claim 2, wherein the at least one of the high performance processing elements (HPBBs) is one of those selected among highly dispersive elements, lines of waveguide delay, generic modulation elements and photodetection systems, optical amplifiers and emission subsystems and high-performance filtering structures, multiplexers and demultiplexers.
    [8]
    8. The field programmable photonic gate quantum matrix (Q-FPPGA) according to claim 2, wherein the at least one high performance quantum processing block (QHPBBs) is selected from quantum sources, detectors, processing units and detectors.
    [9]
    9. The field programmable photonic gate quantum matrix (Q-FPPGA) according to claim 2, further comprising multiple and independent processing cores interconnected with each other and connected to high performance processing elements (HPBBs, Q- HPBBs).
    [10]
    10. A quantum and photonic integrated device implemented by means of a chip integrated photonic circuit on a substrate, characterized in that it comprises:
    - a physical layer comprising at least one quantum field programmable photonic gate (Q-FPPGA) of any one of the preceding claims; -a layer of control electronics; and
    -a software layer.
    [11]
    11. A programmable quantum circuit including an integrated photonic circuit and a quantum device according to claim 10.
    [12]
    12. The programmable quantum circuit of claim 11, wherein the circuit is based on a resonant ring or a Mach-Zehnder type interferometer (MZIs).
    [13]
    13. A programmable quantum circuit design method of any of claims 11 or 12 characterized by comprising the following steps:
    - choice of an initial application to be implemented;
    -processing an area and features of the programmable quantum circuit;
    - mapping and transferring the application on a circuit compatible with the field programmable photonic gate quantum matrix (Q-FPPGA) processing blocks.
    [14]
    The method of claim 13 wherein the application mapping and transferring step in a circuit compatible with the elements of the field programmable photonic gate quantum matrix (Q-FPPGA) further comprises:
    - a first selection step where the parts of the circuit are implemented by means of integrated circuit elements,
    - an interconnection step in which the circuit elements are connected, - an allocation step where each processing block is assigned to a specific location in the field programmable photonic gate quantum matrix (Q-FPPGA).
    - a second selection step where the processing elements that operate as access roads and interconnection are selected.
    [15]
    15. The method of claim 14, further comprising:
    - calculation of circuit performance and a design verification step.
    [16]
    16. The method of claim 15 where in addition the calculation of the circuit performance and the design verification step is performed physically by loading the configuration data of the data necessary to program the units that configure the chip or by the use of accurate models of the field programmable photonic gate quantum matrix (Q-FPPGA).
    [17]
    17. The method of any of claims 13 to 16 where the steps are carried out automatically by the software layer, by the user or by a mixture of both, depending on the degree of autonomy and the capabilities of the quantum matrix Field Programmable Photonic Gate System (Q-FPPGA).
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    同族专利:
    公开号 | 公开日
    ES2752086B2|2020-08-07|
    WO2021123470A1|2021-06-24|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    ES2695323A1|2018-11-19|2019-01-03|Univ Valencia Politecnica|METHOD OF CONFIGURATION AND OPTIMIZATION OF PROGRAMMABLE PHOTONIC DEVICES BASED ON MALLED STRUCTURES OF INTEGRATED OPTICAL GUIDEWAYS |WO2022013466A1|2020-07-16|2022-01-20|Universitat Politècnica De València|Programmable photonic integrated circuit and related method of operation|JP3897688B2|2002-12-11|2007-03-28|キヤノン株式会社|Optoelectronic wiring board|
    US9354039B2|2014-06-06|2016-05-31|Massachusetts Institute Of Technology|Methods, systems, and apparatus for programmable quantum photonic processing|
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    ES201931123A|ES2752086B2|2019-12-18|2019-12-18|INTEGRATED PHOTONIC DEVICE OF QUANTUM MATRIX OF FIELD PROGRAMMABLE PHOTONIC DOORS, QUANTIC DEVICE AND PROGRAMMABLE CIRCUITS|ES201931123A| ES2752086B2|2019-12-18|2019-12-18|INTEGRATED PHOTONIC DEVICE OF QUANTUM MATRIX OF FIELD PROGRAMMABLE PHOTONIC DOORS, QUANTIC DEVICE AND PROGRAMMABLE CIRCUITS|
    PCT/ES2020/070671| WO2021123470A1|2019-12-18|2020-10-30|Integrated photonic device comprising a field-programmable photonic gate array, a quantum device and programmable circuits|
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