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    • 专利摘要:
    A method of controlling the current within a power inverter, the power inverter comprising at least a first branch parallel to a second branch, wherein at least one power switch of the first branch is carrying at least 60% of the full current of the power inverter in a first switching period and at least one power switch of the second branch is carrying at least 60% of the full current of the power inverter in a subsequent switching period.
    公开号:DK201570269A1
    申请号:DKP201570269
    申请日:2015-05-07
    公开日:2016-11-14
    发明作者:Bjørn Rannestad
    申请人:Kk Wind Solutions As；
    IPC主号:
    专利说明:

    Discontinued interleaving based control of a power inverter Field of the invention
    The invention relates to a method of controlling current in a power inverter and such power inverter.
    Background of the invention
    Every power inverter in operation i.e. through which current is conducted is subject to losses. There are different types of losses depending on the type of power switches and the size of the losses is also dependent on the type of switches. These losses mainly relates to conduction losses and losses in relation to change of state of the power switches. It is always desired to reduce these losses and one common way of doing this in relation to conduction losses is to limit the current through the power switches. In relation to tum-on and tum-ofif i.e. losses relating to change of state of the power switches the type of the power switches may be selected based on its properties in relation to losses in the application it should be used.
    Brief description of the invention
    It is an object of the invention to control a power inverter independent of type of power switch so as to reduce losses in the power inverter. This is according to the invention accomplished by a method of controlling the current within a power inverter, the power inverter comprising at least a first branch parallel to a second branch, wherein at least one power switch of the first branch is carrying at least 60% of the full current of the power inverter in a first switching period and at least one power switch of the second branch is carrying at least 60% of the full current of the power inverter in a subsequent switching period.
    In an advantageous embodiment of the invention the at least one power switch of the first branch is carrying at least 90% preferably 100% of the full current of the power inverter in a first switching period and at least one power switch of the second branch is carrying at least 90% preferably 100% of the full current of the power inverter in a subsequent switching period.
    By mentioning 100% of the full current it should be mentioned that this is in the ideal case. In reality it is hard to ensure that all current is running in one branch even though it is desired. At least at a point in time during a first switching period the full current is conducted by the first branch and at least a point in time during the subsequent switching period the full current is conducted by the second branch. Hence in contrary to known ways of controlling the current through branches of a half bridge power inverter the current is according to present invention unevenly distributed between the branches. A power switch may according to this invention be referred to as either a passive switch such as a diode or an active switch such as a controllable semiconductor switch e.g. an IGBT or MOSFET or the like. Semiconductor switches may be of the silicon type or any other semiconductor material such as silicon carbide and gallium nitride.
    By controlling a power inverter according to the inventive method leads to conducting losses in the active switches which is two times the conducting losses of active switches which are controlled according to the traditional current sharing principles. Despite this drawback it has turned out that by controlling according to the new inventive control method the current though the diodes when shifting switching period is reduced leading to a reduction in diode turn-off loss. Hence the reverse recovery loss in the diode antiparallel (seen from the current this diode is turned upside down compared to the switch) to the active switch carrying the current as well as in turn on losses of the active switch is reduced. Therefore by controlling the power inverter according to the inventive method the total losses are minimised as compared to the power inverters controlled according to the traditional control method. This is further intensified if commutation inductors in the output of each branch is introduced as describe in below. A switch period is defined by the control system as the time current flows through a branch typically based on a PWM signal i.e. from one active switch is turned on to a second active switch is turned on (it should be noted that this could be the same switch). It should be note that a switch period may be divided in two where one part of the switch period the current flows through an active switch in the form of e.g. an IGBT switch and another part of the switch period where current flows through a passive switch in the form of e.g. a diode. Whether the current first flows though the switch or the diode depends on the direction of the current. A power inverter is in relation to this document defined per phase as at least two half bridges in parallel. The common output of the at least two half bridges is referred to as the output of the power inverter. Each of the at least two parallel half bridges are referred to as a branch and is connected to the same DC+ / DC-. Hence according to the invention a power converter comprise a plurality of parallel branches each branch comprising a plurality of power switches.
    Typically a power inverter comprises three independent phases and thereby the power inverter comprises at least three sets of at least two half bridges all which are controlled according to the same principles.
    The full current is in relation to this document defined as the full current of the phase operated by the power inverter. It should be mentioned that examples may occur where the full current is not conducted by one branch in the entire switching period. Typically when the current is commutated completely to one branch the full current flows through that branch. Towards the end of the switching period the other branch may be switched to a conductive mode and current is then starting to commutate from the first to the second branch.
    The definition of power inverter may depend on the type of active switch used and may vary from a current of 10 amps to several thousand amps. When the power inverter is used in relation to wind turbines each branch will conduct above 100 amps. Above 100 amps is also the typical size of the current conducted by a branch of a power inverter of the present invention when using power switches such as IGBTs.
    It should be mentioned that the order of power switches (active switches and diodes) in which the currents are commutating depends on the direction of the current. Hence in general a positive current would commutate from the “higher” active switch (and or “lower” diode) of the first branch in the first switching period to the “lower” diode of the second branch in the subsequent switching period. In the same way a negative current would commutate from the “lower” active switch (and/or “higher” diode) of the second branch to the “higher” diode of the first branch.
    In an advantageous embodiment of the invention within the first switching period after a delay of a predefined time from activating an active switch of the first branch an active switch of the second branch is activated.
    In an advantageous embodiment of the invention the one or more parallel power inverters provides a total phase output.
    As mentioned a power inverter comprises two branches the output is referred to as power inverter output. When two or more power inverters are coupled in parallel the total output of these power inverters is referred to as total phase output. Similarly for other phases of e.g. a three phase system each phase may comprise a plurality of parallel power inverters each having a power inverter output which together is referred to as total phase output.
    This is advantageous in that if the total current of a phase is e.g. 3000 amps then one power inverter may not be capable of carrying such high current. In this situation a plurality of parallel power inverts may mutually carry this current.
    In an advantageous embodiment of the invention the first branch output includes a first output branch inductance and the second branch output includes a second branch output inductance and wherein the accumulated current through the first and second output branch inductances is the power inverter output.
    This is advantageous in that an instant change of current from the first branch to the second branch and vice versa is avoided. This has the advantageous that the diode of the branch the current leaves gains time to recover and thereby the reverse recovery loss is reduced or potentially even eliminated. Further the active switch in the receiving branch is turned on a very low current leading to turn on losses of the switch is reduce of potentially even eliminated
    In an advantageous embodiment of the invention the first and second branch inductances comprises non-linear inductors 10a, 10c having a non-saturated inductance of more than 50uH.
    By non-linear inductor should be understood an inductor which saturates after a period of time with a voltage across. This higher voltage the shorter time from the voltage is applied to the inductor saturates.
    The time from the voltage is applied to the inductor saturates is used by the diode to recombine hence the voltage / time relationship should be balanced with the specific diode. In any case it is advantageous that the inductance of the diode is above lOOuH (micro Henry) in order to give the diode sufficient time to recombine.
    Preferably the size of the inductors in the output of the two branches are the same in that this will give the same time delays in both branches, but different sizes inductors may be implemented. A time corresponding to a voltage in the interval between 0 and lOVolt (zero not included) is sufficient to obtain a time in which recombination of most types of diodes is possible.
    In an advantageous embodiment of the invention the time from voltage is applied to at least one of the first and second inductors to at least one of the first and second non-linear inductors saturates is less than 15us, preferably lOus, most preferably 5us.
    In most cases lOus (micro seconds) is sufficient for a diode of the power inverter to recombine and often 5us is enough.
    In an advantageous embodiment of the invention the saturation point of the first and second branch non-linear inductors is above 1 Tesla. Having inductors at this saturation point and above is advantageous in that the physical size of the inductor is minimized significantly compared to an inductor of e.g. ATcsla.
    In an advantageous embodiment of the invention the core of the first and second branch non-linear inductors is at least partly made of one of the list comprising: an amorphous magnetic material, nanocrystalline magnetic material, ferrite or laminated steel. Nanocrystalline magnetic material is advantageous in that it has a very high magnetic permeability which gives a very high inductance and in that it has a high saturation point i.e. preferably above ITesla. As an alternative Ferrit can also be used even though the saturation point is lover typically around 0,5Tesla. Yet another alternative for the core of the inductor could be laminated steel if losses can be kept low.
    Preferably at 60/40 or 40/60 distribution of current between the first and second branch both non-linear inductors are saturated.
    In an advantageous embodiment of the invention the first output branch comprises a linear inductor and wherein the second output branch comprises a linear inductor wherein at least a part of the inductance of the linear inductors origins from one or more coreless inductors.
    The physical layout of the connections i.e. cables or rails of the power inverter are equivalent to an inductor of e.g. between 0,5 - 2 uH whereas the saturation type inductors are of several hundred uH (uH; Micro Henry) e.g. between 400 and 600 uH.
    If it is not possible to design the layout of the branches of the power inverter to have the desired inductive properties, then to reach the desired inductive linear properties a linear inductor is advantageously used to compensate for this and reach the desired inductive properties. Such adaption could e.g. be implemented by special cable design such as e.g. curl of a cable, extra length of a cable, etc.
    Coreless inductors are linear in that they do not saturated and may refer to an air coil inductor.
    In an advantageous embodiment of the invention when the inverter output current exceeds a first threshold current the inverter output current is divided between the first and second branch in each switching period.
    Hence below the threshold the power inverter is controlled according to the discontinued interleaving control method and above the threshold the power inverter is controlled according to the traditional control method. This is advantageous in that the active switch is in this way kept within the safe operation limit without increasing the capacity of the actives switch and thereby the cost of the switch. The threshold may be determined in the software of the control system or dynamically based on actual operation area, temperature, etc.
    In the traditional control method the power inverter output is divided by the branches of the power inverter in each switching period. Therefore if the power inverter output is 500amps there will in each switching period be 250amps in each branch. In the discontinued interleaving control method there will be 500amps in the each branch in each switching period but 0 in the subsequent switching period.
    In an advantageous embodiment of the invention when the inverter output current drops below a second threshold current the output current is carried by one of the first or second branch of the power inverter in a first switching period and by the other of the first or second branch of the power inverter in the subsequent switching period.
    In an advantageous embodiment of the invention the first predefined threshold is higher than the second predefined threshold.
    In an advantageous embodiment of the invention the threshold is above 50% of the maximum allowable instantaneous current of the power switch.
    This is advantageous in that in situations where an overcurrent occurs this will not damage the power switch. Instantaneous current may be safe operation area of the switch defined by the switch manufacture.
    In an advantageous embodiment of the invention the current is divided equal between first and second branches of the power inverter when the output current exceeds the first predefined threshold current.
    In an advantageous embodiment of the invention the first and second branches of the power inverter is controlled according to a Clamped Pulse Width Modulation signal.
    In an advantageous embodiment of the invention when no switching occurs in a predefined period of time the control strategy is changed to direct paralleling, wherein the predefined period of time is 500us.
    Hence when the power inverter enters a non-switching mode direct paralleling is immediately enabled.
    In an advantageous embodiment of the invention the current through at least one of the first branch and second branch is zero at least at a point in time during a switching period.
    In an advantageous embodiment of the invention the first branch power switches comprising first branch active power switches with parallel passive power switches and the second branch power switched comprising second branch active power switches with parallel passive power switches and wherein between two successive switching periods a commutation of current between the first branch active switch or the first branch passive switch and the second branch active switch or the second branch passive switch are obtained by - turning off at least one of the first branch active power switches and turning on at least one of the second branch active power switch to direct current from one of the first branch power switches to one of the second branch power switches and delaying the commutation of current from one of the first branch parallel passive switches to one of the second branch active power switches by either the first branch output inductance or the second branch output inductor thereby decreasing the reverse recovery losses / diode turn off losses during the commutation of current in the transition between the two successive switching periods.
    Delaying should be understood as slowing down the commutation of current from one branch to the other and slowing down or preventing reverse current flow in the diodes.
    Turning on / off a power switch should be understood as activating or deactivating the power switch so that either current can be conducted (turning on) or cannot be conducted (turned off) by the power switch i.e. the active power switch.
    More over the invention relates to a power inverter having a first branch which is electrical parallel to a second branch, the first branch comprising active switches and passive switches parallel to the active switches, the second branch comprising active switches and passive switches parallel to the active switches characterised in that the output of the first branch includes a linear inductor and a non-linear inductor and the second branch includes a linear inductor and a non-linear inductor wherein the nonlinear inductors is intended to saturate during operation of the power inverter.
    Linear inductor is preferably properties with cables etc. of the power inverter. Non-linear inductor is preferably a component which is added to the output of the first and second branch and which when saturated is having an inductance of e.g. less than 10% of the nominal inductance
    In an advantageous embodiment of the invention the non-linear inductor is having a non-saturated inductance of more than lOOuH.
    In an advantageous embodiment of the invention the saturation point of the first and second branch non-linear inductors is above 1 Tesla.
    In an advantageous embodiment of the invention the inductance of the linear inductors at least partly origins from one or more coreless inductors. Coreless inductor is preferably cable inductance
    Moreover the invention relates to the use of a power inverter according to any of the claims 20-23 and controlled according to the method of any of the claims 1-19 for use in a wind turbine
    Figures A few exemplary embodiments of the invention will be described in more detail in the following with reference to the figures, of which figure 1 illustrates a power inverter, figure 2 illustrates the output path of the power inverter of figure 1, figure 3a-d illustrates output of a power inverter controlled according to an embodiment of the present invention, figure 4a-b illustrates losses in a passive and in an active switches according to an embodiment of the present invention, figure 5a-b illustrates a shift between control of the power inverter of figure 1 according to the discontinued interleaving control method and the direct paralleling control method, figure 6 illustrates the commutation of current from a first branch to a second branch of a power inverter according to an embodiment of the invention, and figure 7a-b illustrates a control setup according to an embodiment to an embodiment of the invention.
    Detailed description of the invention
    Figure 1 illustrates a power inverter 1 with two parallel branches 2, 3 also referred to as half bridges. In a first switching period the first branch 2 is carrying the full power inverter current (referred to simply as full current) in the switching period. In the next switching period the full current is commutated to the parallel branch, the second branch 3, which now will lead the full current and so forth. This is in contrary to known current control of power inverters where the two branches 2, 3 would be carrying half of the full current continuously.
    The power inverter 1 illustrated in figure 1 is controlling one phase or part of one phase. If the current of a phase is above maximum capacity of the power inverter additional power inverts 1 as the one illustrated in figure 1 could be combined in parallel to produce a total power inverter output 12. This is illustrated in figure 2.
    As can be seen from figure 1 the design of the power inverter 1 is equal to traditional power inverters only the output 8, 9 deviates which will be discussed below. Therefore a first branch 2 comprising active switches 4a, 4b with passive switches (referred to as diodes) 6a, 6b coupled in parallel. Similarly the second branch 3 comprising active switches 5a, 5b with diodes 7a, 7b coupled in parallel. Output 8 of the first branch 2 is between the two active switches 4a, 4b and output 9 of the second branch 3 is between the two active switches 5, 5b.
    An active switch is preferably an IGBT (IGBT; Insulated Gate Bipolar Transistor) or a MOSFET (MOSFET; Metal-Oxide-Semiconductor Field-Effect Transistor). A passive switch is often a diode.
    The switching periods are defined in a control unit 22, 23 which is connected to the active switches 4, 5. A switching period is defined as a period in time controlled by the control unit 22, 23 and communicated to the first and / or second branch 1, 2 in which the active power switch of the branches should be on and / or off i.e. conducting or non-conducting current through that branch. Hence one switching period is defined as both a shift from low to high and from high to low i.e. one cycle in which both branches 2, 3 are conducting the full current. It should be mentioned that the switching period does not have to be split equal between the two branches 2, 3. Typically the switching periods are defined by pulse width modulation and communicated to the power inverter from the control unit 22, 23.
    The control unit 22, 23 may be an advanced gate drive control e.g. in the form of an interface between a converter controller or implemented in the power stack where the switches to be controlled is present. Alternative the control of the power module and thereby the discontinued interleaving control method or the direct paralleling hereof may be controlled from the converter controller which in such cases would be the box denoted 22, 23. This is also discussed in relation to figure 7.
    It should be mentioned that one branch may be implemented as a parallel connection of several branches which may be in the same physical enclosure (power module, power stack, etc.) or separated enclosures.
    Figure 2 illustrates a modification of the power inverter 1 of figure 1 which enables optimized operation of the power inverter 1 according to the inventive control method described in this document. In figure 2 the two parallel branches 2, 3 interfaces by means of two single phase inductances lOab, lOcd also referred to as inductors lOab, lOcd. These inductors are located in the branch outputs 8, 9.
    In an example the power inverter output 11 is 500amps, from a measurement of the power inverter output at arrow 11 it is not possible to determine which of the branches 2, 3 delivers the 500amps in that the full current is either provided by the first 2 or the second 3 branch.
    The inductors lOab, lOcd can basically be any type of inductors and could comprise of what may be referred to as a linear inductor 10b, lOd contribution and a non-linear inductor 10a, 10c contribution both types of contribution have effect according to the present invention.
    The linear inductor 10b, lOd contribution is mainly occurring from cable, rails or the like in the physical design of the power inverter 1. The size of this linear inductor 10b, lOd according to the present invention should preferably be less than 2-5uH and simulations has shown that sizes around 0,5uH may be sufficient. The magnitude of the linear inductor 10b, lOd is at least partly determining the commutation time of current from one branch of the power inverter to another which will be explained in more details below. One reason for keeping the inductance of the linear inductors 10b, 10d low is that commutation time of the current will lead to an increased distortion of the voltage output. In addition the linear inductor will increase slow down the current sharing when enabling direct paralleling.
    The non-linear inductor 10a, 10c contribution occurs from a physical inductor connected in or to the output 8, 9 of the branches 2, 3. The non-linear inductors 10a, 10c are of much higher inductance value than the linear inductors 10b, lOd preferably they are above lOOuH and designed to saturate. This property of the nonlinear inductor 10a, 10c is important according to the present invention and will be explained below.
    Together the non-linear 10a, 10c and the linear 10b, lOd inductor are referred to as inductor lOab, lOcd in this document.
    The full current is also referred to as the power inverter output 11 and could be measured at the reference mark 11 of figure 2. It is preferred that the full current through a power inverter 1 in the hole switching period is only running in one branch preferably at least at one point in time during a switching period the full current 11 should be conducted by one branch alone. Further figure 2 illustrates that a plurality of power inverters 1 may be paralleled conducting current of the same phase. The accumulated power inverter outputs 11 of the paralleled power inverters 1 may together be referred to as the total phase output 12
    Figures 3a - 3d clearly illustrate the difference of the inventive control method (referred to as discontinues interleaving) and the traditional control method. In figure 3a the current output 8, 9 through the branches 2, 3 is illustrated and compared to figure 3b illustrating the output 11 of the power inverter 1. It is seen that each branch 2, 3 carries the full current 11 of just above 300 amp. This is in contrary the traditional control method where in figure 3c it is illustrated that each branch carries only half (i.e. 200 amp) the full current (i.e. 400 amp) illustrate in figure 3d.
    It should be mentioned that at figure 3 a the curves 8 and 9 each comprise two peaks before the next branch is conducting.
    The effect of controlling according to the discontinued interleaving method is that active switches 4, 5 is turned on (ideally) at zero current and that the current in the antiparallel diodes 6, 7 is being driven out slowly, reducing the impact of reverse recovery phenomenon of the diodes 6, 7. In the ideal case there will be no (or at least very low) reverse recovery losses in the diodes 6, 7 and no (or at least very low) turn on loss in the active switches 4, 5.
    This is illustrated in figure 4a and 4b. Figure 4a illustrates a comparison of the diode power loss and figure 4b illustrates a comparison of the active switch power loss between traditional control and the new discontinued interleaving control method. Figures 4a and 4b is made by pulse testing during switching an inductor of 105-210uH, Ae of 10,35cm2 and a Bsat of around 1,2 Tesla at 1000VDC.
    From figure 4a it is seen that the loss 13 in the diode 6, 7 traditional controlled is much higher than the loss 14 in the diode 6, 7 controlled according to discontinued interleaving method. This is mainly due to the fact that the inductor prevents flow of reverse current in the diode and thereby allows the charges in the diode to recombine.
    From figure 4b it is seen that the active switch 4, 5 turn on loss 15 traditional controlled is much higher than the loss 16 in the active switch 4, 5 controlled according to the discontinued interleaving method. This is mainly due to fact that the switching of the active switch 4, 5 is done in the phase where current commutates from one branch to another and therefore the load current on the active switch to be turned on is low leading to less loss.
    As can be seen from figure 4b the turn off loss 17 is mainly linear in respect to the current. Due to the fact that the current through the active switches 4, 5 in the discontinued interleaving control is twice the current as in the traditional way the turnoff loss is also twice as high. However since the active switches 4, 5 only carries current every second switching period the average of the turnoff losses are approximately the same for the discontinued interleaving and the traditional control methods.
    Hence even though at first glance one could expect a doubling in turnoff losses when the current through the active switch 4, 5 is doubled then due to the inventive discontinued interleaving control method this is not the case.
    What is a drawback of the doubling of current through the switches 4, 5, 6, 7 in the discontinued interleaving control method is the conduction losses in the switches 4, 5, 6, 7. The conduction losses will increase in that the current through the switches 4, 5, 6, 7 is increased. Whereas conduction losses are appearing in all the power switches 4, 5, 6, 7, the turn on and turn off losses are only seen in the active switches 4, 5 e.g. the IGBT and the reverse recovery losses is only seen in the passive switches 6, 7 i.e. the diodes. With this said the reverse recovery losses may also be referred to as diode turn-off loss and occurs at the same time as the turn-on loss of the active switch 4, 5.
    Beside the size of the current the conduction losses also depend on the type of switch 4, 5, 6, 7. This is illustrated with the following example of calculation of the voltage drop over an active switch in the discontinued interleaving control method and in the direct parallel mode (also referred to as the traditional control mode).
    At a given power inverter output 11 of e.g. 600A each parallel active switch will experience 300A in the continuous operation mode (also referred to as the traditional control mode). By looking up in a data sheet of an active switch this will give a voltage drop of approx. 2V at 150 deg. In the discontinuous interleaving control mode the current in the active switch 4, 5 will be 600A, leading to a voltage drop of approx. 3V at 150 deg. This obviously gives higher conduction losses, but the reduction in switching losses will make the total losses lower, depending on e.g. the actual current, switching frequency, modulation index, DC voltage, properties of the individual power module and temperature. Actual loss comparison between discontinued interleaving control method and the traditional control mode depend on current and type of switch 4, 5, 6, 7 but generally the conduction losses will increase when using the discontinued interleaving control method.
    Concluding on losses one can say that switching losses are reduced but conduction losses are increased when operating in the discontinued interleaving control method and the higher the switching frequency, the higher the gain of discontinued interleaving control method.
    At high current (not overcurrent) and / or low switching frequency the discontinued interleaving control method may have combined losses (switching losses and conduction losses) which are higher than similar losses in the traditional control also referred to as direct paralleling. Therefore in relation to optimization of power losses one may enter direct paralleling in the top area of e.g. a sinusoidal current curve.
    Another problem which must be addressed when using the discontinued interleaving control method is overcurrent. When running the discontinuous interleaving strategy, the current (when conducting) in each switch 4, 5, 6, 7 will be twice as high compared to the current in the switched controlled by the traditional control strategy. This will reduce the margin to maximum allowable instantaneous current of the switch 4, 5, 6, 7 i.e. the hardware limit of the switch 4, 5, 6, 7.
    The immediate consequence hereof is that an active switch 4, 5 capable of carrying a higher current must be chosen if discontinued interleaving control method is chosen.
    In normal operation mode of the power inverter 1 i.e. where there is not fault in relation to the power inverter nor in relation to components connected hereto such as e.g. a generator of a wind turbine at one side and a utility grid on the other side, the current is typically low enough to leave a sufficient margin to maximum allowable current. But in case of a transient overcurrent, the actual output current 11 will approach the maximum allowable current of the power switch. In order to overcome this challenge, the discontinued interleaving control method should be disabled when a certain threshold current is reached. When output current 11 again is below the threshold current, the discontinued interleaving control method is enabled again. During the period in which the discontinued interleaving control method is disabled the traditionally direct paralleling control method is enabled.
    This is illustrated at figure 5a and 5b where a first threshold 18 of 700amps and a second threshold 19 of 600amps are defined with reference to the output current of the power inverter. Figure 5A illustrates the shift from discontinued interleaving control method to direct paralleling control method when the output current 11 is exceeding the first predefined threshold 18. Further the shift from direct paralleling control method to the discontinued interleaving control method when the output current 11 is falling below the second predefined threshold 19. Figure 5b illustrates the inverter output current 11.
    It should be mentioned that the value of the first and second thresholds 18,19 may be the same. These threshold currents 18, 19 may be fixed in the hardware implementation or in the control software. In the latter case the thresholds 18, 19 may be changed either manually or adaptive by the control software as a function of the actual operation parameters such as DC voltage, temperature, etc.
    During the time period T1 the inverter output 11 is below 700amps and thereby the output of the branches 8, 9 and thereby the current through the power switch 4,5,6,7 is below 700amps. The control method in period T1 is discontinued interleaving.
    During the time period T2, the inverter output 11 exceeds 700amps and the control method changes mode to direct paralleling in which the two branches 2, 3 shares preferably equal but not necessary the inverter output current 11.
    During the time period T3 the inverter output 11 falls below 600amps and the control method changes again to direct interleaving. In the same way the control method changes in period T4 and T5.
    When an overcurrent is detected the direct paralleling control method may be chosen to keep for some time, until the overcurrent situation is gone. A typical situation for this type of operation is e.g. a low voltage ride through incident where a short-time overcurrent will occur. Low voltage ride through is especially a requirement to power inverters used in the wind turbine industry and is known by the skilled person.
    The switching losses in the power switches 4, 5, 6, 7 will be higher when entering direct paralleling control mode since there will be tum-on and reverse recovery losses. From a thermal point of view such change in control methods can typically only be allowed for a short period of time, but may be required in some situations to increase the margin to the instantaneous maximum current.
    Power losses in a three phase power inverter system can be reduced by controlling the branches of the power inverter by introducing periods without switching of the active switches. In three phased systems this could e.g. be utilized by a common 60 degree clamping strategy or other strategies introducing longer periods without switching in one or more phases. In order to optimize the power losses in the switches 4, 5, 6, 7 it will typically be beneficial to enter direct paralleling in the phase where there is no switching. When leaving the period of non-switching in the phase one would typically go back the discontinued interleaving control method in order to reduce the switching losses.
    If the parallel active switches 4, 5 are turned on with some microsecond delay (if switch 4 is active there is a delay to activation of switch 5 and vice versa) the system will automatically enter direct paralleling after some time depending on the properties of the inductors 10. The time required for entering direct paralleling is determined by the voltage drop of the active switches 4, 5 and the property of the inductors. Thereby is obtained an automatically shift to direct paralleling in that both switches are active. The property of the inductances 10 facilitates a delay in when the main part of the current will start to share between the parallel switches in this situation switch 4a, 5a. Hence direct paralleling is obtained. With proper design of the inductances lOab, lOcd the system can be optimized in relation to when the system in this way shifts to direct paralleling.
    Now returning to the inductors more specific the non-linear saturation inductors 10a, 10c hereof of which the main effects of these are. Suppress reverse current flow in active diode during commutation i.e. shift from one branch 2, 3 to another and thereby letting the active diode 6, 7 recombine internally. This reduces (or eliminates) the losses associated with reverse recovery. Further, suppress current flow from active diode 6, 7 to parallel diode 6, 7 (inactive) during conduction period. For control reasons parallel IGBTs may be turned on as described above. If so, the same applies to parallel IGBTs as for diodes). Further, low inductance when entering clamped PWM or overcurrent situation, when branches are to be driven in the direct parallel control mode.
    The inductances 10a, 10c may consist of toroid cores mounted on a copper bar. It could also be designed as a core with several turns in the winding. The cores may be made of any magnetic material preferably having a high saturation point (above 1 Tesla). Ferrite or other low permeability materials may also be used, but has a lower saturation point (typically below 0.5 Tesla).
    The saturation of the inductance is reached when the magnetic flux density reaches a certain value, e.g. 1.2 Tesla (the actual saturation point is a smooth continuous point, not a fixed value). The flux in the core is determined by the time integral of voltage divided by the cross sectional area of the core and number of turns. Examples of calculating the time from voltage is applied across the non-linear inductors 10a, 10c to these inductors saturates are given in the following:
    B=flux density (Tesla) V=voltage
    Ae= cross sectional area of core N= turns (1 for copper bar)
    As an example each core has the basic properties:
    Saturation point 1.2 Tesla
    Inductance > 70 uH (giving total inductance for 15 cores of more than ImH)
    With 15 cores the time to saturation can be calculated for 1.5V and 1000V as below: Constant 1.5V case:
    Constant 1000V case:
    An example of impact on the inductors of the output 8, 9 of the branches 2, 3 of the power inverter will now be describe with reference to figure 6. The voltage across the non-linear commutation inductance 10a, 10c is high, e.g. 1000V. This means that the current driving “force” is high. But suppression of current flow is only required in a few microseconds, to let the diode 6, 7 internally recombine charge carriers.
    In the example a low side diode 6b of the first branch 2 has been conducting the full current. Then high side active switch 5a in the second branch 3 is turned on. There will now be a commutation between the branches (from first branch 2 to the second branch 3). Hence this example describes the commutation between branches 2, 3.
    In the situation illustrated in figure 1 and figure 2 the inductances 10a, 10b at the first branch output 8 are carrying the full current, and the non-linear inductor 10a is saturated. This means that, when an active switch of second branch 5a, 5b e.g. switch 5a is turned on, the full voltage potential lies on the second branch 3 inductances 10c, lOd (which is unsaturated). If the non-linear inductances 10a, 10c are of high value i.e. several hundred uH (micro Henry), a very low current starts to flow from the second branch 3 until non-linear inductor 10c saturates. This translates into a delay for the current commutation (see phase PI of figure 6).
    After this period both non-linear inductors 10a, 10c of the first and second branches are saturated and current is rapidly transferred from the first branch 2 to the second branch 3. The current slope in this period is determined by the linear inductors 10b, lOd which is not saturable (see phase P2 of figure 6).
    When most of the current is commutated to the second branch 3, the first branch nonlinear inductor 10a goes out of saturation, meaning it enters high inductance area. This suppresses current flow in reverse direction into the diode 6b of the first branch 2 (see phase P3 of figure 6).
    In the period where the current flow in diode 6b of the first branch 2 is close to zero (a few amperes), the charge carriers in the diode 6b will start to recombine. If time is sufficient, the diode will totally recombine. After some time (few micro seconds) the non-linear inductor 10a of the first branch 2 enters saturation. If the diode 6b is not fully recombined at this time, there will be a reverse current in the diode 6b (see phase P4 of figure 6). A figure 6 the curve 20 illustrates the current through diode 6b if the power inverter is controlled traditionally with direct paralleling i.e. sharing the output 11 equally between the first and second branch 2, 3 in each switching period. Curve 21 illustrates the current through diode 6b when the power inverter 1 is controlled according to the present invention. Curve 22 illustrates voltage across the diode 6b during traditional control and curve 23 illustrates voltage across the diode 6b during control according to the present invention.
    Comparing the waveforms of the curves 20 and 21 it can be seen that the peak current of the curve 20 is much higher than at the curve 21 (peak values of approx. 750A vs 150A). Also the curve 20 has a long tail after it peak value. The total diode turnoff energy is the integral of the product of voltage and current, which is much higher for curve 20 x curve 22 (traditional switching strategy of the power inverter) compared to the curve 21 x curve 23 (switching strategy of the present invention).
    Above the saturation time of the non-linear inductors 10a, 10c was calculated for the 1000V case. With 15 cores the time to saturation with 1000V DC is approximately 1.6us. Phase P3 of figure 6 is very close to 2*1.6us~3.2 us, this is because during phase P3 the core of the non-linear inductors 10a of the first branch 2 experience both positive and negative current, giving twice the value.
    During phase PI the time would have been 1.6 us if the current in the core of the non-linear inductor 10c of the second branch 3 was 0A at this stage. There may be a small current flowing, therefor the exact delay cannot be read.
    As can be seen from figure 6 the control method of the present invention (referred to as a discontinued interleaving switching pattern) will lead to a delay of the output voltage curve 23, compared to the normal case curve 22. Also, the linear inductors 10b, 10c commutation phase P2 will give a voltage level at the output approx. A of VDC. In total this may lead to a distortion on the output voltage, however this disadvantage of the present invention may be compensated for in the control logic.
    Now returning to figure 1 and figure 2 describing a situation where current flows through one branch i.e. a condition mode. When the diode 6a, 6b, 7a, 7b of one branch 2, 3 conducts the full output current it is not desired that the parallel diode (diode 6a and 7a is parallel and diodes 6b and 7b is parallel) is sharing the current (before turning on an active switch of the non-current conducting branch).
    The full current should flow e.g. in diode 6b of the first branch 2 until the active switch 5a of the second branch 3 is turned on (commutation between branches as described above in relation to figure 6).
    When diode 6a, 6b of the first branch 2 conducts e.g. 500A, and the second branch 3 conducts a current close to 0 A, there will be a voltage difference between the first and second branch 2, 3 of approx. 1,5V. In addition there will be voltage drop in cables etc, which may give a total voltage drop higher than the 1.5V. This voltage drop depends on the power inverter module and can be found from data sheets of the power modules for power inverters.
    The voltage difference between the first and second branch 2, 3 will start to drive a current into the second branch 3 at the rate di/dt=U/L (di/dt= current ramp as function of time, U=voltage, L=inductance). In case of only cable inductance of 2*luH, the current flow from the first branch 2 to the second branch 3 will be di/dt=1.5/2uH=0.75A/uS. In case of a switching frequency of 2.5 kHz and 50% dutycycle the conduction time for the diode is 200 us. This translates into a current in second branch 3 after 200 us of 150A (this number is also taken from a data sheet of a power module for a power inverter 1). This will lead to large reverse recovery losses in the diode 7b of the second branch 3 when the active switch 5a of the second branch 3 turns on. The data sheet used above relates to a Fuji 550A power module, power module should be understood as an enclosure typically comprising a plurality of semiconductor chips also referred to as power switches.
    On the other hand if an inductance of e.g 500 uH is present, the current in the second branch 3 diode 7b will only be 1.5/500uH*200us=0.6A, and there is virtually no reverse recovery losses of diode 7b when active switch 5a is turned on.
    The non-linear saturable inductance 10a, 10c of very high inductance (several hundred) will suppress current flow into parallel diode during the conduction mode. As in the commutation between branches above the non-linear saturable inductance 10a, 10c will also saturate at some point. At 1.5V and 15 cores the saturation point will be reached after approx. 1 ms, which is much less than the maximum 400us conduction time for a 2.5 kHz system.
    In the following considerations in relation Discontinued PWM control and safe operation margin will be described. When entering a Discontinued PWM constant conduction or overcurrent it is desirable to shift to the direct paralleling where the two parallel branches 2, 3 conducts the load current equally. The reason for this could either be to reduce losses in Discontinued PWM or to have a sufficient margin to Safe Operation Area for the power switches 4, 5, 6, 7 at high current.
    As described above the saturable non-linear inductor 10a, 10c reaches saturation after some time when in conduction mode i.e. after e.g. 40% of the full current is commutated from one branch to the other. When entering the traditional control strategy referred to as direct parallel mode there will be a delay before the parallel branches 2, 3 shares the current equally. The delay is determined by the difference in voltage of the two branches 2, 3, the non-linear inductance’s 10a, 10c saturation level and core area hereof and linear inductance 10b, lOd, as described above. The voltage driving the flux in the cores of the non-linear inductors 10a, 10b is the voltage difference between the branches 2, 3. When entering the high current mode the voltage difference will automatically start to rise, driving the cores into saturation faster and thereby helping to switch from the discontinued interleaving to the direct paralleling control strategy.
    The design of the non-linear saturation inductance 10a, 10c is a compromise between having as low losses as possible, suppressing parallel current during the conduction mode, but still have a relatively fast response when entering direct paralleling control strategy. The linear cable inductance 10b, lOd will typically be kept as low as possible.
    As an example if 1000V is applied it will take about 5us before the inductor is saturated. The longer time before saturation the less turn off loss in the diode 6, 7 in that the diode them have more time to recombine. Typically the largest part of the recombination takes place in the first 1-1 Ous and the following 90us not much happens but this depends on the type of diode.
    It should be mentioned that saturation cannot typically be measured in one specific point but is seen e.g. on a graph as a series of continues points smoothening a comer of the graph around the saturation point.
    Hence the present invention is advantageous in that the current in the diode antiparallel to the current carrying power switch is driven out slowly which reducing reverse recovery losses. In the ideal case there will be no losses related to reverse recovery. An example of an ideal case would be when the inductor saturates and thereby keeping the current (ideally) at zero amp for a time which is sufficient for the diode to recombine completely. This ideal situation will lead to no reverse recovery loss.
    In relation to control of the power inverter 1 and thereby the above described new and traditional control strategies it should be mentioned that conventional data processors and logic circuits such as FPGAs or CPLDs may be suitable. This means that it is possible to construct an interface device getting input from the original power inverter control, process these data and output new control signals to the power inverter 1. Thereby the power inverter 1 is controlled according to the present invention. Such program logic may also be implemented in the power stacks directly eliminating the need of an interface box.
    Figure 7a and 7b illustrates different control setups enabling controlling the switches and especially the active switches 4, 5 of the branches 2, 3 of the power inverter 1. Figure 7a illustrates a converter controller 22 communicating directly with gate drivers 23 of the power inverter 1. In this illustration the control of the discontinued interleaving control method is implemented as part of the converter control 22. The converter controller 22 is therefore communicating with the gate drivers 23 in order to control the active switches 4, 5 as described above.
    Figure 7b illustrates another way of implementing the discontinued control method. As illustrated a gate driver controller 24 is inserted between the converter controller 22 and the gate drivers 23. In this implementation the discontinued interleaving functionality may be placed in the gate driver controller 24 which therefore may function as an interface module between the converter controller 22 and the gate drivers 23. This is advantageous in that by such interface module the discontinued interleaving control method could be retrofitted into existing power inverters.
    As can be understood from the above the present invention enables optimized control of power inverters in relation to losses and hardware limits using a combination of the discontinued interleaving control method and the direct paralleling control method on one or more paralleled power inverters conducting current of the same phase.
    It should be mentioned that a power inverter 1 and control hereof could be used in a wind turbine to optimise the overall yield of the wind turbine by reducing losses in the power converter of the wind turbine. But the power inverter 1 and control hereof may be used in any application where power inverters are used.
    Further it should be mentioned that where referred to power switch 4 a reference is made to both the first and second active power switch of the first branch 4a and 4b. This way of interpretation of references is also used with other reference numbers to ease reading of this document.
    List of reference numbers 1. Power inverter 2. First branch 3. Second branch 4. Active switch of first branch a. First active switch of first branch b. Second active switch of first branch 5. Active switch of second branch a. First active switch of second branch b. Second active switch of second branch 6. Passive switch of first branch a. First passive switch of first branch b. Second passive switch of first branch 7. Passive switch of second branch a. First passive switch of second branch b. Second passive switch of second branch 8. First branch output 9. Second branch output 10. Output inductors a. First branch output non-linear inductor b. First branch linear (cable) inductor c. Second branch output non-linear inductor d. Second branch linear (cable) inductor 11. Power inverter output 12. Total phase output 13. Curve illustrating losses in passive switch traditionally controlled 14. Curve illustrating losses in passive switch controlled according to the present invention 15. Turn on losses in active switch traditionally controlled 16. Turn on losses in active switch controlled according to the present invention 17. Turn off losses in active switch 18. First threshold for shifting control method 19. Second threshold for shifting control method 20. Current traditional control 21. Current discontinued interleaving control 22. Converter controller 23. Gate driver 24. Gate drivers controller
    权利要求:
    Claims (24)
    [1] 1. A method of controlling the current within a power inverter 1, the power inverter 1 comprising at least a first branch 2 parallel to a second branch 3, wherein at least one power switch of the first branch 4 is carrying at least 60% of the full current of the power inverter 1 in a first switching period and at least one power switch of the second branch 5 is carrying at least 60% of the full current of the power inverter 1 in a subsequent switching period.
    [2] 2. A method according to claim 1, wherein at least one power switch of the first branch 4, 6 is carrying at least 90% preferably 100% of the full current of the power inverter 1 in a first switching period and at least one power switch of the second branch 5, 7 is carrying at least 90% preferably 100% of the full current of the power inverter 1 in a subsequent switching period.
    [3] 3. A method according to claim 1 or 2, wherein within the first switching period after a delay of a predefined time from activating an active switch of the first branch 4a, 4b, an active switch of the second branch 5 a, 5b is activated.
    [4] 4. A method according to any of the preceding claims, wherein one or more parallel power inverters 1 provides a total phase output 12.
    [5] 5. A method according to any of the preceding claims, wherein the first branch output 8 includes a first output branch inductance lOab and the second branch output 9 includes a second branch output inductance lOcd and wherein the accumulated current through the first and second output branch inductances lOab and lOcd is the power inverter output 11.
    [6] 6. A method according to claim 5, wherein the first and second branch inductances lOab, lOcd comprises non-linear inductors 10a, 10c having a non-saturated inductance of more than 50uH.
    [7] 7. A method according to any of the claims 5-6, wherein the time from voltage is applied to at least one of the first and second inductors 10a, 10c to at least one of the first and second non-linear inductors 10a, 10c saturates is less than 15us, preferably lOus, most preferably 5us
    [8] 8. A method according to any of the claims 5-7, wherein the saturation point of the first and second branch non-linear inductors 10a, 10c is above 1 Tesla.
    [9] 9. A method according to any of the claims 5-8, wherein the core of the first and second branch non-linear inductors 10a, 10c is at least partly made of one of the list comprising: an amorphous magnetic material, nanocrystalline magnetic material, ferrite or laminated steel.
    [10] 10. A method according to any of the preceding claims, wherein the first output branch 8 comprises a linear inductor 10b and wherein the second output branch 9 comprises a linear inductor lOd wherein at least a part of the inductance of the linear inductors 10b, lOd origins from one or more coreless inductors.
    [11] 11. A method according to any of the preceding claims, wherein when the inverter output current 11 exceeds a first threshold current 18 the inverter output current 11 is divided between the first and second branch 2, 3 in each switching period.
    [12] 12. A method according to claim 11, wherein when the inverter output current 11 drops below a second threshold current 19 the output current 11 is carried by one of the first or second branch 2, 3 of the power inverter 1 in a first switching period and by the other of the first or second branch 2, 3 of the power inverter 1 in the subsequent switching period.
    [13] 13. A method according to claims 11-12, wherein the first predefined threshold 18 is higher than the second predefined threshold 19.
    [14] 14. A method according to any of the claims 11-13, wherein the threshold is above 50% of the maximum allowable instantaneous current of the power switch.
    [15] 15. A method according to any of the claims 12-14, wherein the current is divided equal between first and second branches 2, 3 of the power inverter 1 when the output current 11 exceeds the first predefined threshold current 18.
    [16] 16. A method according to any of the preceding claims, wherein the first and second branches 2, 3 of the power inverter 1 is controlled according to a Clamped Pulse Width Modulation signal.
    [17] 17. A method according to claim 16, wherein when no switching occurs in a predefined period of time the control strategy is changed to direct paralleling, wherein the predefined period of time is 500us.
    [18] 18. A method according to any of the preceding claim, wherein the current through at least one of the first branch 2 and second branch 3 is zero at least at a at a point in time during a switching period.
    [19] 19. A method according to any of the preceding claims wherein the first branch power switches 4, 6 comprising first branch active power switches 4a, 4b with parallel passive power switches 6a, 6b and the second branch power switched 5, 7 comprising second branch active power switches 5a, 5b with parallel passive power switches 7a, 7b, and wherein between two successive switching periods a commutation of current between the first branch active switch 4 or the first branch passive switch 6 and the second branch active switch 5 or the second branch passive switch 7 are obtained by - turning off at least one of the first branch active power switches 4a, 4b and turning on at least one of the second branch active power switch 5a, 5b to direct current from one of the first branch power switches 4, 6 to one of the second branch power switches 5, 7, and delaying the commutation of current from one of the first branch parallel passive switches 6a, 6b to one of the second branch active power switches 5a, 5b by either the first branch output inductance lOab or the second branch output inductor lOcd thereby decreasing the reverse recovery losses / diode turn off losses during the commutation of current in the transition between the two successive switching periods.
    [20] 20. A power inverter having a first branch 2 which is electrical parallel to a second branch 3, the first branch comprising active switches 4 and passive switches 6 parallel to the active switches 4, the second branch comprising active switches 5 and passive switches 7 parallel to the active switches 5 characterised in that the output of the first branch 8 includes a linear inductor 10b and a non-linear inductor 10a and the second branch 9 includes a linear inductor lOd and a non-linear inductor 10c wherein the non-linear inductors 10a, 10c is intended to saturate during operation of the power inverter 1.
    [21] 21. A power inverter according to claim 20, wherein the non-linear inductor 10a, 10c is having a non-saturated inductance of more than lOOuH.
    [22] 22. A power inverter according to any of the claims 20-21, wherein the saturation point of the first and second branch non-linear inductors 10a, 10c is above 1 Tesla.
    [23] 23. A power inverter according to claim 20, wherein the inductance of the linear inductors 10b, lOd at least partly origins from one or more coreless inductors.
    [24] 24. Use of a power inverter according to any of the claims 20-23 and controlled according to the method of any of the claims 1-19 for use in a wind turbine.
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    同族专利:
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    DK178696B1|2016-11-21|
    引用文献:
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    DKPA201570269A|DK178696B1|2015-05-07|2015-05-07|Discontinued interleaving based control of a power inverter|DKPA201570269A| DK178696B1|2015-05-07|2015-05-07|Discontinued interleaving based control of a power inverter|
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