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    • 专利摘要:
    The present invention relates to a distance sensor (1A) which reduces a difference in the amounts of current supplied to each of the plurality of charge collecting regions provided for a photosensitive region to avoid saturation caused by stray light. A current injecting circuit (20) which feeds current to each charge collecting region includes a voltage generating circuit which generates a control voltage for adjusting the amount of current supplied, and the voltage generating circuit generates the control voltage corresponding to a large amount of charge between the charge amounts of storage nodes respectively connected to the charge collection regions are coupled. Meanwhile, a cascode device is disposed between a transistor configured to adjust the amount of current corresponding to the control voltage and the storage node, and a potential of a current output end of the transistor and a potential of the storage node are disconnected.
    公开号:CH713890B1
    申请号:CH01288/18
    申请日:2017-04-19
    公开日:2019-07-15
    发明作者:Akihiro Shimada；Mitsuhito Mase；Jun HIRAMITSU；Takashi Suzuki
    申请人:Hamamatsu Photonics Kk；
    IPC主号:
    专利说明:

    description
    Technical Field The present invention relates to a distance sensor.
    Background Art A time-of-flight method (TOF method) for measuring a distance to an object based on a time difference between a timing of irradiating pulsed light from a light source and a time when reflected light from the object is reached has been known , For example, the following Patent Document 1 describes a distance sensor based on a TOF method. The distance sensor disclosed in Patent Document 1 has a configuration of a charge distribution type in which charges generated in a photosensitive area during a first period after the light irradiation and charges in the photosensitive area during a second time period after the first time period are stored in storage nodes which are each coupled to different charge collection areas. Subsequently, the distance to the object is calculated from a ratio of the amounts of charge stored in these storage nodes. Moreover, the distance sensor disclosed in Patent Document 1 includes means for injecting current into each of the storage nodes to prevent saturation by an interfering light component.
    References
    Patent Literature [0003] Patent Document 1: German Patent Application Publication No. Hei. 102005056774
    Summary of the invention
    Technical Problem As a result of the examination of the above-mentioned prior art, the inventors have found the following problems. That is, some distance sensors having the configuration of a charge distribution type inject the current into the storage nodes respectively coupled to the charge collection regions to prevent the saturation caused by the disturbance light component (see Patent Document 1). In such a system, it is desirable to accurately control the amount of current injected into the storage nodes to a uniform size. This is because the result of calculating the distance to an object causes an error when the amounts of current supplied to the storage nodes coupled to the different charge collection areas, respectively, vary.
    The present invention has been made to solve the above-described problem, and an object thereof is to provide a distance sensor capable of reducing a difference in the amount of current fed into storage nodes, respectively are coupled to different charge collection areas provided for a photosensitive area. Solution to the Problem A distance sensor according to the present invention is configured to irradiate an object with light and to measure a distance to the object by detecting reflected light from the object, and includes a semiconductor substrate, first and second transfer electrodes, a voltage generating circuit , a first and second transistor, a third transistor and a fourth transistor to solve the above problem. The semiconductor substrate has a photosensitive region that generates charges corresponding to a light amount of the reflected light and first and second charge collection regions that respectively collect the charges from the photosensitive region. Incidentally, the first and second charge collecting regions are individually arranged in the state of separation from the photosensitive region by a predetermined distance. The first transfer electrode is an electrode configured to control charge transfer from the photosensitive region to the first charge collection region and disposed on a region between the photosensitive region and the first charge collection region. Moreover, the first transfer electrode is set at an on-potential, which allows the charge exchange during a first period after the irradiation with light, and set to an off-potential, which stops the charge exchange during a second period following the first period. The second transfer electrode is an electrode configured to control charge transfer from the photosensitive region to the second charge collection region, and disposed on a region between the photosensitive region and the second charge collection region. In addition, the second transfer electrode is set to the off-potential during the first period and to the on-potential during the second period. The voltage generating circuit has one end electrically connected to a first constant potential line set to a predetermined potential and the other end electrically connected to a second constant potential line to a lower potential than the first constant potential Line is set. The
    A voltage generating circuit generates a control voltage corresponding to a larger one between a charge amount stored in a storage node electrically coupled to the first charge collection region and an amount of charge stored in a storage node electrically coupled to the second charge collection region. Each first and second transistor has a control terminal to which the control voltage is applied, a first current terminal connected to the first constant potential line, and a second current terminal. The third transistor has a first power terminal connected to the second power terminal of the first transistor, a second power terminal connected to the storage node electrically coupled to the first charge collection area, and a control terminal to which a constant voltage is applied becomes. The fourth transistor has a first power terminal connected to the second power terminal of the second transistor, a second power terminal connected to the storage node electrically coupled to the second charge collection area, and a control terminal to which a constant voltage is applied becomes.
    Advantageous Effects of Invention According to the distance sensor of the present invention, a cascode device is disposed between a transistor and the storage node, and the transistor that adjusts the amount of current in accordance with the control voltage generated based on the charge amounts of the storage nodes, respectively A plurality of charge collection regions is prepared, which are prepared for a photosensitive region, and wherein a potential of a current output end of the transistor and a potential of the storage node are separated. Thereby, it is possible to reduce a difference in the amount of injected current between the storage nodes respectively coupled to the charge collection areas.
    Brief Description of the Drawings [0008]
    FIG. 1 is a plan view illustrating a configuration of a distance sensor according to an embodiment of the present invention. FIG.
    Fig. 2 is a plan view of a light receiving unit of each pixel of the distance sensor shown in Fig. 1.
    FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2. FIG.
    FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 2. FIG.
    Fig. 5A is a diagram illustrating an example of a temporal change of the intensity of the reflected light incident on a particular pixel; Fig. 5B is a diagram illustrating a time change of a voltage applied to a transfer electrode, and Fig. 5C FIG. 12 is a diagram illustrating a time change of a voltage applied to a transfer electrode.
    6 is a view illustrating a drive system of an imaging area using a sensor control circuit.
    Fig. 7A is a timing chart showing the operations of transfer electrodes in a memory frame of a first frame, and Fig. 7B is a timing chart illustrating the operations of the transfer electrodes in a storage frame of a second frame.
    Fig. 8 is a view showing time charts of the first frame and the second frame for a one-time clocking in an overlapping manner.
    9 is a view further illustrating a diagram of the received light pulse waveforms of the reflected light in the time chart shown in FIG. 8.
    FIG. 10 is a view further illustrating a diagram of the received light pulse waveforms of the reflected light in the time chart shown in FIG. 8.
    11 is a circuit diagram illustrating a configuration of a current injection circuit according to an embodiment.
    FIG. 12 is a circuit diagram illustrating a configuration of a current injection circuit according to a comparative example. FIG.
    13A is a diagram illustrating an example of a time change of a voltage value (Potenti) of each storage node in the current injection circuit according to the comparative example, and FIG. 13B is a diagram showing an example of a change with time of the amount of the feed Represents current to each storage node in the current injection circuit according to the comparative example.
    14A is a diagram illustrating an example of a time change of a voltage value (potential) of each storage node in the current injection circuit according to an embodiment, and FIG. 14B is a diagram indicating an example of a temporal change of the amount of the injected current represents each storage node in the current injection circuit according to an embodiment.
    FIGS. 15A and 15B are views illustrating a timing chart of a driving method according to a first change.
    Figs. 16A to 16C are views for describing a distance calculating method according to the first modification.
    Fig. 17 is a plan view illustrating a light receiving unit according to a second modification.
    FIG. 18 is a cross-sectional view taken along the line XVIII-XVIII of FIG. 17. FIG.
    Fig. 19 is a view illustrating a drive system of a sensor drive circuit according to the second Modi fication.
    Fig. 20 is a timing chart illustrating the operation of a transfer electrode in a storage frame.
    DESCRIPTION OF EMBODIMENTS [Description of Embodiments of the Invention of the Present Application]
    First, those corresponding to the embodiments of the invention of the present application are individually listed and described.
    (1) A distance sensor according to the present embodiment is configured to irradiate an object with light and measure a distance to the object by detecting reflected light from the object, and as an aspect thereof includes a semiconductor substrate, first and second Transfer electrodes, a voltage generating circuit, a first and second transistor, a third transistor and a fourth transistor. The semiconductor substrate has a photosensitive region that generates charges corresponding to a light amount of the reflected light and first and second charge collection regions that respectively collect the charges from the photosensitive region. Incidentally, the first and second charge collecting regions are individually arranged in the state of separation from the photosensitive region by a predetermined distance. The first transfer electrode is an electrode configured to control charge transfer from the photosensitive region to the first charge collection region and disposed on a region between the photosensitive region and the first charge collection region. Moreover, the first transfer electrode is set at an on-potential that allows charge transfer during a first period of time after the irradiation with light, and set to an off-potential that stops the charge transfer during a second period following the first period. The second transfer electrode is an electrode configured to control charge transfer from the photosensitive region to the second charge collection region, and disposed on a region between the photosensitive region and the second charge collection region. In addition, the second transfer electrode is set to the off-potential during the first period and to the on-potential during the second period. The voltage generating circuit has one end connected to a first constant potential line set at a predetermined potential and the other end connected to a second constant potential line set at a lower potential than the first constant potential line. The voltage generating circuit generates a control voltage corresponding to a larger one between an amount of charge stored in a storage node coupled to the first charge collection area and an amount of charge stored in a storage node coupled to the second charge collection area. Each first and second transistor has a control terminal to which the control voltage is applied, a first current terminal connected to the first constant potential line, and a second current terminal. The third transistor has a first current terminal connected to the second current terminal of the first transistor, a second current terminal connected to the storage node coupled to the first charge collection region, and a control terminal to which a constant voltage is applied , The fourth transistor has a first power terminal connected to the second power terminal of the second transistor, a second power terminal connected to the storage node coupled to the second charge collection area, and a control terminal to which a constant voltage is applied ,
    (2) The potentials of the storage nodes coupled to the different charge collection regions vary depending on the stored charge amounts. Thus, there is also a difference between the potentials of the respective storage nodes as a function of the difference between the stored charge quantities. Thus, when each first and second transistor is directly connected to the corresponding storage node, a difference arises between the voltages between the current terminals of the first and second transistors. Therefore, the charge amount injected into the first charge collection region and the charge amount injected into the second charge collection region are not equal due to channel length modulation effects of the first and second transistors, so that there is little difference between them. This creates a fault in the test section.
    (3) With respect to such a problem, the third transistor is connected between the first transistor and the storage node coupled to the first charge collection region, and the fourth transistor is connected between the second transistor and the storage node coupled to the second charge collection region in the distance sensor connected to the present embodiment. In such a configuration, a potential of a current output end of the first transistor and a potential of the corresponding memory node are disconnected. Also, a potential of the current output end of the second transistor and a potential of the corresponding storage node are disconnected. As a result, even with a potential difference between the storage nodes, the influence on the voltages between the current terminals of the first and second transistors can be suppressed. That is, it is possible to reduce a difference in the power supply from the first and second transistors to the respective storage nodes.
    (4) As an aspect of the present embodiment, the third and fourth transistors may be MOSFETs in the distance sensor having the above structure. Accordingly, the potential of the current output end of the first transistor and the potential of the corresponding storage node are respectively disconnected, and the potential of the current output end of the second transistor and the potential of the corresponding storage node are also disconnected.
    [Details of Embodiment of the Present Invention] Hereinafter, a specific structure of the distance sensor according to the present embodiments will be described in detail with reference to the accompanying drawings. Incidentally, the invention is not limited to these various examples, but is illustrated by the claims, and every change in an equivalent sense and the equivalent scope of the claims shall be included therein. In the description of the drawings, the same elements are identified with the same reference characters and redundant descriptions are omitted. In the following description, when a transistor is a FET, a control terminal means a gate and a power terminal means a source or sink. When the transistor is a bipolar transistor, a control terminal means a base and a current terminal means a collector or an emitter.
    Fig. 1 is a plan view illustrating a configuration of a distance sensor 1A according to an embodiment of the present invention. The distance sensor 1A in FIG. 1 is a device that measures a distance to an object by irradiating the object with light and detecting reflected light from the object. As shown in Fig. 1, the distance sensor 1A includes an imaging area 11 formed on a semiconductor substrate 10, a sensor driving circuit 12, and a processing circuit 13. The sensor driving circuit 12 controls the imaging area 11. The processing circuit 13 processes an output of the imaging area 11. The imaging area 11 faces a plurality of pixels P, which are arranged one or two-dimensionally on the semiconductor substrate 10. In Fig. 1, the pixels P (m, n) are represented in m rows and n columns (m and n are natural numbers). Each of the pixels P (m, n) includes a light receiving unit 9 and a current injection circuit 20. The imaging area 11 detects the reflected light from the object for each of the pixels P. Then, the distance for each of the pixels P of the image of the object is obtained by obtaining the time from the irradiation of the light to the arrival of the reflected light for each of the pixels P. The distance sensor 1A is a charge-distribution-type distance sensor and obtains the time from the irradiation of the light to the arrival of the reflected light according to a ratio of the amounts of charge distributed to two positions within each of the pixels P.
    Fig. 2 is a plan view of the light receiving unit 9 of each of the pixels P (m, n) of the distance sensor 1A shown in Fig. 1. FIGS. 3 and 4 are cross-sectional views along a line III-III and a line IV-IV of FIG. 2, respectively, and views illustrating cross-sectional configurations of the light receiving unit 9. In addition, FIG. 3 also illustrates a light source unit 30. The light source unit 30 is a component configured to irradiate an object with light L1, and includes a light source 31, a light source drive circuit 32, and a control circuit 33. The light source 31 includes light emitting semiconductor element, such as a laser element or a light emitting diode. The light source drive circuit 32 drives the light source 31 at a high frequency. The control circuit 33 outputs a drive clock of the light source drive circuit 32. In addition, pulsed light subjected to intensity modulation of a rectangular or sine wave is periodically emitted from the light source 31.
    The irradiation light L1 from the light source 31 is reflected by a surface of the object B and impinges on each of the pixels P (m, n) in the imaging region 11 of the distance sensor 1A from a back side 10b of the semiconductor substrate 10 as the reflected light L2. Incidentally, a plurality of imaging lenses corresponding to the pixels P (m, n) may be arranged so as to oppose the back surface 10b of the semiconductor substrate 10.
    As shown in Fig. 2, the light receiving unit 9 includes a transfer electrode 17 (first transfer electrode), a transfer electrode 18 (second transfer electrode), a transfer electrode 44, a photo gate electrode 19, signal extraction electrodes 42 and 43, and a charge discharge electrode 45. In Figs. 2, the number of the transfer electrodes 17 and 18 and the signal extraction electrodes 42 and 43 is two, but may be one. In Fig. 2, the number of individual elements of the transfer electrode 44 and the charge discharge electrode 45 is two, but may be one.
    As shown in Fig. 3, the light receiving unit 9 further comprises a photosensitive region 14, a charge collecting region 15 (first charge collecting region) and a charge collecting region 16 (second charge collecting region). The photosensitive area 14 receives the reflected light L2 and generates charges corresponding to the amount of light. The charge collecting regions 15 and 16 are disposed adjacent to the photosensitive region 14 in a state of pinching the photosensitive region 14. Each of the charge collection regions 15 and 16 collects charges from the photosensitive region 14 so that the charges are stored in each storage node coupled thereto. Incidentally, the photosensitive region 14 is disposed between the charge collection regions 15 and 16 in Fig. 3, but the charge collection regions 15 and 16 may be adjacent to one side of the photosensitive region 14, and there is no restriction on a positional relationship therebetween.
    Concretely, the semiconductor substrate 10 is made of a high concentration P-type (second conductivity type) semiconductor, and the light receiving unit 9 of each of the pixels P (m, n) has a low-concentration P-type (second conductivity type) surface area 10c on one side of a surface 10 a of the semiconductor substrate 10. In addition, on the surface 10a of the semiconductor substrate 10, an insulating layer 41 and on the surface portion 10c between the charge collecting regions 15 and 16, the photo-gate electrode 19 with the insulating layer 41 therebetween is formed. A region within the surface region 10c positioned immediately below the photo-gate electrode 19 is the photosensitive region 14. A potential of the photosensitive region 14 is controlled by a voltage applied to the photo-gate electrode 19. If necessary, a slightly positive DC voltage is applied to the photo-gate electrode 19. As a result, hole-electron pairs are generated in the light-sensitive region 14 in response to the reflection of the reflected light L2.
    The charge collection regions 15 and 16 are high-concentration n-type (first conductivity-type) regions formed on the side of the surface portion 10 c of the semiconductor substrate 10. The charge collection regions 15 and 16 are also referred to as sliding diffusion regions or charge storage regions. An n-type semiconductor has electrons as the carrier in the electrically neutral state and is positively ionized in the absence of the carrier. This means that each band structure of the highly concentrated n-charge collecting regions 15 and 16 has a strongly recessed shape and forms a potential well. The signal extraction electrode 42 is formed on the charge collection region 15 and the signal extraction electrode 43 is formed on the charge collection region 16. The signal extraction electrodes 42 and 43 are in contact with the charge collecting regions 15 and 16 through openings formed in the insulating layer 41.
    The transfer electrode 17 is disposed on a region between the photosensitive region 14 and the charge collecting region 15. The transfer electrode 18 is disposed on a region between the photosensitive region 14 and the charge collection region 16. When a positive potential (on-potential) is applied to the transfer electrode 17, a potential of the region immediately below the transfer electrode 17 has an average size between a potential of the photosensitive region 14 and a potential of the charge collecting region 15. In this way, potential steps are formed from the photosensitive region 14 to the charge collecting region 15, and electrons fall into the potential well of the charge collecting region 15 (the charges are stored in the well). Also, when a positive potential (on-potential) is applied to the transfer electrode 18, a potential of the region immediately below the transfer electrode 18 has an average size between the potential of the photosensitive region 14 and a potential of the charge-collecting region 16. Thus, potential steps of the photosensitive Area 14 is formed to the charge collecting region 16, and electrons fall into the potential well of the charge collecting region 16.
    Incidentally, the structure of providing the signal extraction electrodes 42 and 43 on the charge collection regions 15 and 16 for extracting signals is adopted in the present embodiment, but it is also possible to separately provide a highly concentrated region for the signal extraction applied to the charge collection regions 15 and 16, and to arrange other transfer electrodes on areas between the high-concentration area and each of the charge-collecting areas 15 and 16, and to provide a signal extraction electrode in the high-concentration area to extract a signal.
    As shown in Fig. 4, the light receiving unit 9 further comprises two charge collecting regions 46. The charge collecting regions 46 are formed in the surface region 10 c of the semiconductor substrate 10 and disposed adjacent to the photosensitive region 14 in the state of insertion of the photosensitive region 14. Subsequently, the charge discharge electrode 45 is formed on the charge collecting region 46. The charge discharge electrode 45 is in contact with the charge collecting region 46 through the opening formed in the insulating layer 41. The transfer electrode 44 is disposed on a region between the photosensitive region 14 and the charge collection region 46. When a positive potential (on-potential) is applied to the transfer electrode 44, the charge moves from the photosensitive region 14 to the charge-collecting region 46, and the charges are stored in a potential well of the charge-collecting region 46. Incidentally, a specific configuration of the charge collecting region 46 is the same as that of the charge collecting regions 15 and 16.
    Fig. 5A is a diagram illustrating an example of a temporal change of the intensity of the reflected light on a certain pixel P (m, n). FIG. 5B is a graph illustrating a time change of the voltage applied to the transfer electrode 17. FIG. FIG. 5C is a graph illustrating a time change of the voltage applied to the transfer electrode 18. FIG. As shown in FIG. 5A, the reflected light L2 is incident on the pixel P (m, n) delayed by a light illumination timing T1 by a time T2 corresponding to a distance to the object B. FIG.
    As shown in Fig. 5B, the transfer electrode 17 is set to the on-potential in a first period H1 after the light irradiation and to the off-potential in a second period H2 after the first period. In addition, the transfer electrode 18 is set to the off-potential in the first period H1 and to the on-potential in the second period H2, as shown in Fig. 5C. Then, it is assumed that a part of the reflected light L2 (a region A1 of the graph in the drawing) hits the pixel P (m, n) within the first period H1. At this time, since the transfer electrode 18 is set at the off-potential and the transfer electrode 17 at the on-potential, the charges generated in the photosensitive region 14 move to the charge-collecting region 15 and are stored therein. The remaining part of the reflected light L2 (a region A2 of the graph in the drawing) strikes the pixel P (m, n) within the second period H2. At this time, since the transfer electrode 17 is set at the off-potential and the transfer electrode 18 at the on-potential, the charges generated in the photosensitive region 14 move to the charge-collecting region 16 and are stored therein. Therefore, it is possible to know the delay time T2, that is, the distance to the object B, by taking a relationship between a charge amount stored in the charge collecting region 15 (a charge amount stored in the storage node coupled to the charge collecting region 15) and an im Charge accumulation area 16 stored charge amount (a stored in the storage node charge amount, which is coupled to the charge collection area 16) receives.
    Here, the processing circuit 13 of the present embodiment may be a circuit that outputs a difference between these charge amounts by causing the charges stored in the charge collection region 15 and the charges stored in the charge collection region 16 to equalize each other. Also in this case, it is possible to know the relationship between the charge amount stored in the charge collection region 15 and the charge amount stored in the charge collection region 16 as long as the sum of the charge amounts stored in the charge collection regions 15 and 16 (the sum of the charge amounts stored in the storage nodes each coupled to the charge collection regions 15 and 16) is known. Hereinafter, a drive system of the imaging area 11 will be described to know the sum of the charge amounts stored in the charge collection areas 15 and 16.
    The sensor drive circuit 12 drives the transfer electrodes 17 and 18 according to the present embodiment by successively executing a plurality of time-divided frames (each of which represents a drive pattern of a transfer electrode). FIG. 6 is a view illustrating the drive system of the imaging area 11 using the sensor drive circuit 12. As shown in FIG. 6, in the drive system of the present embodiment, the processing in each of the first and second frames F1 and F2 is performed while the frames F1 and F2 are alternately repeated. Fig. 6 also illustrates the processing contents within the respective frames F1 and F2. Within the frames F1 and F2, a storage frame F3 for storing charges in the charge collecting regions 15 and 16 and a reading frame F4 for reading charges from the charge collecting regions 15 and 16 are alternately repeated.
    Figs. 7A and 7B are timing charts illustrating the operation of the transfer electrodes 17, 18 and 44 in the memory frame F3. Fig. 7A illustrates the timing chart in the first frame F1, and Fig. 7B illustrates the timing chart in the second frame F2. 7A and 7B illustrate a drive clock CL of the light source driver 32 outputted from the control circuit 33 (that is, a temporal change of an intensity of the pulsed light output of the light source 31), a drive voltage Vtx-i applied to the transfer electrode 17, a drive voltage Vtx2 applied to the transfer electrode 18 and a drive voltage Vtxr applied to the transfer electrode 44.
    In the memory frame F3, the drive voltages Vtx-i and Vtx2 are repeatedly switched between the on-potential and the off-potential twice at a certain cycle T in each one-time boost of the drive clock CL. The cycle T is set to twice the turn-on time tL of the drive clock CL (for example, T = 2tL). In addition, a turn-on time (a period in which a drive voltage is set to the turn-on potential) of the drive voltages Vtx-i and Vtx2 in each cycle is equal to the turn-on time tL of the drive clock CL.
    Specifically, the equidistant times t0, t-i, ... and t9 are defined in the memory frame F3 of the first frame F1 and the second frame F2, respectively, as shown in Figs. 7A and 7B. An interval between these times is one half of the one-time irradiation time tL of the irradiation light L1. At this time, the light source unit 30 transmits the irradiation light L1 for the times t-1 to t3. Subsequently, the sensor drive circuit 12 sets the drive voltage Vtx-i to the on-potential between times t0 and t2 and between times t4 and t6 and the drive voltage Vtx2 to the on-potential between times t2 and t4 and between times t6 and t8 in the first frame F1, as shown in Fig. 7A. In addition, the sensor drive circuit 12 sets the drive voltage Vtx-i to the on-potential between times t-1 and t3 and between times t5 and t7 and the drive voltage Vtx2 to the on-potential between times t3 and t5 and between times t7 and t9 in the second frame F2 as shown in Fig. 7B.
    Incidentally, the drive voltage Vtxr applied to the transfer electrode 44 is set to the on-potential except for a period in which the other drive voltages Vtx-i and Vtx2 are first set to the on-potential and then finally to the off-potential be set. That is, the drive voltage Vtxr is set to the off-potential between the times t0 and t8 in the first frame F1, to the off-potential between the times L and t9 in the second frame F2, and to the on-potential in the other frame.
    In other words, the above process is performed as follows. In the first frame F1, the drive voltage Vtx-i rises at a timing earlier than (tL / 2) than the rise timing of the drive clock CL. Hereinafter, a phase of the drive voltage Vtx-i in the first frame F1 is set to 0 °. In the same first frame F1, the drive voltage Vtx2 rises at a later time by tL as the rising timing of the drive voltage Vtx-i. In other words, a phase of the drive voltage Vtx2 in the first frame F1 is 180 °. In the second frame F2, the drive voltage Vtx-i rises at the same time as the rise timing of the drive clock CL. In other words, one phase of the drive voltage Vtx-i in the second frame F2 is 90 °. Moreover, in the same second frame F2, the drive voltage Vtx2 increases by tL at a later time as the rising timing of the drive voltage Vtx-i. In other words, one phase of the drive voltage Vtx2 in the second frame F2 is 270 °. Incidentally, Fig. 8 is a view overlapping the time charts of the first frame F1 and the second frame F2 in Figs. 7A and 7B for the one-time driving clock CL to facilitate the understanding. A drive voltage Vtx-i (1) and a drive voltage Vtx2 (1) respectively represent the drive voltages Vtx-i and Vtx2 in the first frame F1, and a drive voltage Vtx-i (2) and a drive voltage Vtx2 (2) respectively set the drive voltages Vtx-i and Vtx2 in the second frame F2.
    Figs. 9 and 10 further illustrate a diagram of a light-receiving pulse waveform of the reflected light L2 in the timing chart shown in Fig. 8. As shown in FIG. 9, it is assumed that the reflected light L2 strikes the pixel P (m, n) after a time (tL / 3) elapsed since the object has been irradiated with light L1. At this time, in the first frame F1, charges corresponding to the area of an area A3 in Fig. 9 in the charge accumulation area 15 and charges corresponding to the area of an area A4 are stored in the charge accumulation area 16. Assuming that the total charge amount generated by the reflected light L2 is Q, a charge amount stored in the charge collection region 15 is Q / 6 and a charge amount stored in the charge collection region 16 is (5 × Q / 6). Moreover, in the second frame F2, in the charge collecting region 15 charges corresponding to the area of a region A5 in the drawing and in the charge collecting region 16 charges corresponding to the area of a region A6 are stored. At this time, a charge amount stored in the charge accumulation region 15 is (2 × Q / 3), and a charge amount stored in the charge accumulation region 16 is Q / 3. Subsequently, the charge amount Q / 6 of the charge accumulation region 15 in the first frame F1 is subtracted from the charge amount (5 × Q / 6) of the charge accumulation region 16 in the first frame F1, whereby a value of (2 × Q / 3) is obtained. Also, the charge amount (2 × Q / 3) of the charge collecting region 15 in the second frame F2 is subtracted from the charge amount Q / 3 of the charge collecting region 16 in the second frame F2, thereby obtaining a value of -Q / 3. Then, when absolute values of these values are added, the total charge amount Q generated by the reflected light L2 is obtained.
    Next, it is assumed that the reflected light L2 strikes the pixel P (m, n) after a time (3 xtL / 4) elapsed from the irradiation of the object with the light L1, as in FIG Fig. 10 shown. At this time, in the first frame F1, charges corresponding to the area of a region A7 in FIG. 10 are stored in the charge collecting region 15 and a charge corresponding to the area of a region A8 in the charge collecting region 16. At this time, a charge amount stored in the charge accumulation region 15 is Q / 4 and a charge amount stored in the charge accumulation region 16 is (3 × Q / 4). Moreover, in the second frame F2, charges corresponding to the area of a region A9 in FIG. 10 in the charge collection region 15 and charges corresponding to the area of a region A10 are stored in the charge collection region 16. At this time, a charge amount stored in the charge accumulation region 15 is Q / 4 and a charge amount stored in the charge accumulation region 16 is (3 × Q / 4). Subsequently, the charge amount Q / 4 of the charge accumulation region 15 in the first frame F1 is subtracted from the charge amount (3 × Q / 4) of the charge accumulation region 16 in the first frame F1, whereby a value of (Q / 2) is obtained. Also, the charge amount Q / 4 of the charge accumulation region 15 in the second frame F2 is subtracted from the charge amount (3 × Q / 4) of the charge accumulation region 16 in the second frame F2, whereby a value of (Q / 2) is obtained. Then, when absolute values of these values are added, the total charge amount Q generated by the reflected light L2 is obtained.
    As is apparent from the above example, it is possible to obtain the total charge amount Q generated by the reflected light L2 by adding the absolute value of the value obtained by subtracting the amount of charge stored in the Phase 0 ° is collected, that is, the times t0 to t2 and t4 to t6, of the charge amount collected in phase 180 °, that is, in times t2 and t4 and t6 and t8, and the absolute value of the value obtained by subtracting the amount of charge collected in the phase 90 °, ie the times t-1 and t3 and t3 and t5 and t7 and t9, from the charge amount collected in the phase 270 °, ie the times t3 and t5 and t5 and t7 and t9. Therefore, it is possible to know the delay time T2, that is, the distance to the object B, by dividing the ratio of the charge amounts stored in the charge collecting regions 15 and 16 (the ratio of those in the storage nodes respectively coupled to the charge collecting regions 15 and 16) are stored charge amounts) based on the thus obtained total charge amount Q and the difference between the charge amounts stored in the charge collection areas 15 and 16, which have been taken out of the processing circuit 13.
    According to the distance sensor 1A according to the present embodiment, it is possible to obtain the time T2, that is, the distance to the object B, based on the difference between the amounts of charge stored in the storage nodes, each with the charge accumulation regions 15 and 15 described above 16 are coupled. Therefore, it is possible to adopt the application method of injecting the same amount of electricity into each storage node, and as a result, it is possible to avoid the saturation of each storage node. In the following, an example of a circuit configuration for feeding the same amount of electricity into each storage node will be described in detail. Fig. 11 is a circuit diagram illustrating a configuration of the current injection circuit 20 shown in Fig. 1. As shown in FIG. 11, the current injection circuit 20 of the present embodiment includes a voltage generating circuit 21, a transistor 22a (first transistor), a transistor 22b (second transistor), a transistor 23a (third transistor), and a transistor 23b (fourth transistor). The transistors 22a, 22b, 23a and 23b are field effect transistors, for example p-channel MOSFETs.
    The voltage generating circuit 21 is disposed between a supply potential line 34 (first constant potential line) and a reference potential line GND (second constant potential line) having a lower potential than the supply potential line 34. The voltage generating circuit 21 generates control voltages / Ci and VC2 which correspond to a larger one of the charge amounts stored in the charge collecting regions 15 and 16. In particular, the voltage generating circuit 21 includes a transistor pair 24 and a current source 25 connected in series between the supply potential line 34 and the reference potential line GND. In addition, the voltage generating circuit 21 has the buffer circuits 27 and 28.
    The transistor pair 24 includes a transistor 24a (fifth transistor) and a transistor 24b (sixth transistor). The transistors 24a and 24b are field effect transistors, for example p-channel MOSFETs. A current terminal (first current terminal) of the transistors 24a and 24b is electrically connected to the supply potential line 34 via the current source 25 in the state of mutual short-circuiting. The other power terminals (second power terminals) of the transistors 24a and 24b are electrically connected to the reference potential line GND in the state of mutual short-circuiting. A control terminal of the transistor 24a is electrically connected to the signal extraction electrode 42 in the charge collection region 15 via a storage node 26a. A control terminal of the transistor 24b is electrically connected to the signal extraction electrode 43 on the charge collection region 16 via a storage node 26b. The storage node 26a stores the charge accumulated in the charge collection region 15, and the storage node 26b stores the charge accumulated in the charge collection region 16.
    The current source 25 includes a transistor 25a. The transistor 25a is a field effect transistor, for example a p-channel MOSFET. A power terminal (first power terminal) of the transistor 25 a is electrically connected to the power supply line 34. The other current terminal (second current terminal) of the transistor 25a is electrically connected to the first current terminal of each of the transistors 24a and 24b. A predetermined bias voltage (constant voltage) V-1 is applied to a control terminal of the transistor 25a. Incidentally, the power source may also include another transistor connected in parallel with the transistor 25a.
    The transistor 22a supplies a current for eliminating an interfering light component to avoid saturating the storage node 26a on the storage node 26a. A current terminal (first current terminal) of the transistor 22a is connected to the power supply potential line 34, and the other power terminal (second power terminal) is connected to the storage node 26a via the transistor 23a. A control terminal of the transistor 22a is electrically connected through the buffer circuit 27 to a node N1 between the pair of transistors 24 and the power source 25.
    The transistor 22b supplies the current for eliminating the disturbance light component to the storage node 26b. One power terminal (first power terminal) of the transistor 22b is connected to the power supply potential line 34, and the other power terminal (second power terminal) is connected to the storage node 26b via the transistor 23b. A control terminal of the transistor 22b is connected through the buffer circuit 28 to the node N1.
    The transistor 23a is cascade-connected to the transistor 22a and prevents an operation of the transistor 22a from being affected by a potential fluctuation of the storage node 26a. Specifically, one power terminal (first power terminal) of the transistor 23a is connected to the second power terminal of the transistor 22a, and the other power terminal (second power terminal) of the transistor 23a is connected to the storage node 26a. A predetermined bias voltage (constant voltage) V3 is applied to a control terminal of the transistor 23a.
    The transistor 23b is connected in cascade with the transistor 22b and prevents an operation of the transistor 22b from being affected by a potential fluctuation of the storage node 26b. Specifically, a current terminal (first current terminal) of the transistor 23b is connected to the second current terminal of the transistor 22b, and the other current terminal (second current terminal) of the transistor 23b is connected to the storage node 26b. A given bias voltage (constant voltage) V4 is applied to a control terminal of the transistor 23b. As an example, the bias voltage V3 and the bias voltage V4 can be set equal.
    The buffer circuit 27 shifts a potential of the node N1 to generate a control voltage VC-ι and provides the generated control voltage to the control terminal of the transistor 22a. The buffer circuit 27 is configured to integrate, for example, a source sequencing circuit. In particular, the buffer circuit 27 has the transistors 27a and 27b connected in series. One power terminal (first power terminal) of the transistor 27a is connected to the power supply potential line 34, and the other power terminal (second power terminal) is connected to a power terminal (first power terminal) of the transistor 27b. The other current terminal (second current terminal) of the transistor 27b is connected to the reference potential line GND. A predetermined bias voltage (constant voltage) V5 is applied to a control terminal of the transistor 27a. The potential of the node N1 is applied to a control terminal of the transistor 27b. The buffer circuit 27 outputs the control voltage VCi of a magnitude corresponding to the potential of the node N1 from the node between the transistors 27a and 27b.
    The buffer circuit 28 shifts the potential of the node N1 to generate a control voltage VC2 and provides the generated control voltage to the control terminal of the transistor 22b. The buffer circuit 28 is configured to integrate, for example, a source sequencing circuit. In particular, the buffer circuit 28 has the transistors 28a and 28b connected in series. One power terminal (first power terminal) of the transistor 28a is connected to the power supply potential line 34, and the other power terminal (second power terminal) is connected to a power terminal (first power terminal) of the transistor 28b. The other current terminal (second current terminal) of the transistor 28b is connected to the reference potential line GND. A predetermined bias voltage (constant voltage) V6 is applied to a control terminal of the transistor 28a. The potential of the node N1 is applied to a control terminal of the transistor 28b. The buffer circuit 28 outputs the control voltage VC2 having a magnitude corresponding to the potential of the node N1 from the node between the transistors 28a and 28b. The magnitudes of the bias voltages V5 and V6 are set so that the amount of current supplied from the transistor 22a to the storage node 26a and the amount of current supplied from the transistor 22b to the storage node 26b are equal. As an example, V5 = V6 can be set.
    Incidentally, the buffer circuits 27 and 28 may be omitted. In this case, the control terminals of the transistors 22a and 22b are directly connected to the node N1, and the potential of the node N1 is provided to these control terminals as the control voltage / Ci and VC2.
    The current injection circuit 20 further includes the reset circuits 35 and 36. The reset circuit 35 has a transistor 35a, and the reset circuit 36 has a transistor 36a. A reset potential Vr is applied to a current terminal (first power terminals) of each of the transistors 35a and 36a. The other current terminal (second current terminal) of the transistor 35a is connected to the storage node 26a and the other current terminal (second current terminal) of the transistor 36a is connected to the storage node 26b. A reset signal Sr is applied to a control terminal of each of the transistors 35a and 36a, and the charges of the storage nodes 26a and 26b are discharged when the transistors 35a and 36a are set in the on state.
    An operation of the current injection circuit 20 having the above configuration will now be described. When the reflected light L2 hits the pixel P (m, n), the charges flow into the charge collecting regions 15 and 16 in the ratio corresponding to the distance to the object B (see Figs. 5A to 5C). In addition, the charges corresponding to the magnitude of the stray light incident on the pixel P (m, n) also flow into the charge collecting regions 15 and 16. However, when the turn-on time of the drive voltage applied to the transfer electrode 17 and the turn-on time of the transfer electrode 18 to the transfer electrode 18 applied driving voltage are the same, the amounts of charge that flow due to the stray light in the charge collecting regions 15 and 16, the same.
    As a result, the potentials of the storage nodes 26a and 26b have sizes corresponding to the amounts of charge flowing into the charge collecting regions 15 and 16, respectively. Then, when the charges continue to flow into the charge collecting regions 15 and 16 and one of the potentials of the storage nodes 26a and 26b exceeds a turn-on voltage, one of the transistors 24a and 24b starts to flow a current corresponding to the potential of the one storage node. Therefore, the potential of the node N1 has a size corresponding to a larger amount of charges stored in the charge collecting regions 15 and 16 (storage nodes 26a and 26b). The control voltages VC-1 and VC2 having magnitudes corresponding to the potential of the node N1 are respectively output to the control terminals of the transistors 22a and 22b.
    The transistors 22a and 22b receive at their control terminals the above control voltages VCi and VC2 and cause current to flow according to each magnitude of the control voltages VC-ι and VC2. Since the predetermined bias voltages V3 and V4 are constantly applied to the control terminals of the transistors 23a and 23b, the current from each of the transistors 23a and 23b is supplied to each of the storage nodes 26a and 26b. This compensates for the same amount of charge on the storage nodes 26a and 26b and prevents saturation of the storage nodes 26a and 26b (charge collection areas 15 and 16) caused by the disturbance light.
    Effects which can be achieved by the distance sensor 1A according to the present embodiment as described above will be described. FIG. 12 is a circuit diagram illustrating a configuration of a current injection circuit 100 according to a comparative example. The current injection circuit 100 has the same configuration as the current injection circuit 20 of the present embodiment, except that the transistors 23a and 23b and the buffer circuits 27 and 28 are not provided. Incidentally, the reset circuits 35 and 36 are not shown.
    In the current injection circuit 100 shown in Fig. 12, the transistors 22a and 22b are directly connected to the storage nodes 26a and 26b, and the potentials of the storage nodes 26a and 26b vary depending on the charge amounts stored in the charge collection regions 15 and 16. Therefore, there is also a difference between the potentials of the storage nodes 26a and 26b depending on the difference between the amounts of charge stored in the charge collecting regions 15 and 16. That is, a difference arises between the source-drain voltages of the transistors 22a and 22b. Thus, the amount of charge injected into the storage node 26a and the amount of charge injected into the storage node 26b are unequal, so that there is little difference between them due to the characteristics (channel length modulation effects) of the transistors 22a and 22b. Thereby, an error occurs when the processing circuit 13 outputs the difference between the amounts of charges stored in the charge accumulation areas 15 and 16, thereby causing an error in the measurement path.
    Concerning such a problem, cascode devices such as the transistors 23a and 23b according to the present embodiment are disposed between each of the transistors 22a and 22b and each of the storage nodes 26a and 26b in the distance sensor 1A. Thereby, the potential of each of the transistors 22a and 22b and the potential of each of the storage nodes 26a and 26b are disconnected so that even with a potential difference between the storage node 26a and the storage node 26b, the influence on the source-drain voltage of each of the transistors 22a and 22b is suppressed can be (the source-drain voltages of the transistors 22a and 22b can be equated). Therefore, it is possible to reduce the difference in the amounts of current input from the transistors 22a and 22b into the respective storage nodes 26a and 26b (charge accumulation areas 15 and 16) and to accurately control these injected amounts of current to a substantially uniform size.
    Here, FIG. 13A is a diagram illustrating an example of a time change of a voltage value (potential) of each of the storage nodes 26a and 26b in the current injection circuit 100 according to the comparative example. In Fig. 13A, a graph G11 indicates the voltage value of a storage node and a graph G12 indicates the voltage value of the other storage node. Moreover, Fig. 13B is a diagram illustrating an example of a time change of the amount of current supplied to each of the storage nodes 26a and 26b in the current injection circuit 100 according to the comparative example. In Fig. 13B, a graph G21 indicates the amount of current supplied to a storage node and a graph G22 indicates the amount of current supplied to the other storage node.
    As shown in Fig. 13A, the potentials of the storage nodes 26a and 26b are gradually reduced by the storage of charges in the storage nodes 26a and 26b. Further, when the potential of a storage node exceeds a turn-on voltage of the transistor 24a (or 24b), the current injection is started to each of the storage nodes 26a and 26b (1.5 to 1.6 milliseconds) as shown in Fig. 13B. As a result, the potential of one storage node no longer decreases and becomes constant, and the potential of the other storage node begins to increase.
    However, the amounts of current supplied to the respective storage nodes are slightly different from each other due to the above-described potential difference between the storage node 26a and the storage node 26b. As a result, the graph G21 and the graph G22 gradually deviate from each other. Such a difference in the amount of injected current appears as a measurement error.
    On the other hand, Fig. 14A is a diagram illustrating an example of a time change of a voltage value (potential) of each of the storage nodes 26a and 26b in the current injection circuit 20 according to the present embodiment. In Fig. 14A, a graph G31 indicates the voltage value of a storage node and a graph G32 indicates the voltage value of the other storage node. In addition, the graphs G41 and G42 in FIG. 14B illustrate examples of changes with time of the injected current amounts at the storage nodes 26a and 26b in the current injection circuit 20 of the present embodiment, respectively. Since the injected amounts of current of the storage nodes 26a and 26b are equal, the graphs G41 and G42 are completely superimposed.
    As described above, the potential difference between the storage node 26a and the storage node 26b is reduced, and it is possible to approximate the supplied amounts of current to the storage nodes according to the present embodiment. Therefore, it is possible to reduce the measurement error according to the present embodiment.
    Moreover, each of the transistors 23a and 23b is preferably the MOSFET as in the present embodiment. Thereby, it is possible to correspondingly separate the potential of each of the transistors 22a and 22b from the potential of each of the storage nodes 26a and 26b. This is particularly effective when each of the transistors 22a and 22b is the MOSFET as in the present embodiment.
    (First modification)
    FIGS. 15A and 15B are views illustrating time charts of a driving method according to a first modification of the above embodiment. The sensor drive circuit 12 of the above embodiment may drive the transfer electrodes 17 and 18 based on the timing charts shown in FIGS. 15A and 15B instead of the timing charts shown in FIGS. 7A and 7B.
    A difference between the timing chart of the first modification and the timing chart of the above embodiment is the length of a turn-on time of the drive voltages Vtx-i and Vtx2. In the above embodiment, the turn-on time (time period in which a transfer electrode is set to a turn-on voltage) of the drive voltages Vtx-i and Vtx2 is equal to the turn-on time of the drive clock CL (that is, the irradiation time of the irradiation light L1) tL; however, the turn-on time of the drive voltages Vtx-i and Vtx2 is half the time tL (tL / 2) in the present modification. In particular, the uniform times t0, t-1, ..., and t8 are defined in the memory frame F3 of the first frame F1 and the second frame F2, respectively, as shown in Figs. 15A and 15B. An interval between these times is one half of the one-time irradiation time tL of the irradiation light L1. At this time, the light source unit 30 irradiates the irradiation light L1 for the times t-1 to t3. Subsequently, the sensor drive circuit 12 sets the drive voltage Vtx-i to the turn-on potential between times t0 and t-1 and between times t4 and t5 and the drive voltage Vtx2 to the turn-on potential between times t2 and t3 and between times t6 and t7 in the first Frame F1, as shown in Fig. 15A. In addition, the sensor drive circuit 12 sets the drive voltage Vtx-i at the turn-on potential between the times L and t2 and between the times t5 and t6 and the drive voltage Vtx2 at the turn-on potential between the times t3 and t4 and between the times t7 and t8 in the second frame F2 as shown in Fig. 15B.
    Incidentally, the drive voltage Vtxr applied to the transfer electrode 44 is set to the on-potential, but for a period of time in which the other drive voltages Vtx-i and Vtx2 are first set to the on-potential and finally to the off-potential , That is, the drive voltage Vtxr is set in the first frame F1 to the off potential between the times t0 and t7, set in the second frame F2 to the off potential between the times t-ι and t8 and in the other periods to the on -Potential.
    A drive system of the first modification can obtain a value of 1/2 the total charge amount generated by the reflected light L2 by taking absolute values of a difference between the output values of the first frame F1 and a difference between the output values of the second frame F2 and the absolute value of the larger is selected. In addition, a sign of the output value of the first frame F1 and a sign of the output value of the second frame F2 are correspondingly inverted and a corresponding offset is added, whereby a linearly increasing value corresponding to the time T2 is obtained.
    Figs. 16A to 16C are views for describing a distance calculating method with the first modification. 16A is a graph illustrating a relation between a value obtained by subtracting an amount of charge of a storage node coupled to the charge collection region 15 from a charge amount of a storage node coupled to the charge collection region 16 (ie, an output value of each of the pixels P (m, n )) and the time t from the irradiation of the light L1 to the incidence of the reflected light L2 (that is, a distance to the object B). In Fig. 16A, a graph G41 indicates the output value in the first frame F1 and a graph G42 indicates the output value in the second frame F2. Incidentally, the output value is normalized to reach a maximum value of 1 and a minimum value of -1.
    As the graph G41 of Fig. 16A shows, in the first frame F1, the output value is constant as 1 in a portion D1 of 0 <t <t <tL / 2, the output value decreases from 1 to -1 in a portion D2 of tL / 2 <t <t <tL, the output value is constant as -1 in a section D3 of tL <t <t <(3 x tL / 2), and the output value increases from -1 to 1 in a section D4 of (3 x tL / 2) <t <2tL. Moreover, as shown in the graph G42, in the second frame F2, the output value increases from -1 to 1 in the section D1, the output value is constant as 1 in the section D2, the output value decreases from 1 to -1 in the section D3, and Output value is constant as -1 in section D4.
    Here, absolute values of the respective output values of the first frame F1 and the second frame F2 are obtained, and the absolute value of the larger one is selected between the output values of the first frame F1 and the second frame F2. Subsequently, a graph G51 having a constant value is obtained irrespective of the time t, as shown in Fig. 16B. This graph G51 represents half the total amount of charge generated by the reflected light L2.
    Meanwhile, in a portion where the output value (graph G41) of the first frame F1 is smaller than the output value (graph G42) of the second frame F2 among the respective portions DI to D4, a sign of a smaller absolute value between the Output values of the first frame F1 and the second frame F2 inverted. In the example of Fig. 16A, the signs of the output value of the first frame F1 in the section D2 and the output value of the second frame F2 in the section D3 are inverted. As a result, both the output value of the second frame F2 in the sections D1 and D3 and the output value of the first frame F1 in the sections D2 and D4 have a positive slope with respect to the time t. Then, both the output value of the second frame F2 in the sections D1 and D3 and the output value of the first frame F1 in the sections D2 and D4 are multiplied by 1/4, as shown in Fig. 16B. Finally, a corresponding offset value is added to each of the output values of the second frame F2 in the sections D1 and D3 and the output value of the first frame F1 in the sections D2 and D4, whereby a linear map G52 is obtained in which the output value is from 0 to 1 in a range of 0 <t <2tL, as shown in Fig. 16C. This makes it possible to determine the time t, ie the distance to the object B, based on the diagram G51 and the diagram G52. Incidentally, the order of operations shown in Figs. 16A to 16C is not limited to those described above and may be performed in a different order. Alternatively, the operations shown in Figs. 16A to 16C may be performed simultaneously.
    According to this first modification, the distance to the object B can be obtained based on the difference between the amounts of charge stored in the storage nodes, which are respectively coupled to the charge collecting regions 15 and 16, similar to the above embodiment. Therefore, it is possible to apply the current injection circuit 20 of the above embodiment, and thereby it is possible to avoid the saturation of each storage node.
    (Second modification)
    Fig. 17 is a plan view illustrating a light receiving unit 9A according to a second modification of the above embodiment. As shown in Fig. 17, the light receiving unit 9A of the present modification includes each of the transfer electrode 17 (first transfer electrode), the transfer electrode 18 (second transfer electrode), a transfer electrode 51 (first transfer electrode), and a transfer electrode 52 (second transfer electrode). These transfer electrodes 17, 18, 51 and 52 are arranged around the photo-gate electrode 19 so as to be adjacent to the photo-gate electrode 19. Incidentally, in the second modification, the photo-gate electrode 19 is disposed between the transfer electrode 17 and the transfer electrode 18 and the photo-gate electrode 19 between the transfer electrode 51 and the transfer electrode 52, and a positional relationship between the transfer electrodes 17, 18, 51 and 52 is not limited the transfer electrodes are adjacent to the photo-gate electrode 19.
    In addition, the light receiving unit 9A has one of the signal extraction electrodes 42, 43, 55 and 56, respectively. The transfer electrode 17 is disposed between the signal extraction electrode 42 and the photo gate electrode 19, the transfer electrode 18 is interposed between the signal extraction electrode 43 and the photo gate electrode 19, the transfer electrode 51 is disposed between the signal extraction electrode 55 and the photo gate electrode 19, and the transfer electrode 52 is interposed between the signal extraction electrode 56 and the photo-gate electrode 19. In addition, the light receiving unit 9A has the transfer electrode 44 and the charge discharge electrode 45. In the light receiving unit 9A, a configuration immediately below the transfer electrodes 17 and 18 and the signal extraction electrodes 42 and 43 is the same as in Fig. 3, and a configuration immediately below Fig. 18 is a cross-sectional view taken along a line XVIII-XVIII of Fig. 17 including a configuration immediately below the transfer electrodes 51 and 52 and the signal extraction electrodes 55 and 56. As shown in Fig. 18, the light receiving unit 9A further has a charge collecting region 57 (first charge collecting region) and a charge collecting region 58 (second charge collecting region). In the example of FIG. 18, the charge collecting regions 57 and 58 are arranged to be adjacent to the photosensitive region 14 in the state of insertion of the photosensitive region 14. The charge collection regions 57 and 58 collect charges from the photosensitive region 14 so that the charges are stored in storage nodes coupled to the charge collection regions 57 and 58, respectively. Incidentally, the configurations of the charge collection regions 57 and 58 are identical to those of the charge collection regions 15 and 16 shown in FIG. 3.
    The signal extraction electrode 55 is formed on the charge collection region 57 and the signal extraction electrode 56 is formed on the charge collection region 58. The signal extraction electrodes 55 and 56 are in contact with the respective charge collecting regions 57 and 58 through openings formed in the insulating layer 41.
    The transfer electrode 51 is disposed on a region between the photosensitive region 14 and the charge collection region 57. The transfer electrode 52 is disposed on a region between the photosensitive region 14 and the charge collection region 58. When a positive potential (on-potential) is applied to the transfer electrode 51, electrons from the photosensitive region 14 fall into a potential well of the charge collecting region 57 (charges are stored in the pot). Also, electrons from the photosensitive region 14 fall into a potential well of the charge collecting region 58 when a positive potential (on-potential) is applied to the transfer electrode 52.
    The sensor drive circuit according to the second modification drives the transfer electrodes 17, 18, 51 and 52 by sequentially executing a plurality of time-divided frames (each of which represents a drive pattern of a transfer electrode). FIG. 19 is a view illustrating a drive system of the sensor drive circuit according to the second modification. FIG. As shown in Fig. 19, an identical frame F5 is repeated and the processing in frame F5 is performed in the drive system of the second modification. Fig. 19 also illustrates the processing contents within the frame F5. Within the frame F5, there are alternately repeated a memory frame F6 for performing charge storage in storage nodes respectively coupled to the charge collecting regions 15, 16, 57 and 58 and a reading frame F4 for performing charge readings from the charge collecting regions 15, 16, 57 and 58 ,
    Fig. 20 is a timing chart illustrating the operation of the transfer electrodes 17, 18, 44, 51 and 52 in the memory frame F6. This drawing illustrates the drive clock CL, the drive voltage Vtx-i applied to the transfer electrode 17, the drive voltage Vtx2 applied to the transfer electrode 18, a drive voltage Vtx3 applied to the transfer electrode 51, a drive voltage Vtx4 applied to the transfer electrode 52, and the transfer electrode 44 applied drive voltage Vtxr.
    In the memory frame F6, the drive voltages Vtx-i to Vtx4 are repeatedly switched at every rise of the drive clock CL between the on-potential and the off-potential twice at a certain cycle T. The cycle T is set to twice the turn-on time tL of the drive clock CL (for example, T = 2tL). Moreover, a turn-on time of the drive voltages Vtx-i to Vtx2 in each cycle is half the turn-on time tL (tL / 2) of the drive clock CL.
    Specifically, the uniform times t0, t-1, ..., and t8 are defined in the memory frame F6 of each of the frames F5, as shown in FIG. An interval between these times is one half of the one-time irradiation time tL of the irradiation light L1. At this time, the light source unit 30 transmits the irradiation light L1 for the times L to t3. Then, the sensor drive circuit 12 sets the drive voltage Vtx-i in each of the frames F5 to the on-potential between the times t0 and L and between the times t4 and t5, the drive voltage Vtx2 to the on-potential between the times t-1 and t2 and between times t5 and t6, the drive voltage Vtx3 to the on potential between times t2 and t3 and between times t6 and t7, and the drive voltage Vtx4 to the on potential between times t3 and t4 and between times t7 and t8 as in FIG. 20.
    Incidentally, the drive voltage Vtxr applied to the transfer electrode 44 is set to the on-potential, for a period of time in which the other drive voltages Vtx-i to Vtx4 are first set to the on-potential and then finally to the off-potential become. That is, in each of the frames F5, the drive voltage Vtxr is set to the off-potential between times t0 and t8 and to the on-potential in the other periods.
    The second modification is an example in which the first frame F1 and the second frame F2 of the first modification are executed together in the single frame F5. Therefore, according to the second modification, it is possible to obtain a value of 1/2 the total charge amount generated by the reflected light L2 similar to the first modification, and further it is possible to set a distance to the object B based on a difference between to obtain the charge amounts stored in the storage nodes respectively coupled to the charge collection regions 15, 16, 57 and 58. That is, the output value of the first frame F1 of the first modification may be replaced by a value obtained by subtracting the charge amount of the charge collection region 15 from the charge amount of the charge collection region 16 in the second modification, and the output value of the second frame F2 of the first modification is replaced by a value obtained by subtracting the charge amount of the charge collecting region 57 from the charge amount of the charge collecting region 58 in the second modification. Therefore, it is possible to apply the current injection circuit 20 of the above embodiment, and thereby it is possible to avoid the saturation of each storage node. Incidentally, in the second modification, a current injection circuit 20 is connected to the charge collection regions 15 and 16, and another current injection circuit 20 is connected to the charge collection regions 57 and 58.
    The distance sensor according to the present invention is not limited to the above-described embodiments, and other various modifications can be made. For example, the case where each transistor is the MOSFET has been illustrated in the above embodiment, but each transistor may be another FET or a bipolar transistor.
    [0085] 1A distance sensor 10 semiconductor substrate 10a surface 10b back surface 10c surface area 11 imaging area 12 sensor driving circuit 13 processing circuit 14 photosensing area 15 first charge collecting area 16 second charge collecting area 17 first transfer electrode 18 second transfer electrode 19 photocoupler electrode 20 current injection circuit 21 voltage generating circuit 22a first transistor 22b second transistor 23a third transistor 23b fourth transistor 24 transistor pair 25 current source 26a, 26b storage node 27,28 buffer circuit 30 light source unit 31 light source 32 light source driver 33 control circuit 34 supply potential line 35,36 reset circuit 41 insulating layer 42,43 signal extraction electrode 100 current injection circuit B object GND reference potential line L1 irradiation light L2 reflected light N1 node P pixel
    Sr Reset signal T Cycle tL On time T1 Light irradiation time T2 Delay time V3, V4, V5, V6 Bias voltage (constant voltage) VCi, VC2 Control voltage
    Vr reset potential
    Vtx-i, Vtx2 control voltage
    权利要求:
    Claims (2)
    [1]
    claims
    A distance sensor (1A) configured to irradiate an object with light and to measure a distance to the object by detecting the light reflected from the object, the distance sensor comprising: a semiconductor substrate (10) having a photosensitive area (FIG. 14) which generates charges corresponding to a light amount of the reflected light, and first and second charge collecting regions (15, 16) which respectively collect the charges from the photosensitive region (14), the first and second charge collecting regions (15, 16 ) are each separated by a predetermined distance from the photosensitive region (14); a first transfer electrode (17) disposed on a region between the photosensitive region (14) and the first charge collection region (15), the first transfer electrode (17) being set to an on potential configured to charge transfer from the photosensitive region (14) to the first charge collecting region (15) during a first period after the light irradiation, and set to an off potential configured to stop the charge transfer during a second period following the first period ; a second transfer electrode (18) disposed on a region between the photosensitive region (14) and the second charge collection region (16), the second transfer electrode (18) being set to an off potential configured to transfer the charge from the photosensitive region (14) to the second charge collection region (16) during the first period, and is set to an on potential configured to allow the charge transfer during the second period; a voltage generating circuit (21) whose one end is connected to a first constant potential line (34) set at a predetermined potential and the other end connected to a second constant potential line (GND) which is at a lower potential is set as the first constant potential line (34), wherein the voltage generating circuit (21) is configured to generate a control voltage having a magnitude larger than an amount of charge in a storage node coupled to the first charge collection area (15) (26a) and an amount of charge stored in a storage node (26b) coupled to the second charge collection area (16); a first and second transistor (24a, 24b) each having a control terminal to which the control voltage is applied, a first power terminal connected to the first constant potential line (34), and a second power terminal; a third transistor (23a) having a first current terminal connected to the second current terminal of the first transistor (24a), a second current terminal connected to the storage node (26a) coupled to the first charge collection region (15), and a control terminal to which a constant voltage is applied; and a fourth transistor (23b) having a first current terminal connected to the second current terminal of the second transistor (24b), a second current terminal connected to the storage node (26b) coupled to the second charge collection region (16) , and a control terminal to which a constant voltage is applied.
    [2]
    2. Distance sensor according to claim 1, wherein the third and fourth transistors (23a, 23b) are MOSFETs.
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    同族专利:
    公开号 | 公开日
    KR102289223B1|2021-08-13|
    JP2017201244A|2017-11-09|
    KR20190002417A|2019-01-08|
    US20200333459A1|2020-10-22|
    US11156700B2|2021-10-26|
    CN109073735A|2018-12-21|
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    JP6659447B2|2020-03-04|
    WO2017191757A1|2017-11-09|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP2016092659A|JP6659447B2|2016-05-02|2016-05-02|Distance sensor|
    PCT/JP2017/015745|WO2017191757A1|2016-05-02|2017-04-19|Distance sensor|
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