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    • 专利摘要:
    The invention relates to a device (100) for generating a reconstructed signal (102) from a pulse width modulated signal (PWM signal) and has a first sampler (104) configured to sample the PWM signal at periodic sampling instants To generate samples of the PWM signal. A low pass filter (106) is configured to produce a low pass filtered version of the PWM signal. A second sampler (108) is configured to sample the low-pass-filtered version of the PWM signal at the sampling instants to produce samples of the low-pass-filtered version of the PWM signal. A signal reconstructor (110) is configured to generate the reconstructed signal (102) based on the samples of the PWM signal and the samples of the low-pass-filtered version of the PWM signal. The invention also relates to a test apparatus for testing a circuit, to a method for generating a reconstructed signal, and to a computer program product having a program code which allows a device according to the invention to operate in accordance with the method according to the invention.
    公开号:CH708292B1
    申请号:CH01052/14
    申请日:2014-07-11
    公开日:2018-04-30
    发明作者:Schöke Achim
    申请人:Keb Automation Ag；
    IPC主号:
    专利说明:

    Description: The invention relates to an apparatus and a method for generating a reconstructed signal from a discrete-time pulse width modulated signal (PWM signal), which may be suitable for driving a circuit, for example a simulated power semiconductor, in a real-time simulation , Furthermore, the invention relates to a corresponding test device.
    Real-time simulation has established itself in recent years as a test and verification method in industrial practice. An important area of application of real-time simulations is the so-called RCP (Rapid Control Prototyping). In this method, a real-time simulator is used to test new control algorithms on a physical link. Using real-time simulation significantly shortens development times because of the increased flexibility and debuggability of powerful real-time simulators. After verification of control algorithms by means of RCP, the implementation can take place on the actual target hardware.
    Again, a real-time simulator can be used to verify the implementation on the target hardware. In this case, industrial-scale hardware-in-the-loop simulation (HIL simulation) is used. HIL means that hardware to be tested is interfaced with real-time simulation hardware. With regard to the hardware to be tested, reference will hereinafter be made by way of example to a control unit which is representative of a hardware to be tested. The task of the real-time simulation hardware is the mathematical simulation of a real physical system. In the following, the real physical system is also referred to as a real system, and the real-time simulation hardware is also referred to below as an HIL simulator or simply as HIL-S.
    The mathematical simulation of the real physical system in the HIL-S is referred to below as a model. The HIL-S replaces the real system to perform test and verification procedures for the control and regulating processes implemented in the control unit. It is assumed that a control unit in a technical application should act on a real system. In order to achieve this in a predetermined manner, the control unit must assume a specific system behavior of the real system. If now this assumed system behavior of the real system is implemented in the HIL-S and the real system is replaced by the HIL-S, the control unit can be tested under idealized and reproducible conditions.
    Of course, a reliable working control unit on the HIL-S does not mean that it works just as well on the real system. Since the real system can have other properties than assumed, an HIL simulation can only be used to test how the control unit behaves, taking into account the assumptions made about the real system. Using the HIL simulation, clearly defined and reproducible test conditions can be created. In comparison, the behavior of a real system depends on many physical factors. Clearly defined and reproducible test conditions are therefore not necessarily given on the real system. The advantage of an HIL simulation in comparison to the direct test on the real system is that a control unit can already be tested before the real system with which the control unit is to be connected is even available. Also, a previous test on the HIL-S prevents the real system from being damaged due to a malfunctioning control unit.
    Due to the required real-time capability of HIL simulators, solver with fixed step size (cycle time) are used to perform a model calculation. In contrast, non-real-time simulations that do not rely on the time required for computation can use a variety of variable-step equation solvers. The smallest time constant of a model determines the maximum permissible step size for an HIL simulation. As a guideline, it has been proven that the cycle time (step size) should be 10 times smaller than the smallest time constant of the model.
    There are conditions that must be considered in an HIL real-time simulation. Thus, the cycle times of a HIL-S must be adapted to the dynamics of the real system to be replicated. The output times of the output signals of an HIL-S must be matched to the sampling times of the input signals of the control unit, and the sampling times of the input signals of an HIL-S must be matched to the output times of the output signals of the control unit.
    In the current state of the art HIL-S can be divided into two broad categories. The first category includes HIL-S, in which a model calculation is realized with the aid of a microprocessor. These so-called PC-based systems are limited in the cycle times due to the sequential operation. Cycle times on today's high-performance HIL-S of this category are a few microseconds for relatively simple models and may increase to tens of microseconds for complex models.
    The second category includes HIL-S, in which the model calculation is outsourced to an FPGA (Field Programmable Gate Array). Due to the parallel structure of an FPGA, shorter cycle times are possible compared to PC-based systems, with cycle times of a few hundred nanoseconds known in practice.
    An important industrial application of the HIL simulation is the electric drive technology and power electronics. In the field of electric drive technology and power electronics, control units are required to control power semiconductors of an inverter with the aid of a PWM signal. A frequency converter with a voltage intermediate circuit is the type of converter most frequently encountered in the industrial environment. It roughly consists of a network-side rectifier, a DC link capacitance and a load-side inverter. The load of the inverter is mostly formed by a three-phase synchronous or asynchronous machine. The inverter is mainly used in industrial practice as a three-phase 2-level inverter. Such an inverter has a total of six power semiconductors to be controlled. 12 shows this type of inverter with the connection to a voltage intermediate circuit formed by a capacitor 10, six power semiconductors 12a to 12f and a load 14. The power semiconductors 12a to 12f are driven by control signals Ui, Vi, Wi, u0, v0 and w0 , In this example, the power semiconductors 12a to 12f are implemented as IGBTs (Insulated Gate Bipolar Transistor). In general, the upper and the lower IGBT of a phase are always driven alternately.
    In principle, simulation models can be subdivided into 3 main groups as a function of the modeling depth. The first group includes models that are modeled at the system level. For the modeling of a voltage source inverter at the system level, for example, the individual switching of the IGBTs would not be considered. Instead, a voltage averaged over the PWM period would be assumed. A more detailed modeling offers the so-called circuit level. At this level, for example, the IGBTs would be modeled as ideal switches. The highest modeling depth is achieved in the so-called component level. The switching on of an IGBT takes place, for example, by the locking time delayed after the correspondingly complementary IGBT has been switched off. The potential curve on the load side, however, is not only dependent on the switch-on and switch-off times of the IGBTs, but is additionally influenced by transfer processes of parasitic capacitances of the IGBTs. However, according to the prior art, there are no HIL real-time models satisfactorily considering this influence.
    For an HIL simulation, it is therefore appropriate to use an idealized inverter model. The structure of this model is shown in FIG. The neglect of the locking times and the parasitic capacitances means that the detection of the three upper drive signals Ui, v-, and w- is usually sufficient for an HIL simulation. Each two complementary switching power semiconductors 12a and 12d, 12b and 12e, and 12c and 12f are thus each simulated by a switch 18, 18 and 20. However, it should be noted that in other models, the drive signals of all power semiconductors can be considered.
    In Fig. 14, a PWM driving pattern with three PWM signals ui, v1 and w1 is shown by way of example, which has a degree of modulation of 80 percent and a ratio of switching frequency to output frequency of 8 to 1. The degree of modulation determines the minimum and maximum level time surface, for example, when specifying a sinusoidal output signal, i. the minimum and maximum ratio of the respective duration of the high level and the low level of the PWM signal during a PWM period (wherein at a modulation level of 0%, the high level and the low level of the PWM signal are equal in length). The switching frequency (PWM switching frequency) corresponds to the reciprocal of the PWM period and the output frequency corresponds to the frequency of the output signal of the inverter. PWM switching frequencies from 2 to 16 kilohertz are standard in industrial practice.
    [0014] PWM switching frequencies in the kilohertz range can no longer be detected by PC-based HIL-S with a sufficiently high time resolution. The state of the art is therefore in PC-based HIL-S, the acquisition of an FPGA to take over. Acquisition times of a few tens of nanoseconds are known in practice. Even with FPGA-based HIL-S, it is customary to accomplish the acquisition of the PWM signals with the aid of an additional FPGA. The hardware for detecting the PWM signals is referred to below as PWM-IN. The model calculation of the HIL-S usually takes place with a longer cycle time than the acquisition of the switching times from the PWM-IN. The consequence of this concept is that at the time of the model calculation, not only the current digital levels of the switch signals from the PWM-IN to the HIL-S must be transferred, but also information about the timing of digital level changes.
    Decisive for a practical HIL-S is not necessarily the consideration of the change of a digital level of the PWM signal at the time of change, but only to know when a level change has taken place to account for this information at the current calculation time of the model ,
    There are HIL-S, which perform only a model calculation synchronous to the PWM switching frequency. A disadvantage of such a method is that due to the resulting averaging switching frequency dependent components are not taken into account and the model calculation has at least one dead time of the size of the PWM period compared to the real system. Another disadvantage is that a synchronization of the HIL-S must be done with the PWM switching frequency. Experience has shown that with cycle times of the HIL-S smaller than a quarter of the smallest PWM period, sufficiently accurate HIL simulations are possible. At a maximum switching frequency of 16 kHz, this corresponds to a cycle time of around 15.6 ps. However, for a practical HIL simulation it was necessary to capture a PWM signal with a much higher resolution. The guideline that the acquisition of a PWM signal should be made at least 100 times per PWM period has been proven in practice. At a maximum switching frequency of 16 kHz, this would mean that the sampling time of the PWM detection may not exceed 625 ns.
    The realization of the accurate timing of a PWM signal in the HIL simulation has the disadvantage in the prior art that the HIL-S must be equipped with additional hardware. This additional hardware must be designed in such a way as to enable provision of the recorded PWM switching times at the calculation times of the HIL-S.
    The object of the present invention is to provide a device and a method that allow the generation of a reconstructed signal from a pulse width modulated signal with reduced effort, and a test device with such a device.
    This object is achieved by a device according to claim 1, a test device according to claim 12 and a method according to claim 14.
    The invention provides an apparatus for generating a reconstructed signal from a pulse width modulated (PWM) signal, comprising: a first sampler configured to sample the PWM signal at periodic sampling instants to obtain samples of the PWM signal; Generate signals; a low pass filter configured to generate a low pass filtered version of the PWM signal; a second sampler configured to sample the lowpass filtered version of the PWM signal at the sampling instants to generate samples of the lowpass filtered version of the PWM signal; and a signal reconstructor configured to generate the reconstructed signal based on the samples of the PWM signal and the samples of the low-pass-filtered version of the PWM signal.
    The invention provides a method for generating a reconstructed signal from a pulse width modulated signal (PWM signal), having the following features:
    Sampling the PWM signal at periodic sampling instants to generate samples of the PWM signal; Low pass filtering the PWM signal to produce a low pass filtered version of the PWM signal;
    Sampling the lowpass filtered version of the PWM signal at the sampling instants to produce samples of the lowpass filtered version of the PWM signal; and
    Generating the reconstructed signal based on the samples of the PWM signal and the samples of the low-pass filtered version of the PWM signal.
    The invention is based on the basic idea not to read in a PWM signal, as usual, only digitally via corresponding digital inputs of a real-time system, but to additionally subject the PWM signal to a previous low-pass filtering. The low pass filtered PWM signal is then sampled at the sampling instants at which the non-low pass filtered PWM signal is also sampled, wherein the samples of the low pass filtered PWM signal depend on the time constant of the low pass filter. Embodiments of the invention take advantage of the fact that with a PWM signal, the level changes at most twice per PWM period, so that the samples of the low-pass filtered PWM signal together with the samples of the PWM signal draws a conclusion on a course of the PWM signal. Allow signal. Thus, based on the samples of the PWM signal and the samples of the low-pass filtered PWM signal, the reconstructed signal representing a reconstruction of the PWM signal may be generated.
    Thus, the invention enables a detection of a PWM signal, for example, for a real-time simulation using a significantly reduced compared to previous approaches sampling frequency and thus with significantly reduced effort.
    The level of the reconstructed signal at the sampling instants corresponds to the level of the PWM signal. Whether and when level changes in the reconstructed signal occur between the sample points is determined on the basis of the samples of the low-pass filtered version of the PWM signal.
    In embodiments, the sampler is configured to sample the PWM signal at sampling instants whose sampling period is less than a PWM signal period of the PWM signal or less than one-half of a PWM signal period of the PWM signal. In embodiments of the method according to the invention, the PWM signal is sampled at sampling instants whose sampling period is less than a PWM signal period or whose sampling period is less than half the PWM signal period.
    In embodiments, when two consecutive samples of the PWM signal have different levels, the time of a level change between the two consecutive samples is calculated based on the samples of the low-pass filtered version of the PWM signal. In embodiments, the sample period may be set relative to a duty cycle of the PWM signal such that no more than one level change between two samples in the PWM signal may occur. For example, the sampling period may be set relative to a minimum duty cycle and a maximum duty cycle such that a maximum of one level change may occur during a sampling period, wherein at the minimum duty cycle, a high level duration of the PWM signal is minimum and at the maximum duty cycle the duration of the high level of the PWM signal is maximum. In such embodiments, a time for a level change in the reconstructed signal between two consecutive samples of the signal is calculated when the level of two consecutive samples is different, and there is no level change in the reconstructed signal when the level of two consecutive samples of the PWM signal is equal to.
    In embodiments, when two consecutive samples of the PWM signal have the same level, a period of time is calculated based on the samples of the low-pass filtered version of the PWM signal, while the reconstructed PWM signal is centered in the sampling period between the consecutive ones Samples having the other level. Such embodiments are based on the recognition that in order to reconstruct the signal for such a case, it is sufficient to determine the appropriate time duration and to center in the sampling period, thus an error that occurs because the time points of the level changes can not be accurately determined , to minimize.
    Embodiments further include a simulator configured to simulate a PWM signal dependent behavior of a circuit using the reconstructed signal in real time. The simulator can be an HIL simulator. For this purpose, the simulator may comprise a feedback signal output configured to output a feedback signal indicating the result of the behavior of the circuit to a device outputting the PWM signal.
    The invention provides a test device for testing a first circuit having a corresponding device for generating a reconstructed signal, a corresponding simulator and an evaluator, which is coupled to an output of the simulator, and configured to be based on a the output of the simulator signal to a behavior of the device that outputs the PWM signal to check.
    Embodiments of the invention are explained below with reference to the accompanying drawings. It shows:
    Fig. 1 is a schematic representation of an embodiment of an apparatus for Erzeu gene of a reconstructed signal;
    Figs. 2A to 2C are schematic diagrams of signal waveforms for explaining the invention;
    Fig. 3 is a schematic representation of waveforms of a first case;
    4 is a schematic representation of signal curves of a second case;
    Fig. 5 is a schematic representation of waveforms of a third case;
    Fig. 6 is a schematic illustration of waveforms of a fourth case;
    Figs. 7A to 7D are signal diagrams for explaining embodiments of the invention;
    and FIGS. 8A to 8D
    9A to 9D are diagrams showing an influence of different filter times;
    10 is a schematic representation of a test device according to an embodiment;
    Fig. 11 shows waveforms showing different reconstructions;
    Fig. 12 is a schematic illustration of an example of an inverter;
    Fig. 13 is a schematic representation of a model of the inverter of Fig. 12;
    Fig. 14 is an example of a PWM driving pattern with three PWM signals;
    15A to 15D are schematic diagrams for explaining an influence of the degree of modulation; and
    16 to 19 are schematic waveforms for explaining embodiments in which the sample period is not less than half of the PWM signal period.
    1 shows an exemplary embodiment of a device 100 for generating a reconstructed signal 102. The device 100 has a first sampler 104, a low-pass filter 106, a second sampler 108 and a signal reconstructor 110. An input of the first sampler 104 is connected to an input of the device at which a PWM signal 112 is received. An input of the low pass filter is also connected to the input at which the PWM signal 112 is received. An input of the second sampler 108 is connected to the output of the low pass filter 106. An output of the first sampler 104 is connected to a first input of the signal reconstructor 110, and an output of the second sampler 108 is connected to a second input of the signal reconstructor 110.
    The first sampler 104 is configured to sample the PWM signal 112 at respective sampling instants corresponding to one sampling period and to output samples of the PWM signal to the signal reconstructor. The samples of the PWM signal 112 indicate whether the level of the PWM signal is high or low. For example, the first sampler may include a threshold comparator for comparing the PWM signal with a threshold and outputting the samples of the PWM signal depending on the result of the comparison. The threshold comparator can be formed by a digital input of the real-time simulator.
    The low-pass filter 106 may be implemented, for example, by a hardware-built RC element with a time constant τ = RC. This time constant can also be referred to as filter time. The output signal of the
    Low pass filter 106 may be provided as an analog value to the input of second sampler 108. The second sampler 108 may be implemented, for example, as an analog-to-digital converter (ADC), the input of which is an analog input. The second sampler 108 outputs the samples of the low-pass-filtered version of the PWM signal 112 to the signal reconstructor 110.
    In embodiments, the analog-to-digital converter may be part of a real-time simulator, such that the low-pass-filtered PWM signal is provided to the real-time simulator via a corresponding analog input. Advantageously, the fact that real-time simulators available on the market are usually equipped with a plurality of analog-to-digital converters (ADCs) can be used. These ADCs are required in HIL simulations as well as in RCP simulations to process analog values provided by the hardware in the test setup in the real-time simulator.
    The signal reconstructor 110 may be implemented by any hardware capable of generating the reconstructed signal based on the samples. The signal constructor 110 may, for example, be implemented as a computer, that is, microprocessor-based, which receives the samples at suitable interfaces and performs the corresponding calculations. Alternatively, the signal reconstructor may also be implemented by an FPGA or an ASIC (Custom Integrated Circuit).
    The theory underlying the present invention is explained in more detail below, which is based on the reconstruction of the PWM signal. It does not require a separate explanation that the signal reconstructor 110 is appropriately configured or programmed to perform the calculations required for the reconstruction. For example, the signal reconstructor may be implemented as part of an HIL simulator whose cycle time at which the PWM signal and the low-pass filtered PWM signal are sampled corresponds.
    A digital PWM signal has the property that it may have two different levels, and during a PWM period, the level thereof may change a maximum of twice. The timing of the level changes depends on the current duty cycle, with the minimum and maximum duty cycles depending on the degree of modulation.
    The theory underlying the invention is based on the assumption that the level of a PWM signal changes at most twice within the sampling period. Since the pulse width of a PWM signal can vary from zero to at most the PWM period and no synchronization of the HIL-S with the switching frequency should be provided, the maximum theoretical limit for the sampling period is less than half of the PWM period. Thus, using the reconstructed signal for simulating an inverter as described above with respect to FIGS. 12 and 13, the maximum theoretical limit for the sample period is less than half the minimum PWM period, that is the inverse the maximum switching frequency (the power semiconductor or switch) corresponds.
    The background for the inventive procedure of the low-pass filtering of the PWM signal is not justified in the observance of Shannon's sampling theorem. The Shannon sampling theorem states that a signal can only be uniquely reconstructed if it is band limited before a discrete-time sample. This method of reconstructing a sampled signal by means of linear operations is referred to in the art as DFT (Digital Fourier Transform). It should be noted that the Shannon sampling theorem refers to a reconstruction of a signal by means of linear operations. By low-pass filtering, frequency components of the PWM signal are lost. However, since an idealized PWM signal has infinitely high frequency components, it is impossible or only error-prone to reconstruct the original, unfiltered signal by means of linear operations. In embodiments of the invention, in contrast to the DFT method, the low-pass filtering and the application of non-linear operations enable the temporal reconstruction of a PWM signal. This reconstruction can be based on the reconstruction of switching times and / or the reconstruction of level time areas, as will be explained below.
    The method will now be explained with reference to FIGS. 2A to 2C by way of example. In Fig. 2A, the HIL-S input signals needed for a reconstruction of the switching instants are shown. These are a digital PWM signal 120 (PWM), which may, for example, be supplied directly by a control unit and, in addition, a low-pass filtered analog signal 122 (PWM filter) generated from this PWM signal. Further, in Fig. 2A, the PWM period is shown by dashed lines.
    Fig. 2B shows these two signals after a discrete-time scan, which can be done for example by a HIL-S. The digital PWM signal is shown as a sample-and-hold signal for clarity. In contrast, the analog, low-pass filtered PWM signal is only shown as sample points. The two signals are sampled at the same sampling times, the sampling period being indicated by dashed lines in Fig. 2B and being designated as the HIL-S period. Since the sampling is asynchronous, it can be clearly seen that the level changes of the PWM signal occur asynchronously to the HIL-S sampling period. If only the sampled digital PWM signals are used to determine switching operations, then in the worst case, a level time area smaller than the sampling period (cycle time of the HIL-S) can not be detected at all.
    FIG. 2C shows a signal 124 that has been reconstructed based on the samples of the PWM signal 120 and the samples of the low-pass-filtered version of the PWM signal 122. As information for the choice of suitable nonlinear
    Operations for the reconstruction of the switching instants, the level of the digital PWM signal at the current calculation time point and the digital level of the last calculation time point can be used (wherein calculation time equates to sampling time point).
    With the assumption that per sample period, the levels can change only a maximum of twice, resulting in a total of four variants or modes to be considered.
    If the level at the current sampling time of the PWM signal is high and the level at the last sampling time is low, then assuming that a maximum of two switching cycles per sample period (of the HIL-S) occurs. can, inevitably, that exactly one level change from deep to high within the sampling period has taken place. The same is true for a level change from high to low. Again, only a level change may have occurred. The other two variants arise when the levels of the last sampling time and the current sampling time are the same. If both levels are high, then it may be that within the sample period, a level change from high to low and back from low to high has occurred. If both levels are low, it may be that a level change from low to high and back from high to low has occurred.
    In the first two variants, in which a level change is detected by the evaluation of the digital signal, the exact switching time can be determined with the inventive method. However, this only applies assuming an ADC with infinitely high resolution for sampling the low-pass filtered version of the PWM signal. When implemented by an ADC with real resolution results in a determination of the switching time (time of level change), the accuracy of which depends on the resolution of the ADC.
    For the last two variants, in which no digital level change is detected, the level time surface can be calculated by the low-pass filtering of the PWM signal. The accuracy of this calculation depends on the filter time of the low-pass filter. By a large compared to the cycle time of the HIL-S filter time theoretically a high accuracy of the calculation of the level time surface can be achieved. However, a large filter time reduces the accuracy of the AD conversion that is subjected to the low-pass filtered PWM signal because the ADC measurement range is no longer optimally utilized. It has been found that even with a filter time which is half the sampling period, an accuracy sufficient for example for an inverter simulation can already be obtained. By level-time-surface is meant the duration for which the reconstructed signal during the sampling period is at the level different from the level of the samples of the PWM-signal.
    The optimum filter time for the low-pass filtering of the PWM signal can be determined taking into account the discrete-value resolution of the ADC and an assumed input noise of the analog low-pass filtered PWM signal so that the average error in the reconstruction of the switching times is minimized.
    Calculation rules for the reconstruction of a switching time or for reconstruction of a level time surface in embodiments of the invention will be described in more detail below, as low-pass filter, for example, an RC filter with a time constant or filter time τ = RC can be used. It should be noted that the reconstructed signal or sections of the reconstructed signal in the figures are designated by "PWM reconstruction".
    The four possible switching variants are referred to as MODE1, MODE2, MODE3 and MODE4.
    The following terms are used in the mathematical equations, where k represents a running index for the sampling times: TP: sampling period (corresponding to the cycle time of the HIL-S)
    Filter time: Smoothing time or time constant of the hardware-based RC element with which the PWM
    Signal low-pass filtered PWMFiiter (k-1): sampled, low-pass filtered PWM signal from the last calculation time PWMpter (k): sampled, low-pass filtered PWM signal from the current calculation time point Fig. 3 shows the variant MODE1. This occurs when the level of the sampled digital PWM signal from the current sampling instant is high and the level of the digital PWM signal from the last sampling instant is low. The calculation rule for the switching time tMoDEi with reference to the last sampling time is given in equation GL.1:
    The variant MODE2 shown in Fig. 4 is when the level of the sampled digital PWM signal at the current sampling time is low and the level of the digital PWM signal at the last sampling time is high. The calculation rule for the switching time based on the last sampling time is given in equation GL.2.
    The variant MODE3 shown in Fig. 5 is when the level of the sampled digital PWM signal is low at the current sampling time and the level of the digital PWM signal at the last sampling time is low. The calculation instructions for the switching times tM0DE3-i and tMODE3-2 in relation to the last sampling time are given in Equations GL.3.1 and GL.3.2:
    The variant MODE4 shown in Fig. 6 is when the level of the sampled digital PWM signal from the current sampling time is high and the level of the digital PWM signal from the last sampling time is high. The calculation instructions for the switching times tM0DE4-i and tMODE4-2 in relation to the last sampling time are given in equations GL.4.1 and GL.4.2:
    As already mentioned, the exact switching times can be determined in the MODE1 and MODE2 under idealized conditions. In contrast, in MODE3 and MODE4, at least approximately the exact level time surface can be determined. This applies if the filter time from the hardware-based RC element is much larger than the sampling period (cycle time of the HIL-S).
    The calculation rule in MODE3 and MODE4 has the advantageous property that the level changes are assumed to be symmetrical to the middle of the sampling period. This assumption minimizes the mean error in the determination of the level-time area. With an infinitely large assumed low-pass filtering of the PWM signal, the level time surface can be calculated exactly. The calculated level time area then has only a phase shift compared to the real level time area. In practice, however, it should be noted that this effect is affected by the accuracy of AD conversion.
    In the event that in MODE3 and MODE4 no level change between the two sampling times has taken place, the calculation rules according to the equations GL.3.1, GL3.2, GL.4.1 and GL.4.2 no switching times that in the considered sampling interval lie and the reconstructed signal has no level change between the two sampling times.
    The described properties of the method are further illustrated by FIGS. 7A to 7D. It is assumed that a level-time area has the width of half a sampling period and that this level-time area is sampled asynchronously by a HIL-S. The diagrams in Figs. 7A to 7D are snapshots of the passage of the level time area from left to right through the sampling period, referred to as the HIL-S period. A filter time of the low-pass filtering of the PWM signal is assumed which has the value of half the sampling period. The resolution of the ADC was assumed to be infinitely high. Noise in the sampling of the low-pass filtered PWM signal has been neglected.
    In Fig. 7A, the level time area has partially run into the sampling period. The HIL-S detects a low level for the digital PWM signal at the current time tk and a high level for the digital PWM signal at the last time tk_ · ,. Thus, MODE2 is valid. The time of the level change from high to low can be determined exactly for this case. This property in MODE2 is shown graphically as a signal "PWM reconstruction".
    In Fig. 7B, the level-time area has just run completely into the sampling period of the HIL-S. The HIL-S detects a low level for the digital PWM signal at the current time tk and a low level for the digital PWM signal at the last time tk_ · ,. Thus, MODE3 is valid. The time of the level change from low to high and back again from high to low can not be determined exactly in this mode. The calculation rule causes a level time area to be taken symmetrically to the middle of the sampling period. The consequence of the low filter time is that the calculated level time surface is smaller than the real level time surface and it is additionally shifted to the right. This property in MODE3 is graphically represented as PWM reconstruction.
    In Fig. 7C, the level-time area in the PWM signal is just centered on the sample period of the HIL-S. The HIL-S detects a low level for the digital PWM signal at the current time tk and a low level for the digital PWM signal at the last time W. Thus, MODE3 is valid again. The time of the level change from low to high and back from high to low is now determined exactly because the real level time surface is as expected in the middle of the sampling period of the HIL-S. This property in MODE3 is shown graphically in FIG. 7C as "PWM reconstruction".
    In Fig. 7D, the level time area has partially drained from the sampling period of the HIL-S. The HIL-S detects a high level for the digital PWM signal at the current time tk and a low level for the digital PWM signal at the last time tk_i. Thus, MODE1 is valid. The time of the level change from low to high can be determined exactly for this case. This property in MODE1 is plotted as "PWM reconstruction" in Fig. 7D. Figs. 8A to 8D again show the passing of the level time area through the HIL-S sample period, comparing the filter time of the low-pass filtering of the PWM signal to the example of FIGS. 7A to 7D has been increased by a factor of eight. It can be seen in Fig. 8B that the larger filter time in MODE3 causes less error in the reconstructed level time area.
    As already stated, an error minimization of the reconstructed level time surface can be achieved under idealized conditions by an infinitely high filter time. In practice, however, the resolution of the ADC and noise at the input of the ADC must be taken into account when designing the filter time.
    These influences are shown in principle in FIGS. 9A to 9D. It is assumed, as previously, that a level-time area has the width of one half cycle time of the HIL-S, and that this level-time area passes through the sampling period of the HIL-S. In Fig. 9A, the proportion of the level-time areas which is present when passing through the sampling period of the HIL-S is shown. The left-hand side of the trapezoid arises because the level-time surface first enters the sampling period. The horizontal portion of the trapezoid results when the level-time area is completely within the sampling period. The right sloping trapezoidal side results when the level time surface emerges from the HIL-S sampling period. FIG. 9B shows the level time areas reconstructed as a function of the filter time. As already illustrated by FIGS. 7A to 8D, an increase in the filter time will result in a better reconstruction of the level time area, if this level time area is completely within the sample period of the HIL-S. Due to a limited resolution of the ADC and noise at the input of the ADC, the amount of filter time is limited. The influence of a limited resolution of the ADC is shown in Fig. 9C. Fig. 9D shows the influence of noise at the input of the ADC.
    The case that a level-time area is completely within a sampling period can only occur when the level-time area is smaller than the sampling period. For a 3-phase PWM as shown in Fig. 14, this is the case when the degree of modulation exceeds the value indicated in GI.5.
    GL.5 In GL.5, the switching frequency indicates the reciprocal of the period of the PWM signal. The sampling period TP can thus be selected such that, for a degree of modulation which lies between a minimum degree of modulation and a maximum degree of modulation, the variants MODE3 and MODE4 do not even occur. In such a case, the reconstruction merely comprises the determination of the time points of the level changes when the levels of successive samples of the PWM signal are different. If the levels of successive samples in such a case are equal, no level change is effected in the reconstructed signal between the successive samples.
    To clarify the relationships between sampling period, degree of modulation and the occurrence of the variants MODE3 and MODE4 reference is further made to FIGS. 15A to 15D, the three PWM signals Ui, v-ι and wi for driving an inverter with different degrees of modulation show , These figures show the situation at an output frequency (the output signal of an inverter to be simulated) of 500 Hz, a switching frequency (1 / PWM period) of 8 kHz and a sampling period (sampling time HIL simulator) of 15 ps. The representations extend over an output period of 2 ms, with the pulse pattern repeated for the selected output frequency of 500 Hz every 2 ms. Fig. 15A shows the situation at a modulation degree of 0%, Fig. 15B the situation at a modulation degree of 50%, Fig. 15C the situation at a modulation depth of 76% and Fig. 15D the situation at a modulation depth of 100%. As can be seen in Figures 15A and 15B, at a modulation level below 76%, the MODE3 and MODE4 variants do not occur, while at a modulation level of 100%, they are most common.
    It is possible that MODE3 and MODE4 are detected very frequently in reality. However, this only matters for the accuracy if in fact a double level change between the two sampling times has taken place. Otherwise, the restrictions described regarding the accuracy of the reconstruction do not apply.
    The calculation instructions GL.1 to GL.4.2 for the reconstruction of a switching time, or for the reconstruction of a level time surface, can be simplified by linearization. This results in linearized calculation rules according to the equations GL.6 to GL.9.2:
    If the filter time is assumed to be infinitely high, the same results are obtained with the linearized equations as with the nonlinear equations. However, as already mentioned, the choice of high filter time is limited by the resolution of the ADC and by noise effects at the input of the ADC. For this reason, better and better results are achieved in practice with the nonlinear equations GL.1 to GL.4.2 than with the linearized equations GL.6 to GL.9.2.
    Devices and methods for reconstructing a signal, and in particular a PWM signal, can be used, for example, in an HIL simulation in which a device is to be tested which outputs a PWM signal, for example, as a control signal. FIG. 10 shows a test device having an HIL simulator 200 and an evaluator 202. The HIL simulator has a first interface 204 for receiving the PWM signal from a device under test 206. The device under test is not part of the test device and therefore shown in dashed lines. The HIL simulator further includes a second interface 208 for outputting a feedback signal to the device under test 206. The evaluator 202 is connected to an output of the HIL simulator, which may correspond to the second interface 208, and is configured to test a behavior of the device under test based on the corresponding output of the HIL simulator. In this respect, the structure of the test device can correspond to known test devices, as described in the introduction to the description. In embodiments of the invention, the HIL simulator includes an apparatus 100 for generating a reconstructed signal as described herein.
    In embodiments, the HIL simulator may be an HIL simulator for simulating an inverter as described in the opening paragraph describing the behavior of an inverter based on the three PWM signals Ui, v-1 and Wi (see FIG. 14). simulated. The HIL simulator can have three corresponding devices 100 in order to generate an input signal for the simulation for each of these PWM signals.
    11 illustrates the performance of the method using an exemplary embodiment of such an HIL simulator. In the upper part of Fig. 11, the three PWM signals ui, v- and w-i are shown, which are supplied by a control unit. These are used to control a three-phase 2-level voltage source inverter. The load of the inverter is formed by a three-phase, permanent magnet synchronous machine. The task of the HIL-S is to calculate the phase currents of the motor. The necessary model consists of the replica of the voltage source inverter and the load. As inputs, the HIL-S receives the three-phase PWM (signals Ui, v1f w-i). For reference, a phase current 300 is shown in the upper part of FIG. 11, which results in a cycle time of the HIL-S of 100 ns. The cycle time refers to the acquisition of the PWM, the calculation of the motor current and the output of this current via a corresponding DAC.
    Section a) of FIG. 11 shows the calculated current 302 in the application of the inventive method with a cycle time of the HIL-S of 15 ps. The cycle time again relates to the acquisition and reconstruction of the PWM, the model calculation and the output of the model current via a corresponding DAC. Compared to the reference current, the 15-ps raster of the calculation time of the model current can be clearly seen. In practice, a real measured current for processing in a control unit is usually smoothed beforehand for the sake of noise suppression with the aid of a hardware-based analog low-pass filter. The lower illustration in section a) of FIG. 11 shows, by way of example, the model current and the reference current after an analog smoothing of 30 ps. It can be seen that the reference current and the model current agree well.
    Section b) of FIG. 11 shows the calculated current 304 when applying the linearized calculation rules. In the lower area of section b), a deviation between the reference current and the model current can be seen.
    Section c) of FIG. 11 shows the calculated current 306 at a cycle time of 1 ps without application of the inventive method. In the lower area of section c), a slight drift of the model current from the reference current can be seen. This result confirms the empirical value that PWM detection should be performed at least 100 times per PWM period. With the 16kHz sounding frequency assumed in this example and a 1 ps HIL-S cycle time, detection of PWM occurs only 63 times per PWM period.
    Embodiments thus allow an accurate simulation with a significantly lower number of samples, whereby already with a 2 times sampling per PWM period, a switching time or a level time surface can be reconstructed having sufficient for a simulation example of an inverter accuracy ,
    Embodiments of the invention are particularly advantageous in that the sampling period with which the PWM signal and the low-pass filtered version of the PWM signal are sampled may correspond to the cycle time or step size of the HIL simulator. Embodiments of the invention thus make it possible to extend a real-time simulator for HIL simulations so that it is possible to dispense with accurate time detection of a PWM signal by means of the described PWM-IN hardware.
    In other words, embodiments thus provide methods for reconstructing a discrete-time digital signal in which a built-in hardware low-pass filter is provided. The input of the low-pass filter can be connected to the digital signal to be reconstructed. The output of the low-pass filter can be detected time-discretely using an analog-to-digital converter. The acquired time-discrete low-pass filtered signal can be used for mathematical calculations for reconstruction. The mathematical calculations can be selected as a function of the discrete-time digital signal.
    Embodiments of the invention have been described in the context of the application in the field of electrical drive technology and power electronics. These embodiments are intended to serve as an example and not limit the present invention to this field. Rather, the invention is applicable everywhere where a PWM signal using a reduced number of samples is to be detected or reconstructed time-discrete.
    In embodiments of the invention, the PWM signal may be sampled with a sample period no greater than a quarter of the PWM signal period, allowing a more accurate reconstruction of the PWM signal, since the probability that the above described variants MODE3 and MODE4 are decreasing. Accordingly, the first and second samplers may be configured to sample the PWM signal with a sampling period that is no greater than a quarter of the PWM signal period.
    Although embodiments of the invention have been described above with respect to a theory in which the PWM signal changes its level at most twice within a sampling period, this is not a mandatory requirement. There may also be applications where sampling with a larger sampling period, for example a sampling period between half the PWM signal period and the full PWM signal period, may be sufficient for reconstruction, for example in the simulation of large time constant models. In such applications, it may be sufficient that the sampling period is not greater than the PWM signal period, so that at least level time areas can be reconstructed using the method according to the invention in order to reconstruct the signal therefrom. Examples of such reconstructions are shown in FIGS. 16-19.
    Referring now to Figs. 16 to 19, a case where the sampling period corresponds to the PWM signal period will be explained, and the corresponding considerations will of course apply if the sampling period is between half of the PWM signal period and the PWM signal period. Signal period is. In the upper area of FIGS. 16 to 19, the PWM signal is shown, in the middle area the result of the sampling of the PWM signal at times tk-i and tk (as a sample-and-hold signal) and in the lower area the reconstructed signal.
    16 and 17 show cases of a PWM reconstruction in which the theoretical limit (sampling period <half PWM period) is not met and the variant MODE1 is present. In Fig. 16, the level of the PWM signal changes three times within the sampling period (HIL-S period). The calculation rules described above were used for PWM reconstruction. The additional block in the PWM signal is taken into account (due to the above-described calculation rules) by a block extension in the PWM reconstruction. With a very large filter time, the block extension corresponds to the duration of the additional block. With a small filter time, the block extension is shorter than the additional block. Fig. 17 shows a similar case, but in which the position of the additional block is different in the sampling period (the HIL-S). As can be seen from the reconstructed signal in Figs. 16 and 17, the position of the additional block in the PWM signal has no influence on the block extension in the PWM reconstruction.
    Figs. 18 and 19 show cases of PWM reconstruction in which the theoretical limit (sampling period <half PWM period) is not satisfied and the variant MODE2 is present, in Fig. 18, the level of the PWM signal changes three times within the sampling period (HIL-S period). The calculation rules described above were used for PWM reconstruction. The additional block in the PWM signal is taken into account (due to the above-described calculation rules) by a block extension in the PWM reconstruction. With a very large filter time, the block extension corresponds to the duration of the additional block. With a small filter time, the block extension is longer than the additional block. Fig. 19 shows a similar case, but in which the position of the additional block in the sampling period (the HIL-S) is different. As can be seen from the reconstructed signal in Figs. 18 and 19, the position of the additional block in the PWM signal has no influence on the block extension in the PWM reconstruction.
    From the above explanations of FIGS. 16 to 19 shows that even if the theoretical limit is not yet a reconstruction is possible, but then not the individual switching times can be reconstructed, but only a reconstruction of the level duration.
    The limit of the sampling period for a practical HIL-S is generally determined by the feedback signals returned to the controller. Advantageous embodiments of the invention can therefore use a sampling period of not more than one quarter of the PWM signal period, for example a sampling period lying in a range of one sixth of the PWM signal period to one quarter of the PWM signal period.
    Although some aspects have been described in the context of a device, it should be understood that these aspects also constitute a description of the corresponding method such that a block or device of a device is also to be understood as a corresponding method step or feature of a method step is. Similarly, aspects described in connection with or as a method step also represent a description of a corresponding block or detail or feature of a corresponding device.
    Depending on particular implementation requirements, embodiments of the invention may be implemented in hardware or in software. The implementation may be using a digital storage medium, such as a floppy disk, a DVD, a Blu-ray Disc, a CD, a ROM, a PROM, an EPROM, an EEPROM or FLASH memory, a hard disk, or other magnetic or optical memory are stored on the electronically readable control signals, which can cooperate with a programmable computer system or cooperating, that the respective method is performed. Therefore, the digital storage medium can be computer readable. Thus, some embodiments according to the invention include a data carrier having electronically readable control signals capable of interacting with a programmable computer system such that one of the methods described herein is performed.
    In general, embodiments of the present invention may be implemented as a computer program product having a program code, wherein the program code is operable to perform one of the methods when the computer program product runs on a computer. The program code can also be stored, for example, on a machine-readable carrier.
    Other embodiments include the computer program for performing any of the methods described herein, wherein the computer program is stored on a machine-readable medium.
    In other words, an embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer. Another embodiment of the inventive method is
    权利要求:
    Claims (22)
    [1]
    thus a data carrier (or a digital storage medium or a computer readable medium) on which the computer program is recorded for performing one of the methods described herein. A further embodiment of the method according to the invention is thus a data stream or a sequence of signals, which represents the computer program for performing one of the methods described herein. The data stream or the sequence of signals may be configured, for example, to be transferred via a data communication connection, for example via the Internet. Another embodiment includes a processing device, such as a computer or a programmable logic device, that is configured or adapted to perform one of the methods described herein. Another embodiment includes a computer on which the computer program is installed to perform one of the methods described herein. In some embodiments, a programmable logic device (eg, a field programmable gate array, an FPGA) may be used to perform some or all of the functionality of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform one of the methods described herein. In general, in some embodiments, the methods are performed by any hardware device. This may be a universal hardware such as a computer processor (CPU) or hardware specific to the process, such as an ASIC. The embodiments described above are merely illustrative of the principles of the present invention. It will be understood that modifications and variations of the arrangements and details described herein will be apparent to others of ordinary skill in the art. Therefore, it is intended that the invention be limited only by the scope of the appended claims and not by the specific details presented in the description and explanation of the embodiments herein. claims
    An apparatus (100) for generating a reconstructed signal (102) from a pulse width modulated signal, PWM signal (112), comprising: a first sampler (104) configured to receive the PWM signal (112) sampling periodic sampling instants to generate samples of the PWM signal (112); a low pass filter (106) configured to generate a low pass filtered version of the PWM signal; a second sampler (108) configured to sample the low-pass-filtered version of the PWM signal at the sampling instants to produce samples of the low-pass-filtered version of the PWM signal; and a signal reconstructor (110) configured to generate the reconstructed signal (102) based on the samples of the PWM signal and the samples of the low-pass-filtered version of the PWM signal.
    [2]
    The apparatus of claim 1, wherein the signal reconstructor (110) is configured to calculate the time of a level change between two consecutive samples based on the samples of the low-pass filtered version of the PWM signal when the two consecutive samples of the PWM signal have different levels.
    [3]
    The apparatus of claim 1 or 2, wherein the signal reconstructor (110) is configured to, when two consecutive samples of the PWM signal have the same level, calculate a time period based on the samples of the low-pass filtered version of the PWM signal during which the reconstructed PWM signal centered in the sampling period between the consecutive samples has the other level.
    [4]
    An apparatus according to any one of claims 1 to 3, wherein when the sample value of the PWM signal at a sampling time k-1 is a low level and the sample value of the PWM signal is high at an immediately subsequent sampling time k Switching time tMoDEi for the reconstructed signal is calculated as follows:

    and wherein, when the sample value of the PWM signal at the sampling time k-1 is a high level and the sample value of the PWM signal at the immediately succeeding second sampling time k is at a low level, a switching time tM0DE2 for the reconstructed signal is calculated as follows becomes:

    where Tp is the sample period, PWMFiiter (k-1) is the sample of the low-pass filtered PWM signal at sample time k-1, PWMpiiter (k) is the sample of the low-pass filtered PWM signal at sample time k, filter time is the time constant of the low-pass filter, and k Is the running index of sampling times.
    [5]
    5. The apparatus of claim 4, wherein when the sample of the PWM signal at a sample time k-1 has a low level and the sample of the PWM signal at an immediately subsequent sample time k has a low level, a first switching time tMoDE3- i and a second switching time tM0DE3-2 for the reconstructed signal are calculated as follows:

    and wherein when the sample of the PWM signal at a sampling instant k-1 is high and the sample of the PWM signal at a subsequent sampling instant k is high, a first switching time tMoDE4-i and a second switching timing tM0DE4 -2 for the reconstructed signal are calculated as follows:


    [6]
    The apparatus according to any one of claims 1 to 3, wherein when the sample of the PWM signal has a low level at a sampling time k-1 and the sample of the PWM signal has a high level at an immediately subsequent sampling time k Switching time îModei for the reconstructed signal is calculated as follows:

    and wherein, when the sample value of the PWM signal at the sampling time k-1 is a high level and the sample value of the PWM signal at the immediately succeeding second sampling time k is at a low level, a switching time tMODE2 for the reconstructed signal is calculated as follows becomes:

    where Tp is the sampling period, PWMR |, er (k-1) is the sample of the low-pass filtered PWM signal at sampling time k-1, PWMniter (k) is the sample of low-pass filtered PWM signal at sampling time k, and filtering time is the time constant of the low-pass filter and k is a running index of sampling times.
    [7]
    7. The apparatus of claim 6, wherein when the sample of the PWM signal at a sampling time k-1 has a low level and the sample of the PWM signal at an immediately subsequent sampling time k has a low level, a first switching time tMoDE3- i and a second switching time tM0DE3-2 for the reconstructed signal are calculated as follows:

    and wherein, when the sample of the PWM signal is high at a sampling time k-1 and the sample of the PWM signal is high at an immediately subsequent sampling time k, a first switching timing tM0DE4-i and a second switching timing tM0DE4 -2 for the reconstructed signal are calculated as follows:


    [8]
    8. The device of claim 1, wherein the PWM signal has a duty cycle that is between a minimum duty cycle at which a duration of the high level of the PWM signal is minimum and a maximum duty cycle at which the duration of the high level of the PWM signal is maximum, wherein the sampling period is set relative to the minimum duty cycle and the maximum duty cycle such that a maximum of one level change may occur during a sampling period.
    [9]
    The apparatus of any one of claims 1 to 8, wherein the first sampler (104) is configured to sample the PWM signal at sampling instants whose sampling period is less than one PWM signal period of the PWM signal or less than half a PWM signal period of the PWM signal.
    [10]
    10. The apparatus of claim 1, further comprising a simulator configured to simulate in real time a behavior of a circuit dependent on the PWM signal using the reconstructed signal.
    [11]
    The apparatus of claim 10, wherein the simulator (200) comprises a feedback signal output (208) configured to provide a feedback signal indicating the result of the behavior of the circuit to a device (206) containing the PWM signal spend, spend.
    [12]
    12. A test device for testing a first circuit (206), comprising: an apparatus according to claim 11; and an evaluator (202) coupled to an output of the simulator (200) and configured to, based on a signal output at the output of the simulator (200), behave as the device (206) receiving the PWM signal issues, check.
    [13]
    The test apparatus of claim 12, wherein the output of the simulator (200) is the feedback signal output (208).
    [14]
    14. A method of generating a reconstructed signal from a pulse width modulated signal, PWM signal, comprising: sampling the PWM signal at periodic sampling instants to produce samples of the PWM signal; Low pass filtering the PWM signal to produce a low pass filtered version of the PWM signal; Sampling the low-pass-filtered version of the PWM signal to the sampling time points to produce samples of the low-pass-filtered version of the PWM signal; and generating the reconstructed signal based on the samples of the PWM signal and the samples of the low-pass filtered version of the PWM signal.
    [15]
    15. The method of claim 14, wherein the time of a level change between two successive samples is calculated based on the samples of the low-pass filtered version of the PWM signal when the two consecutive samples of the PWM signal have different levels.
    [16]
    The method of claim 14 or 15, wherein, when two consecutive samples of the PWM signal have the same level, a period of time during which the reconstructed PWM signal is centered is calculated based on the samples of the low-pass filtered version of the PWM signal in the sampling period between the consecutive samples has the other level.
    [17]
    17. The method of claim 14, wherein when the sample of the PWM signal at a sampling instant k-1 is at a low level and the sample of the PWM signal at an immediately following sample time k k has a high level , a switching time îmodei for the reconstructed signal is calculated as follows:

    and in which, when the sample of the PWM signal at the sampling time k-1 is high level and the sample value of the PWM signal at the immediately subsequent second sampling time k is low level, a switching time tMODE2 for the reconstructed signal is calculated as follows becomes:

    where Tp is the sampling period, PWMFiiter (k-1) is the sample of the low-pass filtered PWM signal at sampling time k-1, PWMFiiter (k) is the sample of low-pass filtered PWM signal at sampling time k, filter time is the time constant of the low-pass filter, and k Is the running index of sampling times.
    [18]
    18. The method of claim 17, wherein when the sample of the PWM signal has a low level at a sampling instant k-1 and the sample of the PWM signal has a low level at an immediately subsequent sampling instant k, a first switching instant tM0DE3- i and a second switching time tM0DE3-2 for the reconstructed signal are calculated as follows:

    and wherein when the sample value of the PWM signal at a sampling time k-1 is a high level and the sample value of the PWM signal at a immediately subsequent sampling time k is high, a first switching timing tMODE4-i and a second switching timing tM0DE4 -2 for the reconstructed signal are calculated as follows:


    [19]
    A method according to any one of claims 14 to 16, wherein when the sample of the PWM signal at a sampling time k-1 is at a low level and the sample value of the PWM signal is at a high level at an immediately subsequent sampling time k Switching time tMoDEi for the reconstructed signal is calculated as follows:

    and wherein when the sample of the PWM signal at the sampling time k-1 is high and the sample of the PWM signal at the immediately subsequent second sampling time k is at a low level, a switching time îMode2 for the reconstructed signal is calculated as follows becomes:

    where Tp is the sampling period, PWMFiiter (k-1) is the sample of the low-pass filtered PWM signal at sampling time k-1, PWMpjiter (k) is the sample of the low-pass filtered PWM signal at sampling time k, filter time is the time constant of the low-pass filter, and k Is the running index of sampling times.
    [20]
    20. The method of claim 19, wherein when the sample of the PWM signal at a sample time k-1 has a low level and the sample of the PWM signal at an immediately subsequent sample time k has a low level, a first switching time tM0DE3- i and a second switching time tM0DE3-2 for the reconstructed signal are calculated as follows:

    and wherein when the sample of the PWM signal at a sampling time k-1 is a high level and the sample value of the PWM signal at a immediately subsequent sampling time k is at a high level, a first switching timing tMoDE4-i and a second switching timing tM0DE4 -2 for the reconstructed signal are calculated as follows:


    [21]
    21. The method of claim 14, wherein the PWM signal is sampled at sampling instants whose sampling period is less than a PWM signal period of the PWM signal or less than half a PWM signal period of the PWM signal.
    [22]
    A computer program product having a program code, wherein the program code is operative to cause a device for generating a reconstructed signal according to a method according to any one of claims 14 to 21 when the computer program product runs on a computer.
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    同族专利:
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    DE19704296C2|1997-02-06|2001-03-01|Leica Microsystems|Method and device for stepper motor control|
    US7979223B2|2007-06-15|2011-07-12|University Of South Carolina|Systems and methods for power hardware in the loop testing|
    法律状态:
    2017-03-31| PUE| Assignment|Owner name: KEB AUTOMATION AG, DE Free format text: FORMER OWNER: KARL E. BRINKMANN GMBH, DE |
    优先权:
    申请号 | 申请日 | 专利标题
    DE102013213683.8A|DE102013213683B3|2013-07-12|2013-07-12|DEVICE AND METHOD FOR PRODUCING A RECONSTRUCTED SIGNAL AND TEST DEVICE|
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