• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a silicon carbide (SiC) semiconductor device having both a high reverse voltage and a low on-resistance. The semiconductor device has a reverse voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milliohm-square centimeters (mΩ · cm 2), and more preferably less than 5 mΩ · cm 2. According to one embodiment, the semiconductor device has a reverse voltage of at least 15 kV and an on-resistance of less than 15 mΩ · cm 2, and more preferably less than 7 mΩ · cm 2. According to another embodiment, the semiconductor device has a reverse voltage of at least 20 kV and an on-resistance of less than 20 mΩ • cm 2, and more preferably less than 10 mΩ • cm 2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a bipolar transistor (BJT), an insulated gate bipolar transistor (IGBT), or a PIN diode.
    公开号:CH707901B1
    申请号:CH01183/14
    申请日:2013-02-05
    公开日:2017-09-15
    发明作者:Cheng Lin；Kumar Agarwal Anant；John O'loughlin Michael；Augustus Burk Albert Jr；Williams Palmour John
    申请人:Cree Inc；
    IPC主号:
    专利说明:

    Description Government Assistance [0001] This invention was government funded under the contract number DAAD19-01-C-0067 Task Order 4 awarded by the US Army. The US government may have rights to this invention.
    Related Applications This application is a continuation-in-part of U.S. Patent Application No. 13/108 366, filed May 16, 2011, the disclosure of which is incorporated herein by reference in its entirety.
    Technical Field The present invention relates to silicon carbide (SiC) semiconductor devices.
    Background Silicon carbide (SiC) is a preferred material for power and high temperature semiconductor devices due to its high breakdown field strength, high thermal conductivity, and high bandgap. However, to take advantage of the high breakdown field strength in a high voltage device, efficient edge termination is needed. More specifically, field densities at the edge of the device result in breakdown at the edge of the device, which in turn reduces the blocking voltage of the device to a value well below the ideal blocking voltage (i.e., the blocking voltage of an ideally parallel plane device). Therefore, edge termination is an important issue in the design of SiC semiconductor devices, and particularly in power SiC semiconductor devices.
    One type of edge termination used in SiC semiconductor devices is a planar edge structure to improve the breakdown voltage (JTE). FIG. 1 shows an exemplary SiC semiconductor device, namely a thyristor 10, having a number of JTE slots 12, 14 and 16. The thyristor 10 has a substrate 18, an injection layer 20, a field stop layer 22, a drift layer 24, a base layer 26 and an anode layer 28. As shown, to form the JTE wells 12, 14, and 16, the base layer 26 is etched to the drift layer 24. The JTE wells 12, 14 and 16 are then formed by ion implantation in an exposed surface from the drift layer 24. An anode contact 30 is formed on the anode layer 28, a cathode contact 32 is formed on a bottom surface of the substrate 18 opposite to the injection layer 20, and gate contacts 34 and 36 are formed on respective gate regions 38 and 40 in the base layer 26. As a result of etching the base layer 26 to the drift layer 24 to form the JTE wells 12, 14, and 16, a corner 42 is formed. The corner 42 causes electric field condensations, which in turn reduces the reverse voltage of the thyristor 10 to a value less than the ideal reverse voltage.
    Therefore, there is a need for an edge termination for a SiC semiconductor device that results in a reverse voltage whose value approaches the ideal reverse voltage of an ideal parallel plane device.
    Summary The present invention relates to a silicon carbide (SiC) semiconductor device having both a high reverse voltage and a low on-resistance. The semiconductor device has a reverse voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milliohm square centimeters (mxcm2), and more preferably less than 5 mxcm2. According to one embodiment, the semiconductor device has a reverse voltage of at least 15 kV and an on-resistance of less than 15 mQ · cm 2, and more preferably less than 7 mQ · cm 2. According to another embodiment, the semiconductor device has a reverse voltage of at least 20 kV and an on-resistance of less than 20 mQ · cm 2, and more preferably less than 10 mQ · cm 2.
    The semiconductor device has a negative bevel edge termination or beveled or chamfered box termination having a plurality of steps approaching a smooth negative bevel edge termination with a desired slope. More specifically, according to one embodiment, the negative flattening edge termination has at least five stages. According to another embodiment, the negative flattening edge termination has at least ten stages. According to another embodiment, the negative flattening edge termination has at least fifteen stages. The desired slope is, according to one embodiment, less than or equal to 15 degrees. The negative flattening edge termination results in a reverse voltage of the semiconductor device of at least 10 kV and an on-resistance of less than 10 m · cm 2, and more preferably less than 5 m · cm 2. According to one embodiment, the negative flattening edge termination results in a reverse bias voltage of the semiconductor device of at least 15 kV and an on-resistance of less than 15 m · cm 2, and more preferably less than 7 m · cm 2. According to another embodiment, the negative flattening edge termination results in a reverse voltage of the semiconductor device of at least 20 kV and an on-resistance of less than 20 mΩ · cm 2, and more preferably less than 10 m 2 cm 2.
    The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a bipolar transistor (BJT), an insulated gate bipolar transistor (IGBT), or a PIN diode. Furthermore, according to one embodiment, the semiconductor device has an area greater than or equal to one square centimeter.
    One skilled in the art will appreciate the scope of the present disclosure and will recognize further aspects upon reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures.
    Brief Description of the Drawings The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
    Fig. 1 shows a silicon carbide (SiC) thyristor with a conventional planar edge structure for
    Improvement in breakdown voltage (JTE);
    Fig. 2 shows a SiC thyristor with a negative flattening edge termination according to a
    Embodiment of the present disclosure;
    Fig. 3 shows the negative flattening edge termination of Fig. 2 in more detail, the negative
    Flattening edge termination is implemented as a multi-level negative flattening edge termination having a number of stages formed on a surface of a respective semiconductor layer according to an embodiment of the present disclosure;
    FIG. 4 graphically depicts an electric field in the multi-level negative flattening edge termination of FIG. 3 as compared to that of a JTE termination according to an embodiment of the present disclosure;
    FIG. 5 graphically illustrates a blocking voltage from the multi-level negative flattening edge termination of FIG. 3 as compared to that of a JTE termination according to an embodiment of the present disclosure;
    FIG. 6 shows a thyristor having a multi-level negative flattening edge termination formed by counter-doping the base layer according to another embodiment of the present disclosure; FIG.
    Fig. 7 shows an embodiment in which a multi-level negative flattening edge termination is provided by forming a sacrificial layer on the base layer and then etching the sacrificial layer such that the desired multi-stage characteristic is transferred to the base layer to thereby provide the multi-level negative flattening edge termination;
    8 shows a SiC bipolar transistor (BJT) having a negative flattening edge termination, as illustrated in FIG. 3, according to an embodiment of the present disclosure;
    Fig. 9 shows a SiC BJT having a negative flattening edge termination formed by back-doping the base layer according to another embodiment of the present invention;
    FIG. 10 shows a P-type insulated gate SiC bipolar transistor (IGBT) having a negative flattening edge termination, as shown in FIG. 3, according to an embodiment of the present disclosure; FIG.
    Fig. 11 shows a P-type SiC IGBT having a negative flattening edge termination formed by
    Counter doping of the base layer, according to another embodiment of the present disclosure;
    FIG. 12 shows an n-type SiC IGBT having a negative flattening edge termination, as illustrated in FIG. 3, according to an embodiment of the present disclosure; FIG.
    Fig. 13 shows an n-type SiC IGBT having a negative flattening edge termination formed by
    Counter doping of the base layer, according to another embodiment of the present disclosure;
    FIG. 14 shows a SiC PIN diode having a negative flattening edge termination, as illustrated in FIG. 3, according to an embodiment of the present disclosure; FIG.
    Fig. 15 shows a SiC PIN diode with a negative flattening edge termination formed by
    Counter doping of one of the semiconductor layers, according to another embodiment of the present disclosure;
    16 shows a SiC U-channel metal-oxide-semiconductor field effect transistor (UMOSFET) having a negative flattening edge termination, as illustrated in FIG. 3, according to another embodiment of the present disclosure;
    Fig. 17 shows a SiC UMOSFET with a negative flattening edge termination formed by
    Counter doping of the base layer, according to another embodiment of the present disclosure;
    Fig. 18 graphically shows the charge carrier distribution within a conduction thyristor in the on state;
    Fig. 19 graphically shows the charge carrier distribution under high-level injection conditions for a PIN rectifier;
    Fig. 20 graphically illustrates the charge carrier distribution as a function of high level carrier lifetime under high level injection conditions for a PIN rectifier;
    FIGS. 21A-21D illustrate a method of fabricating the SiC thyristor of FIG. 2 having a number of carrier lifetime enhancement techniques resulting in a low on-resistance of the SiC thyristor according to an embodiment of the present disclosure;
    FIGS. 22A-22C graphically illustrate carrier lifetime measurements for a number of exemplary thyristors fabricated by the method of FIGS. 21A-21D; and
    Fig. 23 graphically shows transmission characteristics including an on-resistance of one
    Carrier lifetime improvement techniques manufactured thyristor according to an embodiment of the present disclosure.
    DETAILED DESCRIPTION The following embodiments provide the necessary information to those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in the light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will appreciate applications of those concepts that have not been particularly discussed herein. It should be understood that these concepts and applications are within the scope of the disclosure and the appended claims.
    It should be understood that although the terms first, second, etc. may be used to describe various elements, these elements are not limited to these terms. These expressions are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly a second element may be termed a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" means any and all combinations of one or more of the associated listed items.
    It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "extending" to another element, it may extend directly onto or directly onto another element or there may also be elements in between. In contrast, when an element is referred to as "directly on" or as extending "immediately upon" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" with another element, it may be directly connected or connected to an element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.
    Relative terms such as "bottom" or "top" or "top" and "bottom" or "horizontal" or "vertical" may be used herein to refer to an element, layer or region to another element, Layer or region to describe, as shown in the figures. It is understood that these terms and the various orientations of the device discussed above are intended to encompass additional orientations shown in the figures.
    The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include plurals, unless the context clearly indicates otherwise. It will also be understood that as used herein, the terms "comprising," "comprising," "containing," and / or "including" specify the presence of indicated features, integers, steps, operations, elements, and / or components. but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
    Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art upon which this disclosure resides. It is further understood that terms used herein have a meaning consistent with their meaning in the context of this specification and the relevant prior art and are not construed in an idealized or overly formal sense unless expressly so Here is defined.
    FIG. 2 shows a silicon carbide (SiC) thyristor 44 having a negative bevel edge termination 46 in accordance with an embodiment of the present disclosure. According to a particular embodiment, the thyristor 44 is a turn-off (GTO) thyristor. It should be noted in advance that while the description here focuses on SiC semiconductor devices, the concepts disclosed herein are equally applicable to semiconductor devices made using other types of semiconductor materials (e.g., silicon). As shown, the thyristor 44 includes a substrate 48, an injection layer 50 on a surface of the substrate 48, a field stop layer 52 on a surface of the injection layer 50 opposite to the substrate 48, a drift layer 54 on a surface of the field stop layer 52 opposite to the injection layer 50, and a Base layer 56 on a surface of the drift layer 54 opposite to the field stop layer 52 on. Gate regions 58 and 60 are formed in a surface of the base layer 56 opposite to the drift layer 54 and separated by a desired lateral distance. A mesa anode or region 62 is disposed on the surface of the base layer 56 between the gate regions 58 and 60. An anode contact 64 is on a surface of the anode 62 opposite the mesa base layer 56, a cathode contact 66 is on a surface of the substrate 48 opposite to the injection layer 50 and gate contacts 68 and 70 are on the surface of the base layer 56 over the gate regions 58 and 60 arranged. In particular, according to one exemplary embodiment, the thyristor 44 is produced on a semiconductor chip having an area greater than or equal to 1 cm 2.
    The substrate 48 is preferably a SiC substrate and the injection layer 50, the field stop layer 52, the drift layer 54, the base layer 56 and the mesa anode 62 are preferably all SiC layers deposited on the substrate 48 by epitaxy. The gate regions 58 and 60 are preferably formed by introducing ions into the base layer 56, e.g. Ion implantation, formed. According to this particular embodiment, the substrate 48 is a highly doped N type (N +), the injection layer 50 is a highly doped N type (N +), the field stop layer 52 is a highly doped P type (P +), and the drift layer 54 is a doped one P type (P), the base layer 56 is a doped N type (N), the gate regions 58 and 60 are heavily doped N types (N +) and the mesa anode 62 is a very highly doped P type (N +). Type (p + +). According to one embodiment, the substrate 48 has a doping level in a range of and including 1 × 10 18 to 1 × 10 19 cm -3 and a thickness in a range of and including approximately 100 to 350 micrometers (pm); the injection layer 50 has a doping level of more than or equal to 1 × 10 18 cm -3 and a thickness in a range of and including 1 to 5 μm, the field stop layer 52 has a doping level in a range of and including 1 × 10 16 to 5 × 10 17 cm -3 and a Thickness in a range of and including 1 to 5 pm, the drift layer 54 has a doping level smaller than 2 × 10 14 cm -3 and a thickness greater than or equal to 80 μm, the base layer 56 has a doping level in a range from and including 1 χ 1016 to 1 χ 1018 cm'3 and a thickness in the range of and including 0.5 to 5 pm, and the mesa anode 62 has a doping level greater than 1 χ 1019 cm'3 and a thickness in a range of and including 0.5 to 5 pm. According to a particular embodiment, the substrate 48 has a doping level in a range of and including 1 × 10 18 to 1 × 10 19 cm -3 and a thickness in a range of and including 100 to 350 μm, the injection layer 50 has a doping level of 5 × 1018 cm'3 and a thickness of 1 pm, the field stop layer 52 has a doping level of 1 × 10 16 cm -3 and a thickness of 4 μm, the drift layer 54 has a doping level of less than 2 × 10 14 cm -3 and a thickness of 90 pm, the base layer 56 has a doping level of 1 × 10 17 cm -3 and a thickness of 2.5 μm, and the mesa anode 62 has a doping level greater than 2 × 10 19 cm -3 and a thickness in one range from and including 0.5 to 5 pm, gate regions 58 and 60 are N + regions, according to one embodiment with a doping level greater than 1 × 10 18 cm -3. Finally, the contacts 64, 66, 68 and 70 are formed of a suitable contact material (e.g., metal, metal alloy, etc.).
    An edge of the thyristor 44 is terminated by the negative flattening edge termination 46. In one embodiment, a width of the negative bevel edge termination is 46,600 pm. According to a preferred embodiment, an inclination angle (a) of the negative bevel edge termination 46 is less than or equal to 15 degrees. As discussed in greater detail below, the negative flattening edge termination 46 is formed as a multi-stage negative flattening edge termination 46 that approximates a smooth slope. It is noteworthy that a negative flattening edge termination with a smooth slope in SiC is not feasible. For example, wet etching may be used to form a negative flattening edge termination with a smooth slope for silicon devices, but wet etching is not suitable for SiC and therefore can not be used to form a negative flattening edge termination with a smooth slope for SiC devices. Therefore, as discussed herein, the negative flattening edge termination 46 is formed as a multi-stage negative flattening edge termination that approximates a smooth slope.
    According to one embodiment, the multi-level negative flattening edge termination 46 has a series of steps that approximate a uniform flank with the desired tilt angle (a). According to one embodiment, the multi-level negative flattening edge termination has at least 10 stages that approximate a uniform flank with the desired tilt angle (a). According to another embodiment, the multi-stage negative flattening edge termination 46 has at least 15 stages that approach a uniform flank with the desired tilt angle (a). As a result of the negative bevel edge termination 46, a reverse voltage of the thyristor 44 approximates a reverse voltage of an ideal parallel plane device. According to this particular embodiment, the reverse voltage is greater than or equal to 12 kilovolts (kV). As used herein, the reverse voltage of the device is a voltage at which the device carries a 1 microampere (μΑ) current. In the case of the thyristor 44, the reverse voltage is a voltage which, when applied between the anode contact 64 and the cathode contact 66, causes a current flowing through the thyristor 441 μΩ when no voltage is applied to the gate contacts 68 and 70.
    FIG. 3 shows the negative flattening edge termination 46 of FIG. 2 in more detail according to one embodiment of the present disclosure. Specifically, as shown, the negative flattening edge termination 46 is a multi-level negative flattening edge termination 46. According to this particular embodiment, the multi-level negative flattening edge termination 4615 has steps that approximate the desired tilt angle (a). The multi-level negative flattening edge termination reduces field crowding, which increases the blocking voltage. As discussed below, in one embodiment, the reverse voltage is increased to at least 12 kV. The multi-level negative bevel edge termination 46 of this embodiment is formed by etching the base layer 56 using an appropriate number of masks. According to one embodiment, the number of masks is equal to the number of stages (e.g., 15 masks to form 15 stages). According to another embodiment, the number of masks may be optimized to reduce the number of etching steps so that the total number of masks is less than the number of stages of the multi-level negative bevel edge termination 46 (e.g., 4 to 15 masks for 15 levels).
    FIG. 4 graphically compares the distribution of the electric field along the multi-level negative bevel edge termination 46 of FIG. 3 with that of a 12 kV breakdown planar voltage (JTE) edge structure according to one embodiment of the present disclosure. As shown, the multi-level negative bevel edge termination 46 effectively reduces the peak electrical field at the mesa trench corner (eg, the corner 42 of the thyristor 10 of FIG. 1) to less than 1.4 Mega-Volts per centimeter (MV / cm). In other words, the peak electric field at the connection edge is reduced by more than 0.2 MV / cm.
    FIG. 5 graphically compares the reverse bias voltage of the thyristor 44 with the multi-level negative bevel edge termination 46 of FIG. 3 with that of a thyristor (eg, the thyristor 10 of FIG. 1) with a 15-well JTE edge termination according to one embodiment of the present disclosure. As shown, as a result, the multi-level negative flute edge termination 46 of the thyristor 44 has a reverse voltage in a range of 11.5 to 12 kV. This is a 3.5 to 4 kV improvement over the 9 kV reverse bias of the 15-bay JTE edge termination.
    FIG. 6 shows the thyristor 44 with the negative bevel edge termination 46 according to another embodiment of the present disclosure. According to this embodiment, instead of etching the base layer 56 to form the multi-level negative bevel edge termination 46, as discussed above with reference to FIG. 3, the negative flattening edge termination 46 is counter-doped by the P-type ionic base layer 56 in an edge region 72 are formed to the gate region 60 opposite to the mesa anode 62, which balance the n-type conductivity of the base layer 56 in the edge region 72 to provide a neutral or intrinsic region 76 with a desired negative bevel edge termination characteristic. The P-type ions may be, for example, aluminum (Al), boron (B) or the like. The negative flattening edge termination 46 is thereby formed at an interface of the neutral region 76 and a remainder of the base layer 56. In particular, according to one embodiment, ions are implanted at different depths, which gradually increase from the end of the edge region 72 adjacent to the gate region 60 and continue outward to the desired number of steps and slope (et) for the negative flattening edge termination 46 to provide.
    Fig. 7 shows another method by which the negative flattening edge termination 46 can be formed. According to this embodiment, a sacrificial layer 78 is formed on the surface of the base layer 56 over an area where the negative flattening edge termination 46 is to be formed. The sacrificial layer 78 may be, for example, SiO 2, photoresist, or a similar material. The sacrificial layer 78 is etched or otherwise patterned to provide a negative chamfer 80 having a desired multi-level characteristic (i.e., the number of steps, pitch, width, etc.) for the negative bevel edge termination 46. An etching process is then performed to remove the sacrificial layer 78. In particular, an etching process is performed to etch to a desired depth (d), which in this example is equal to the thickness of the sacrificial layer 78 and also equal to the thickness of the base layer 56. However, the present invention is not limited thereto. As a result of the etching, the negative land 80 is effectively transferred on the base layer 56 to thereby provide the multi-level negative bevel edge termination 46.
    FIGS. 8-17 illustrate further non-limiting examples of other types of SiC devices that may utilize the negative flattening edge termination described above with respect to the thyristor 44. In particular, FIG. 8 shows a SiC bipolar transistor (BJT) 82 having a negative flattening edge termination 84 in accordance with an embodiment of the present disclosure. The BJT 82 includes an N + substrate 86, an n-type drift layer 88 on a surface of the substrate 86, a P-type base layer 90 on a surface of the drift layer 88 opposite to the substrate 86, a P + base region 92, formed in the base layer 90, an N + + mesa emitter 94 on the surface of the base layer 90 opposite the drift layer 88, a base contact 96 on the base region 92, an emitter contact 98 over the mesa emitter 94, and a collector contact 100 on a surface of the substrate 86 opposite to the drift layer 88. In accordance with this embodiment, the negative flattening edge termination 84 is a multi-level negative flattening edge termination like that of FIG. 3. As a result of the negative flattening edge termination 84, a reverse bias voltage of the BJT 82 approaches the reverse voltage of the ideal parallel plane device.
    FIG. 9 shows the BJT 82 including the negative bevel edge termination 84 according to another embodiment of the present disclosure. According to this embodiment, the negative flattening edge termination 84 is formed by counter-doping with N-type ions of the P-type base layer 90 in an edge region 102 adjacent to the P + base region 92 opposite to the mesa emitter 94, which is the P-type conductivity of the base layer 90 in edge region 102 to provide a neutral or intrinsic region 106 having a desired negative bevel edge termination characteristic. The N-type ions may be, for example, nitrogen (N), phosphorus (P) or the like. The negative flattening edge termination 84 is thereby formed at an interface of the neutral region 106 and a remainder of the base layer 90. In particular, according to one embodiment, ions are implanted at different depths that gradually increase from the end of the edge region 102 adjacent to the P + base region 92 and continue outward to the desired number of steps and slope (η) for to provide the negative flattening edge termination 84.
    FIG. 10 shows a P-type SiC insulated gate bipolar transistor (1GBT) 108 having a negative bevel edge termination 110 according to an embodiment of the present disclosure. As shown, the IGBT 108 includes a P + substrate or epitaxial layer 112, an N-type drift layer 114 on a surface of the substrate 112, a base layer 116 on a surface of the drift layer 114 opposite to the substrate 112, P + Regions 118 and 120 on the surface of the base layer 116 opposite the drift layer 114 and the emitter regions 122 and 124. A gate contact 126 is formed in a trench, as shown, and is isolated by a gate insulator 128. Emitter contacts 130 and 132 are disposed on the emitter regions 122 and 124, respectively, and a collector contact 134 is disposed on a surface of the substrate 112 opposite to the drift layer 114. In this embodiment, the negative flattening edge termination 110 is a multi-level negative flattening edge termination like that of FIG. 3. As a result of the negative flattening edge termination HO, a reverse bias voltage of the 1GBT 108 approximates the blocking voltage of the ideal parallel plane device.
    FIG. 11 shows the IGBT 108 with the negative bevel edge termination 110 according to another embodiment of the present disclosure. According to this embodiment, the negative flattening edge termination 110 is formed by counter-doping with N-type ions of the P-base layer 116 in an edge region 136 adjacent to the P + region 118 and the N + emitter region 122 opposite the gate contact 126 compensate the P-conductivity of the base layer 116 in the edge region 136 to provide a neutral or intrinsic region 140 having a desired flattening edge termination characteristic. The N-type ions may be, for example, nitrogen (N), phosphorus (P) or the like. The negative flattening edge termination 110 is thereby formed at an interface of the neutral region 140 and a remainder of the base layer 116. In particular, according to one embodiment, ions are implanted at different depths that gradually increase from the end of the edge region 136 adjacent to the P + base region 118 and continue outward to the desired number of steps and pitch (a) to provide the negative flattening edge termination 110.
    FIG. 12 shows an n-type SiC IGBT 142 having a negative bevel edge termination 144 according to an embodiment of the present disclosure. As shown, the IGBT 142 has a substrate 146, a drift layer 148 on a surface of the substrate 146, a base layer 150 on a surface of the drift layer 148 opposite the substrate 146, N + regions 152 and 154 on the surface of the base layer 150 opposite to the substrate Drift layer 148 and the emitter regions 156 and 158 on. A gate contact 160 is formed in a trench, as shown, and is isolated by a gate insulator 162. Emitter contacts 164 and 166 are disposed on the emitter regions 156 and 158, and a collector contact 168 is disposed on a surface of the substrate 146 opposite to the drift layer 148. In this embodiment, the negative flattening edge termination 144 is a multi-level negative flattening edge termination like that of FIG. 3. As a result of the negative flattening edge termination 144, a reverse voltage of the IGBT 142 approximates the reverse voltage of the ideal parallel plane device.
    FIG. 13 shows the IG BT 142 having the negative bevel edge termination 144 according to another embodiment of the present disclosure. According to this embodiment, the negative flattening edge termination 144 is formed by counter-doping with P-type ions of the n-base layer 150 in an edge region 170 adjacent to the N + region 152 and the P + emitter region 156 opposite the gate contact 160, which balance the N-conductivity of the base layer 150 in the edge region 170 to provide a neutral or intrinsic region 174 having a desired flattening edge termination characteristic. The P-type ions may be, for example, aluminum (Al), boron (B) or the like. The negative flattening edge termination 144 is thereby formed at an interface of the neutral region 174 and a remainder of the base layer 150. In particular, according to one embodiment, ions are implanted at different depths which gradually increase from the end of the edge region 170 adjacent to the N + region 152 and the P + emitter region 156 and continue outward to the desired number of Steps and pitch (a) must be provided for the negative bevel edge termination 144.
    FIG. 14 shows a SiC PIN diode 176 having a negative flattening edge termination 178 according to an embodiment of the present disclosure. As shown, the PIN diode 176 includes an N + substrate 180, an n-drift layer 182, a P-type layer 184, and a P + + layer 186. The N-drift layer 182 may also be referred to as an intrinsic layer between the N + substrate 180 and the P-type layer 184 forming the PIN diode 176. The P + + layer 186 may also be referred to as a mesa anode. An anode contact 188 is disposed on the surface of the P + + layer 186 opposite to the P-type layer 184. A cathode contact 190 is disposed on a surface of the N + substrate 180 opposite to the N-drift layer 182. In this embodiment, the negative flattening edge termination 178 is a multi-level flattening edge termination similar to that of Fig. 3. As a result of the negative flattening edge termination 178, a reverse voltage, in particular a breakdown voltage of the PIN diode 176, approximates the reverse voltage of an ideal parallel plane device.
    Fig. 15 shows the PIN diode 176 with the negative flattening edge termination 178 according to another embodiment of the present disclosure. In accordance with this embodiment, the negative flattening edge termination 178 is formed by counterposing the N-type ionic P-type layer 184 in an edge region 192 adjacent to the P + + layer 186 that has the P-type conductivity of the P-type layer 184 in the edge region 192 to provide a neutral or intrinsic region 196 having a desired negative bevel edge termination characteristic. The N-type ions may be, for example, nitrogen (N), phosphorus (P) or the like. The negative flattening edge termination 178 is thereby formed at an interface of the neutral region 196 and a remainder of the P-type layer 184. In particular, according to one embodiment, ions are implanted at different depths, which gradually increase from the end of the edge region 192 adjacent to the P + + layer and continue outward to the desired number of steps and slope (a) for the negative Provide flat edge termination 178.
    FIG. 16 shows a SiC U-channel metal oxide semiconductor field effect transistor (UMOSFET) 198 having a negative flattening edge termination 200 according to an embodiment of the present disclosure. As shown, the UMOSFET 198 includes an N + substrate 202, an N-type drift layer 204 on a surface of the substrate 202, a P-base layer 206 on a surface of the drift layer 204 opposite to the substrate 202, P + regions 208 and 210 on the surface of the base layer 206 opposite the drift layer 204 and N + source regions 212 and 214. A gate contact 216 is formed in a trench, as shown, and is isolated by a gate insulator 218. Source contacts 220 and 222 are disposed on the source regions 212 and 214, respectively, and a drain contact 224 is disposed on a surface of the substrate 202 opposite to the drift layer 204. In this embodiment, the flattening edge termination 200 is a multi-level negative flattening edge termination like that of FIG. 3. As a result of the negative flattening edge termination 200, a reverse voltage of the UMOSFET 198 approximates the reverse voltage of the ideal parallel plane device.
    FIG. 17 shows the UMOSFET 198 having the negative bevel edge termination 200 according to another embodiment of the present disclosure. According to this embodiment, the negative flattening edge termination 200 is formed by counter-doping with N-type ions of the P-base layer 206 in an edge region 226 adjacent to the P + region 208 and the N + source region 212 opposite the gate contact 216, balancing the P-conductivity of the base layer 206 in the edge region 226 to provide a neutral or intrinsic region 230 having a desired flattening edge termination characteristic. The N-type ions may be, for example, nitrogen (N), phosphorus (P) or the like. The negative flattening edge termination 200 is thereby formed at an interface of the neutral region 230 and a remainder of the base layer 206. In particular, according to one embodiment, ions are implanted at different depths which gradually increase from the end of the edge region 226 adjacent to the P + region 208 and the N + source region 212 and continue outward to the desired number of Provide steps and pitch (a) for the negative bevel edge termination 200.
    Finally, it should be noted that the number of stages of the multi-level negative bevel edge termination 46, 84, 110, 144, 178 and 200 of the various devices described herein may vary depending on the particular implementation. Some exemplary embodiments of the multi-level negative bevel edge termination 46, 84, 110, 144, 178, and 200 have at least 5 stages, at least 7 stages, at least 10 stages, at least 12 stages, at least 15 stages, at least 17 stages, at least 20 stages, a number of Steps in a range of and including 5 to 20 stages, a number of stages in a range of and including 10 to 20 stages, a number of stages in a range of and including 15 to 20 stages, and a series of stages in a range from and including 10 to 15 steps up. Also, the blocking voltages of the various devices may vary depending on the particular implementation. Some exemplary embodiments have a blocking voltage of at least 10 kV, a blocking voltage of at least 12 kV, a blocking voltage of at least 15 kV, a blocking voltage of at least 17 kV, a blocking voltage of at least 20 kV, a blocking voltage of at least 22 kV, a blocking voltage of at least 25 kV blocking voltage in a range of and including 10 kV to 25 kV, a blocking voltage in a range of and including 12 kV to 25 kV, a blocking voltage in a range of and including 15 kV to 25 kV, a blocking voltage in the range of and including 12 kV to 20 kV, and reverse voltage ranging from and including 12 kV to 15 kV.
    Referring again to Figure 2, the on-state characteristic of the high voltage (eg,> 10 kV) thyristor 44, and hence on-resistance of the thyristor 44, is a function of carrier lifetime in the drift layer 54. However, due to the high reverse voltage of the thyristor 44, the drift layer 54 is relatively thick (eg as thick as 160 microns or more for a reverse voltage of up to 20 kV) and high impedance. The charge carrier lifetime in drift layer 54 is typically relatively short, resulting in a different than an optimal on resistance of thyristor 44. The following description describes a number of carrier lifetime improvement techniques that can be used to provide low on-resistance with high reverse voltage ,
    Before describing the carrier lifetime improvement techniques, a brief analysis of the transmission characteristic of the thyristor 44 may be advantageous. As an example, to analyze the transmission characteristic, the thyristor 44 may be considered a PIN rectifier. As shown in FIG. 18, the electron and hole concentrations within the N-base and the P-base regions of the conventional thyristor (PNPN) are a chain distribution according to the analysis for the P-i-N rectifier shown in FIG. Because both electrons and holes are available for current transport under high-level injection conditions for current transport, the total forward current flow JT and resistivity of the drift region RdiSp can be calculated from the average carrier density na in the drift regions by equations (1) and (2). be calculated:
    (1) (2) where xhl is the high level carrier lifetime and d is half the thickness of the drift layer 54, conversion of equation (1) and then substituting into equation (2) gives the resistivity of drift layer 54 in equation (3) at:
    (3) A voltage drop V ™ across the drift layer 54 is then given by the equation (4):
    (4) It is clearly shown in equations (3) and (4) that both the resistivity and the voltage drop in the drift layer 54 are increased as the carrier lifetime is reduced, as shown in FIG a longer lifetime gives a higher carrier density in the drift region. Thus, the high injection level conductivity modulation phenomenon allows the maintenance of a small voltage drop across the drift layer 54, which is advantageous for obtaining a low forward voltage drop in bipolar diodes and transistors.
    FIGS. 21A-21D illustrate a method of fabricating the thyristor 44 of FIG. 2 using a number of carrier-life enhancement techniques leading to the thyristor 44 having a low on-resistance in accordance with one embodiment of the present disclosure. As shown in FIG. 21A, the process begins with an epitaxial structure with the substrate 48, the injection layer 50, the field stop layer 52, the drift layer 54, the base layer 56, and a layer 62 'to be etched to form the mesa anode 62 , Next, as shown in FIG. 21B, the layer 62 'is etched to form the mesa anode 62. After etching the layer 62 'to form the mesa anode 62, an oxidation process and a subsequent oxide removal process are performed. The oxidation process is preferably a dry oxidation process in which the structure of Figure 21B is heated to a temperature in the range of and including 1200 ° C to 1450 ° C for a period of 1 hour to 15 hours. According to a particular embodiment, the dry oxidation process is sensed by heating the structure of Fig. 21B to a temperature of 1300 ° C for 5 hours. The oxide on the surface of the structure resulting from the dry oxidation process is then removed. This dry oxidation process increases the carrier lifetime, and in particular the lifetime of the minority carriers of the drift layer 54.
    Next, the negative flattening edge termination 46 is etched or otherwise formed, and the dopants (eg, N + dopant) are implanted in the base layer 56 to surround the gate regions 58 and 60 as shown in FIG. 21C form. The implanted dopants are activated by an annealing process. The tempering process can be carried out for example at a temperature of 1650 ° C for 30 minutes. Note, however, that the annealing temperature and duration can be changed. In particular, the tempering process may be at a temperature in the range of and including 1500 ° C to 2000 ° C and the duration of 1 minute to 60 minutes. Preferably, however, the annealing process is carried out at a temperature in the range of and including 1600 ° C to 1800 ° C with a duration of 10 to 30 minutes. A sacrificial oxidation process followed by an oxide removal process is then performed to remove damage to the surface of the structure of FIG. 21C from the implantation surface. More specifically, in a particular embodiment, the structure of Fig. 21C is heated to a temperature of 1200 ° C for 2 hours, rinsed, heated to a temperature of 950 ° C for 2 hours, and then rinsed again. It should be noted that the temperature and duration of heating may vary for these oxidation processes. In particular, the sacrificial oxidation is carried out at a temperature of 1150 ° C to 1450 ° C with a duration of 1 hour to 15 hours. Preferably, however, the sacrificial oxidation process is carried out at a temperature in the range of and including 1200 ° C to 1300 ° C with a duration of 1 hour to 5 hours. As a result of the annealing process, followed by the sacrificial oxidation process, the carrier lifetime in the drift layer 54 is further improved. Finally, the anode, the cathode and the gate contacts 64, 66, 68 and 70 are formed as shown in Fig. 21D.
    By means of the carrier lifetime enhancement techniques in the method of Figs. 21A to 21D, the thyristor 44 has both a high reverse voltage and a low on-resistance. According to one embodiment, the thyristor 44 has a reverse voltage of at least 10 kV and a differential on-resistance of less than 10 mQ · cm 2, preferably less than 7 mQ · cm 2, and more preferably less than 5 m · cm 2. According to one embodiment, the thyristor 44 has a blocking voltage in a range of and including 10 kV to 15 kV and a differential on-resistance of less than 10 mQ · cm 2, preferably less than 7 m 2 cm 2 and more preferably less than 5 m 2 cm 2 on. According to another embodiment, the thyristor 44 has a blocking voltage of at least 10 kV or in the range of 10 kV to 15 kV and a differential on-resistance in the range of 1 to 10 ηιΩ · αη2, in the range of 3 to 10 mQ cm2, in the range of 1 to 7 mQ »cm 2, in the range of 3 to 7 m 2, in the range of 1 to 5 m 2 or in the range of 3 to 5 m 2 cm 2. According to another embodiment, the thyristor 44 has a reverse voltage of at least 15 kV and a differential on-resistance of less than 15 mO · cm 2, preferably less than mQ · cm 2, and more preferably less than 7 m · cm 2. According to another embodiment, the thyristor 44 has a blocking voltage in a range of and including 15 kV to 20 kV and a differential on resistance of less than 15 mQ • cm2, preferably less than ιτιΩ · cm2, and more preferably less than 7 mü · cm2 on. According to another embodiment, the thyristor 44 has a blocking voltage of at least 15 kV or in the range of 15 kV to 20 kV and a differential on resistance in the range of 1 to 15 ιτιΩ · cm2, in the range of 3 to 15 ιτιΩ · cm2, in the range of 1 to 10 ηιΩ · cm2, in the range of 3 to 10 ηιΩ · cm2, in the range of 1 to 7 ηιΩ · cm2 or in the range of 3 to 7 ηιΩ · cm2. According to another embodiment, the thyristor 44 has a reverse voltage of at least 20 kV and a differential on-resistance of less than 20 ηιΩ · cm2, preferably less than 15 ηιΩ · cm2 and more preferably less than 10 ηιΩ · cm2. According to another embodiment, the thyristor 44 has a blocking voltage in a range of and including 20 kV to 25 kV and a differential on resistance of less than 20 ηιΩ · cm2, preferably less than 15 ηιΩ · cm2 and more preferably less than 10 m ηιΩ · Cm2 on. According to another embodiment, the thyristor 44 has a reverse voltage of at least 20 kV or in the range of 20 kV to 25 kV and a differential forward resistance in the range of 1 to 20 ηιΩ · cm2, in the range of 3 to 20 ηιΩ · cm2, in the range of 7 to 20 ηιΩ · cm2, in the range of 1 to 15 ηιΩ · cm2, in the range of 3 to 15 mfi · cm2, in the range of 7 to 20 ηιΩ · cm2, in the range of 1 to 10 ηιΩ · cm2, in the range of 3 to 10 ηιΩ · cm2 or in the range of 7 to 10 ηιΩ · cm2.
    By means of the carrier lifetime enhancement techniques, the drift layer 54 of the thyristor 44 can be thicker, thus providing a higher reverse voltage while maintaining proper on-resistance. For example, the drift layer 54 may have a thickness of more than 80 pm, a thickness of more than 100 pm, a thickness of more than 120 pm, a thickness of more than 140 pm, a thickness of more than 160 pm, a thickness in the range from and including 80 pm to 200 pm, a thickness in the range of and including 80 pm to 160 pm, a thickness in the range of and including 100 pm to 200 pm, a thickness in the range of and including 100 pm to 160 pm, a thickness in the range of and including 140 pm to 200 pm, or a thickness in the range of and including 140 pm to 160 pm, or have a thickness in the range of 160 pm to 200 pm inclusive. However, other thicknesses may be used, depending on the desired blocking voltage and the particular design.
    FIGS. 22A-22C illustrate results of carrier lifetime measurements for a number of exemplary thyristors 44 made by the method of FIGS. 21A-21D. In particular, FIG. 22A shows average carrier life measurement, median carrier lifetime measurement, minimum carrier lifetime measurement, maximum carrier lifetime and deviation from carrier lifetime measures for a variety of structures, such as that of FIG. 21A. In this example, drift layer 54 is a 90 pm thick p-type SiC material layer and has a doping level less than 2 x 10 14 cm -3. FIG. 22B shows similar carrier lifetime measurements
    权利要求:
    Claims (17)
    [1]
    after etching the mesa anode 62 and performing a dry oxidation at a temperature of 1300 ° C for 5 hours. As shown, after carrying out the dry oxidation process, the carrier lifetime is significantly increased. Finally, FIG. 22C shows the carrier life measurements after etching the negative bevel edge termination 46, implanting the gate regions 58 and 60, and performing the sacrificial oxidation process. In this particular example, the sacrificial oxidation process includes the steps of heating to a temperature of 1200 ° C for 2 hours, rinsing, heating to a temperature of 950 ° C for 2 hours and then rinsing again. As illustrated, implant annealing followed by the sacrificial oxidation process further increases carrier lifetime in drift layer 54. FIG. 23 graphically illustrates the on-resistance of an example of thyristor 44 having a reverse bias voltage of at least 10 kV coupled with the above-described carrier lifetime. Improvement techniques was produced. As shown, in this example the differential on-state resistance is less than 5 mu cm2 at a current density of 100 A / cm2 (e.g., high level injection state) due to improved carrier lifetime. In particular, at housing temperatures of less than 100 ° C, the differential on-resistance is about 4 mQ · cm2. While the carrier lifetime enhancement techniques have been previously described with respect to the thyristor 44, the carrier lifetime enhancement techniques may be used for any semiconductor device, particularly any type of SiC semiconductor device, that is bipolar (ie, use of both electrons and holes to the line). For example, in addition to the thyristor 44 of FIGS. 2 and 6, the carrier lifetime enhancement techniques in the manufacture of the BJT 82 of FIGS. 8 and 9, the IGBTs 108 and 142 of FIGS. 10, 11, 12, and 13 and the PIN diode 176 of FIGS. 14 and 15 may be used to achieve similar on-resistance enhancements. In particular, in the fabrication of the BJT 82, the above-described oxidation process may be performed after etching the mesa anode 62 of the thyristor 44 after etching the mesa emitter. Likewise, the implant anneal and sacrificial oxidation process may be performed after etching or otherwise forming the negative bevel edge termination 84 and implanting the base zone 92. In this way, the carrier lifetime in the drift layer 88 is improved, which in turn reduces the on-resistance of the BJT 82. Similarly, in the fabrication of the IG BT 108, the oxidation process as described above may be performed after etching the mesa anode 62 of the thyristor 44 after etching the gate trench. Similarly, the implant annealing and sacrificial oxidation process may be performed after etching or otherwise forming the negative bevel edge termination 110 and implanting the P + regions 118 and 120 and the emitter regions 122 and 124. In this way, the carrier lifetime in the drift layer 114 is improved, which in turn reduces the on-resistance of the BJT 82. Similarly, the carrier lifetime techniques for the 1GBT 142 of FIGS. 12 and 13 may be used. Finally, in the fabrication of the PIN diode 176 of FIGS. 14 and 15, the above-described oxidation process may be performed after etching the mesa anode 62 of the thyristor 44 after etching the p-layer 184 and P + + layer 186 be performed. Likewise, the implant anneal and sacrificial oxidation process may be performed after implantation of the P-type layer 184 to form the negative bevel edge termination 178 in the embodiment of FIG. 15. In this way, the carrier lifetime in the N-drift layer 182 is improved, which in turn reduces the on-resistance of the PIN diode 176. Those skilled in the art will recognize improvements and modifications of the preferred embodiments of the present disclosure. All such improvements and modifications are within the scope of the concepts disclosed herein and the following claims. claims
    A silicon carbide, SiC semiconductor device for short, which approximates the ideal reverse bias voltage of an ideal parallel plane device by providing the semiconductor device with a multi-level negative bevel termination close to a smooth slope and a reverse bias of at least 10 kilovolts and an on-resistance of less than 10 Milliohm square centimeter.
    [2]
    2. The SiC semiconductor device according to claim 1, wherein the on-resistance is a differential on-resistance.
    [3]
    3. The SiC semiconductor device according to claim 2, wherein the differential on-state resistance is smaller than 5 mQ · cm 2.
    [4]
    4. The SiC semiconductor device according to claim 2, wherein the reverse voltage is in a range of and including 10 kV to 15 kV, and the differential on-resistance is smaller than 5 m mQ · cm 2.
    [5]
    The SiC semiconductor device according to claim 1 or 2, wherein the multi-level flattening edge termination has at least five stages, and more preferably at least 15 stages.
    [6]
    6. The SiC semiconductor device according to claim 1, wherein the reverse voltage of the SiC semiconductor device is in a range of and including 10 kV to 25 kV.
    [7]
    The SiC semiconductor device according to claim 1 or 2, wherein an inclination angle of the multi-level negative bevel edge termination is less than or equal to 15 degrees.
    [8]
    8. The SiC semiconductor device according to claim 1, wherein the SiC semiconductor device is a thyristor comprising: a substrate of a first conductivity type; a drift layer of a second conductivity type on a surface of the substrate; a base layer of the first conductivity type on a surface of the drift layer opposite to the substrate; a mesa anode of the second conductivity type on a surface of the base layer opposite to the drift layer; and a gate region formed in the surface of the base layer; wherein the multi-level negative flute edge termination in the base layer is formed adjacent to the gate region opposite the mesa anode.
    [9]
    9. The SiC semiconductor device according to claim 1, wherein the SiC semiconductor device is a bipolar transistor comprising: a substrate of a first conductivity type; a drift layer of the first conductivity type on a surface of the substrate; a base layer of a second conductivity type formed on a surface of the drift layer opposite to the substrate; a base region of the second conductivity type formed in a surface of the base layer opposite to the drift layer; and a mesa emitter on the surface of the base layer opposite the drift layer and adjacent to the base region; wherein the multi-level flattening edge termination in the base layer is formed adjacent to the base region opposite to the mesa emitter.
    [10]
    10. The SiC semiconductor device according to claim 1, wherein the SiC semiconductor device is a bipolar transistor comprising: a substrate of a first conductivity type; a drift layer of a second conductivity type on a surface of the substrate; a base layer of the first conductivity type on a surface of the drift layer opposite to the substrate; an emitter region of the second conductivity type on a surface of the base layer opposite to the drift layer; and a gate trench formed in a surface of the BJT adjacent to the emitter region and extending into the drift layer; wherein the multi-level flattening edge termination in the base layer is adjacent to the emitter region opposite to the gate trench.
    [11]
    11. The SiC semiconductor device according to claim 1, wherein the SiC semiconductor device is a PIN diode comprising: a substrate of a first conductivity type; a drift layer of the first conductivity type on a surface of the substrate; a semiconductor layer of a second conductivity type on a surface of the drift layer opposite to the substrate; a mesa anode on a surface of the semiconductor layer of the second conductivity type opposite to the drift layer; an anode contact on a surface of the mesa anode opposite the drift layer; and a cathode contact on a surface of the substrate opposite the drift layer; wherein the multi-stage flattening edge termination is formed in the second conductivity type semiconductor layer adjacent to the mesa anode.
    [12]
    The SiC semiconductor device of claim 1, having a reverse bias of at least 15 kilovolts and an on-resistance of less than 15 milliohm square centimeters.
    [13]
    13. The SiC semiconductor device according to claim 12, wherein the on-resistance is a differential on-resistance.
    [14]
    14. The SiC semiconductor device according to claim 13, wherein the differential on-state resistance is less than 7 m · cm 2 and the reverse voltage is in a range of and including 15 kV to 20 kV.
    [15]
    15. The SiC semiconductor device of claim 1, having a reverse bias of at least 20 kilovolts and an on-resistance of less than 10 milliohm square centimeters.
    [16]
    16. The SiC semiconductor device according to claim 15, wherein the on-resistance is a differential on-resistance.
    [17]
    17. The SiC semiconductor device according to claim 16, wherein the differential on-state resistance is less than 10 mQ · cm 2 and the reverse voltage is in a range of and including 20 kV to 25 kV.
    类似技术:
    公开号 | 公开日 | 专利标题
    DE112013004362B4|2018-06-21|SEMICONDUCTOR DEVICE
    DE102010042998B4|2014-07-03|The silicon carbide semiconductor device
    DE102009038731B4|2021-04-22|Semiconductor component with charge carrier compensation structure and method for manufacturing a semiconductor component
    DE112016003510T5|2018-05-17|SEMICONDUCTOR PROTECTION AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
    DE102017108738B4|2022-01-27|SiC SEMICONDUCTOR DEVICE WITH AN OFFSET IN A TRENCH BOTTOM AND MANUFACTURING METHOD THEREOF
    DE112013006438T5|2015-10-08|The silicon carbide semiconductor device
    DE102015100340A1|2015-08-20|BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
    DE112010005626T5|2013-03-21|Semiconductor device
    DE102013106795B4|2016-11-10|Semiconductor device with a peripheral region and method of manufacturing a semiconductor device
    DE102015101124A1|2015-07-30|Semiconductor device with undulated profile of the net doping of a drift zone
    DE102013106946B4|2022-03-17|Method of forming laterally varying doping concentrations and a semiconductor device
    DE102008032547A1|2009-04-16|Trench isolated gate MOS semiconductor device
    DE102016226237A1|2017-08-03|SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SILICON CARBIDE SEMICONDUCTOR DEVICE
    EP0760528A2|1997-03-05|Semiconductor device on silicium base with a high blocking voltage edge termination
    DE102016118543A1|2017-04-20|SEMICONDUCTOR COMPONENTS, POWER SEMICONDUCTOR COMPONENTS AND METHOD FOR MAKING SEMICONDUCTOR CONSTRUCTION ELEMENTS
    DE102016102861B3|2017-05-24|Semiconductor devices and methods of forming a semiconductor device
    DE102016122787A1|2017-06-14|A method of forming a semiconductor device
    DE102012108302A1|2013-03-07|Semiconductor device and method of manufacturing the semiconductor device
    DE112013000866B4|2019-09-19|Silicon carbide | semiconductor devices
    DE10047152A1|2002-04-25|High-voltage diode and process for its manufacture
    DE112016004981T5|2018-07-19|SILICON CARBIDE SEMICONDUCTOR DEVICE
    DE102014116631B4|2020-12-10|JUNCTION FIELD EFFECT TRANSISTOR CELL WITH LATERAL CHANNEL AREA
    DE102018203693A1|2018-10-04|Semiconductor device
    DE102014116622A1|2015-05-21|A semiconductor device and a method of forming a semiconductor device
    DE102015118616B3|2017-04-13|Latchup-solid transistor
    同族专利:
    公开号 | 公开日
    DE112013000866T5|2014-10-23|
    JP6335795B2|2018-05-30|
    JP2015510272A|2015-04-02|
    WO2013119548A1|2013-08-15|
    DE112013000866B4|2019-09-19|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US5967795A|1995-08-30|1999-10-19|Asea Brown Boveri Ab|SiC semiconductor device comprising a pn junction with a voltage absorbing edge|
    JP4011848B2|2000-12-12|2007-11-21|関西電力株式会社|High voltage semiconductor device|
    SE525574C2|2002-08-30|2005-03-15|Okmetic Oyj|Low-doped silicon carbide substrate and its use in high-voltage components|
    US6974720B2|2003-10-16|2005-12-13|Cree, Inc.|Methods of forming power semiconductor devices using boule-grown silicon carbide drift layers and power semiconductor devices formed thereby|
    JP4585772B2|2004-02-06|2010-11-24|関西電力株式会社|High breakdown voltage wide gap semiconductor device and power device|
    US7345310B2|2005-12-22|2008-03-18|Cree, Inc.|Silicon carbide bipolar junction transistors having a silicon carbide passivation layer on the base region thereof|
    US7372087B2|2006-06-01|2008-05-13|Northrop Grumman Corporation|Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage|
    JP5140347B2|2007-08-29|2013-02-06|株式会社日立製作所|Bipolar transistor and manufacturing method thereof|
    JP5358926B2|2007-11-01|2013-12-04|富士電機株式会社|Silicon carbide trench MOS type semiconductor device|
    US8097919B2|2008-08-11|2012-01-17|Cree, Inc.|Mesa termination structures for power semiconductor devices including mesa step buffers|
    US7759186B2|2008-09-03|2010-07-20|The United States Of America As Represented By The Secretary Of The Navy|Method for fabricating junction termination extension with formation of photosensitive dopant mask to control doping profile and lateral width for high-voltage electronic devices|
    SE537101C2|2010-03-30|2015-01-07|Fairchild Semiconductor|Semiconductor Component and Method for Designing a Structure in a Target Substrate for Manufacturing a Semiconductor Component|US10103540B2|2014-04-24|2018-10-16|General Electric Company|Method and system for transient voltage suppression devices with active control|
    US9806157B2|2014-10-03|2017-10-31|General Electric Company|Structure and method for transient voltage suppression devices with a two-region base|
    JP6483838B2|2015-08-21|2019-03-13|株式会社日立製作所|Semiconductor substrate, semiconductor substrate grinding method, and semiconductor device manufacturing method|
    CN109830529A|2019-01-31|2019-05-31|西安理工大学|Super-pressure silicon carbide thyristor of speed and preparation method thereof is opened in a kind of promotion|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US13/366,658|US9349797B2|2011-05-16|2012-02-06|SiC devices with high blocking voltage terminated by a negative bevel|
    PCT/US2013/024740|WO2013119548A1|2012-02-06|2013-02-05|Sic devices with high blocking voltage terminated by a negative bevel|
    [返回顶部]