MEMORY ACCESS PROCESSING METHOD AND APPARATUS, MEMORY CONTROLLER, AND MEMORY ACCESS SYSTEM.

专利摘要:
memory access processing method and apparatus, memory controller, and memory access system. The present invention provides a memory access method and a processing apparatus and system. the method includes: receiving (101) a memory access request sent by a processor; combining (102) multiple memory access requests received within a predefined period of time to form a new memory access request, where the new memory access request includes an array of code bits corresponding to the memory addresses ; and an identifier of the first code bit is configured so that the code bits that are in the code bit vector correspond to the memory addresses accessed by the multiple memory access requests; and sending (103) the new memory access request to a memory controller, such that the memory controller performs a memory access operation of a memory address corresponding to the first code bit identifier. the method effectively improves memory bandwidth utilization.
公开号:BR112016002568B1
申请号:R112016002568-7
申请日:2014-07-30
公开日:2022-01-18
发明作者:Dongrui Fan；Fenglong Song；Da Wang；Xiaochun Ye
申请人:Huawei Technologies Co., Ltd；
IPC主号:

专利说明:

TECHNICAL FIELD
[001] The present invention relates to computer technologies, and in particular, to a memory access processing method and apparatus, and a system. BACKGROUND
[002] During a process of running a computer processor to a speed of data acquisition from an off-chip memory by the processor, directly affects the efficiency of the processor.
[003] The read/write speed of an off-chip memory is much slower than the data processing speed of a processor. Therefore, in order to reduce latency for a processor to read data, a caching technique (cache) is used in the prior art, taking advantage of the temporal locality and spatial location of a program, i.e., a cache is arranged on a processor chip to store data commonly used by the processor. Cache data read/write speed is relatively high. When reading data, the processor accesses the cache first; when the data accessed is not in the cache, the processor accesses off-chip memory using a memory controller. With cache, processor work efficiency can be effectively improved. To facilitate data management, data in a cache is managed with a granularity of a cache line, such as 64 bytes (Byte). When data is read or written between the cache and an off-chip memory, the data is also read into an on-chip cache, along with a granularity of a cache line.
[004] However, when the previous processor reads or writes data, by an application program with bad data location, the processor needs to repeatedly access the off-chip memory using the memory controller, which wastes relatively large bandwidth. access. Also, when a multicore processor simultaneously sends a large amount of memory access operations to the memory controller, because the amount of memory access requests that can be received and processed simultaneously by the memory controller is limited, some Memory access requests are congested in the memory controller and cannot be processed in a timely and efficient manner. SUMMARY
[005] Embodiments of the present invention provide a memory access method and processing apparatus, a memory controller, and a memory access system, which can improve the timeliness of processing a memory access request , and can improve the effective bandwidth utilization of a memory controller.
[006] A first aspect of an embodiment of the present invention provides a method of processing memory access, including: receiving a memory access request sent by a processor; combining multiple memory access requests received within a period of time to form a new memory access request, where the new memory access request includes a base address of the memory addresses accessed by the memory access requests that are combined, a memory access granularity, and a type memory access request, and a code bit vector consisting of code bits corresponding to the memory addresses; and a first code bit identifier indicating that it is not a memory access operation and is set to code bits that are code bit vectors and that correspond to the memory addresses accessed by the memory access requests that are combined ; and sending the new memory access request to a memory controller, so that the memory controller performs, in accordance with the new memory access request, a memory access operation of a memory address corresponding to the first identifier code bit.
[007] With reference to the memory access processing method of the first aspect, in a first form of execution, the combination of multiple memory access requests received within a predefined period of time to form a new memory access request , where the new memory access request includes a base address of the memory addresses accessed by the combined memory access requests, a memory access granularity, and a memory access request type, and a bit vector of code consisting of bits of code corresponding to memory addresses, including: collecting, on the same line of an address index table, the various memory access requests that are received within the predefined time period and that have a same type of memory access request, the same base address of the memory addresses corresponding to the memory access requests, and the same memory access granularity, where each line of the tab It's address index includes a memory access request type, a base address of memory addresses accessed by memory access requests, a memory access granularity, and a code bit vector, where the memory addresses corresponding to all code bits that form a code bit vector on each line have the same base address; and extract the memory access request type, base address, memory access granularity, and a code bit vector of the collected memory access requests from the same row of the code bit address index table to form the new memory access request.
[008] With reference to the first way of implementing the memory access processing method of the first aspect, in a second way of implementation, if the memory access request type of the new memory access request is a memory operation after sending the new memory access request to a memory controller, the method also includes: writing data, which is returned after the memory controller performs the read memory operation according to the new access request memory, for a cache built into the processor; and update the first code bit identifier, which is in the code bit vector of the address index table and corresponds to the memory access operation performed, to a second code bit identifier that indicates that there is no access operation the memory.
[009] With reference to the first form of execution or the second form of implementation of the memory access processing method of the first aspect, in a third form of execution, if the memory access request type of the new memory access request is a write memory operation, after sending the new memory access request to a memory controller, the method also includes: sending data, which corresponds to the write memory operation and is read from a processor cache, to the memory controller, so that the memory controller writes the corresponding data for the write memory operation to a memory address corresponding to the new memory access request; and update the first code bit identifier, which is in the code bit vector of the address index table and corresponds to the memory access operation performed, to a second code bit identifier that indicates that there is no memory access.
[010] With reference to the first form of execution, the second form of execution or the third mode of implementation of the memory access processing method of the first aspect, in a fourth form of execution, if an amount of bits from each memory address is A, an amount of bits of the address index table code bit vector is N, and the memory access granularity is L, the base address of collected memory access requests whose memory access granularity is L in the address index table row has (A - log2(N * L)) bits.
[011] A second aspect of an embodiment of the present invention provides a method of processing memory access, including: receiving a new memory access request, where the new memory access request is formed by combining multiple requests memory access requests received within a predefined time period, and the new memory access request includes a base address of the memory addresses accessed by the combined memory access requests, a memory access granularity, and a type memory access request, and a code bit vector consisting of code bits corresponding to the memory addresses; and a first code bit identifier indicating that there is a working memory access being set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the memory access requests that are combined; and obtaining, when parsing the new memory access request, the memory addresses accessed by the memory access requests that are combined, and performing a memory access operation on memory addresses that are obtained by the analysis.
[012] With reference to the memory access processing method of the second aspect, in a first form of execution, the new memory access request is formed by combining the various memory access requests that are received within the time period predefined and that have the same type of memory access request, the same base address of the memory addresses corresponding to the memory access requests, and the same memory access granularity, and the retrieval, when analyzing the new access request memory, the memory addresses accessed by the memory access requests that are combined include: acquiring the base address and memory access granularity of the memory access requests that are combined into the new memory access request, and position of each first code bit identifier in the code bit vector of the new memory access request; If the acquired position information indicates that the first code bit identifier is in bit “i” of the code bit vector, obtaining, by adding an offset address to the base address of the new memory access request, the memory addresses accessed by the memory access requests that are combined, where the offset address is a product of the acquired memory access granularity and I, and, if an amount of bits from the code bit vector of the new request of memory access is N, the value of i ranges from 0 to N-1.
[013] With reference to the first way of implementing the memory access processing method of the second aspect, in a second way of implementation, if the memory access request type of the new memory access request is a memory operation of reading, performing a memory access operation on the corresponding memory address that is in off-chip memory and obtained by the analysis includes: reading data in the accessed memory addresses that are obtained by the analysis; and return the read data.
[014] With reference to the first way of implementing the memory access processing method of the second aspect, in a third way of implementation, if the memory access request type of the new memory access request is a memory operation of writing, performing a memory access operation on the corresponding memory address that is in off-chip memory and obtained by parsing includes: acquiring the corresponding data for the write memory operation; e write the corresponding data for the write memory operation to the accessed memory addresses that are obtained by the analysis.
[015] A third aspect of the embodiment of the present invention provides a memory access processing apparatus, including: a first acquisition unit configured to receive a memory access request sent by a processor; a combination unit, configured to combine multiple memory access requests received within a predefined period of time to form a new memory access request, where the new memory access request includes a code bit vector consisting of code bits corresponding to memory addresses, a base address of the memory addresses accessed by the memory access requests that are combined, a memory access granularity, and a memory access request type; and a first code bit identifier indicating that it is not a memory access operation is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the memory access requests that are combined ; and a sending unit, configured to send the new memory access request to a memory controller, so that the memory controller executes, in accordance with the new memory access request, a memory access operation of a memory address corresponding to the first code bit identifier.
[016] With reference to the memory access processing apparatus of the third aspect, in a first form of execution, the combination unit is specifically configured to: collect, in the same row of an address index table, the various orders memory access requests that are received within the predefined period of time and that have the same type of memory access request, the same base address of the memory addresses accessed by memory access requests, and the same memory access granularity. memory, where each row of the address index table includes a memory access request type, the base address of memory addresses corresponding to memory access requests, a memory access granularity, and a code bit vector , where the memory addresses corresponding to all the code bits that form a code bit vector in each line have the same base address; Extract the memory access request type, base address, memory access granularity, and memory access request vector collected from the same address index table row to form the new memory access request code bit memory.
[017] With reference to the first form of execution of the memory access processing apparatus of the third aspect, in a second implementation mode, if the memory access request type of the new memory access request is a memory operation the apparatus further includes: a data writing unit configured to write data which is returned after the memory controller performs the read memory operation in accordance with the new memory access request to an integrated cache in the processor; and a first update unit, configured to update the first code bit identifier, which is in the code bit vector of the address index table and corresponds to the memory access operation performed, to a second code bit identifier which indicates that there is no memory access operation.
[018] With reference to the first form of implementation or the second form of implementation of the memory access processing apparatus of the third aspect, in a third form of implementation, if the memory access request type of the new memory access request is a write memory operation, the apparatus additionally includes: a data read unit configured to send data which corresponds to the write memory operation and is read from a processor cache to the memory controller , such that the memory controller writes the corresponding data for the write memory operation to a memory address corresponding to the new memory access request; and a second update unit, configured to update the first code bit identifier, which is in the code bit vector of the address index table and corresponds to the memory access operation performed, to a second code bit identifier which indicates that there is no memory access operation.
[019] With reference to the first form of execution, the second form of execution or the third form of implementation of the memory access processing apparatus of the third aspect, in a fourth form of execution, if an amount of bits of each address of memory is A, an amount of bits of the address index table code bit vector is N, and the memory access granularity is L, the base address of collected memory access requests whose memory access granularity is L in the address index table row has (a - log2(N * L)) bits.
[020] A fourth aspect of the embodiment of the present invention provides a memory controller, including: a second acquisition unit, configured to receive a new memory access request, where the new memory access request is formed by the combination of multiple memory access requests received within a predefined period of time, and the new memory access request includes a code bit vector consisting of code bits corresponding to memory addresses, and a base address of the memory addresses. memory accessed by the memory access requests that are combined, a memory access granularity, and a memory access request type; and a first code bit identifier indicating that it is not a memory access operation being configured to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the memory access requests that are combined; and a memory access unit configured to: obtain, on parsing the new memory access request, the memory addresses accessed by the combined memory access requests, and perform a memory access operation on memory addresses that are obtained by the analysis.
[021] With reference to the memory controller of the fourth aspect, in a first form of implementation, if the new memory access request is formed by combining the various memory access requests that are received within the predefined period of time and that have the same type of memory access request, the same base address of the memory addresses corresponding to the memory access requests, and the same memory access granularity, the memory access unit is specifically configured to: acquire the address basis and memory access granularity of the memory access requests that are combined into the new memory access request, and position information of each first code bit identifier in the code bit vector of the new memory access request ; If the acquired position information indicates that the first code bit identifier is on the ith of the code vector bit, obtaining, by adding an offset address to the base address of the new memory access request, the memory addresses accessed by the memory access requests that are combined, where the offset address is a product of the acquired memory access granularity and I, and, if an amount of bits from the code bit vector of the new access request to memory is N, a value of i ranges from 0 to N - 1; and performing a memory access operation on the obtained memory addresses accessed by the combined memory access requests.
[022] With reference to the memory controller of the fourth aspect or the first form of memory controller implementation, of a second form of implementation, if the memory access request type of the new memory access request is an operation of read memory, the memory access unit is specifically configured to: read the data in the accessed memory addresses that are obtained by the analysis; and return the read data.
[023] With reference to the memory controller of the fourth aspect or the first form of implementation of the memory controller, in a third form of execution, if the memory access request type of the new memory access request is a memory operation memory, the memory access unit is specifically configured to: acquire data corresponding to the write memory operation; and writing the data corresponding to the write memory operation to the accessed memory addresses that are obtained by the analysis.
[024] A fifth aspect of an embodiment of the present invention provides a memory access system, including at least a processor and off-chip memory, wherein the system further includes a memory access processing apparatus. and a memory controller, wherein: the memory access processing apparatus is configured to: combine multiple memory access requests that are sent by the processor and received within a predefined period of time to form a new memory access request memory, where the new memory access request includes a base address of the memory addresses accessed by the combined memory access requests, a memory access granularity, and a memory access request type, and an array of memory access requests. code bit consisting of code bits corresponding to memory addresses; and a first code bit identifier indicating that it is not a memory access operation is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the memory access requests that are combined ; and sending the new memory access request to the memory controller; and the memory controller is configured to: receive the new memory access request; and obtaining, on parsing the new memory access request, the memory addresses accessed by the combined memory access requests, and performing a memory access operation on memory addresses that are obtained by the parse.
[025] In embodiments of the present invention, multiple memory access requests received within a predefined period of time are combined into a new memory access request, so that multiple memory access requests with low bandwidth utilization bandwidth are combined into a new memory access request corresponding to high bandwidth usage during a memory access process, so as to perform a memory controller access operation, in a joined manner, which reduces the number of memory access requests that are sent to the memory controller, helps to improve the bandwidth utilization of a memory, and ensures that the memory controller performs timely processing on a memory access request sent by a processor. When the multiple memory access requests are combined to obtain the new memory access request, a first code bit identifier is set to a memory address accessed by each memory access request that is combined, so that, When the memory controller performs memory access according to the new memory access request, the memory controller can accurately perform a memory access operation on a corresponding memory address according to the first bit identifier of code, thus realizing the effective exchange of data between the processor and an off-chip memory. As a result, in embodiments of the present invention, the opportunity to process a memory access request sent by the processor is improved, and bandwidth utilization is effectively improved when the memory controller is accessed only once. BRIEF DESCRIPTION OF THE DRAWINGS
[026] To describe the technical solutions in the embodiments of the present invention or in the state of the art more clearly, the following briefly introduces the accompanying drawings necessary to describe the embodiments or the state of the art. Apparently, the accompanying drawings in the following description show some embodiments of the present invention, and a person of ordinary skill in the art can still derive other drawings from these accompanying drawings without creative efforts.
[027] FIG. 1 is a flow diagram of embodiment 1 of a memory access processing method in accordance with the present invention.
[028] FIG. 2 is a flow diagram of embodiment 2 of a memory access processing method in accordance with the present invention.
[029] FIG. 3 is a structural schematic diagram of an address index table in accordance with an embodiment of the present invention.
[030] FIG. 4 is a flow diagram of embodiment 3 of a memory access processing method in accordance with the present invention.
[031] FIG. 5 is a schematic structural diagram of embodiment 1 of a memory access processing apparatus in accordance with the present invention.
[032] FIG. 6 is a schematic diagram of structural embodiment 2 of a memory access processing apparatus in accordance with the present invention.
[033] FIG. 7 is a schematic structural diagram of embodiment 3 of a memory access processing apparatus in accordance with the present invention.
[034] FIG. 8 is a schematic structural diagram of an embodiment of a memory controller in accordance with the present invention.
[035] FIG. 9 is a schematic diagram of structural embodiment 1 of a memory access system in accordance with the present invention.
[036] FIG. 10 is a schematic diagram of structural embodiment 2 of an actual application memory access system in accordance with the present invention.
[037] FIG. 11 is a schematic diagram for a result of combining read memory access requests into an address index table of a memory access processing apparatus.
[038] FIG. 12A is a schematic diagram of a memory access process of a new memory access request obtained through the combination in FIG. 11.
[039] FIG. 12B is a schematic diagram of a process of refilling data after memory access is performed for the new memory access request obtained through the combination in FIG. 11.
[040] FIG. 12C is a schematic diagram of a completed state data "rewrite" after the memory access is performed for the new memory access request obtained through the combination in FIG. 11.
[041] FIG. 13 is a schematic diagram for a result of combining memory access requests written into an address index table of a memory access processing apparatus.
[042] FIG. 14 is a schematic diagram of a memory access process of a new memory access request obtained through the combination in FIG. 13. DESCRIPTION OF THE FORMS OF ACHIEVEMENT
[043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the following form fully describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings, in the forms of carrying out the present invention. Apparently, the described embodiments are some, but not all, embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention will fall within the scope of protection of the present invention.
[044] FIG. 1 is a flow diagram of embodiment 1 of a memory access processing method in accordance with the present invention. As shown in FIG. 1, the method in this embodiment is performed by a memory access processing apparatus disposed between a processor and a memory controller, and the method of this embodiment includes: Step 101: receiving a memory access request sent by the processor .
[045] During a process of execution of a computer processor, such as a central processing unit (CPU), when data exchange is carried out between the computer's processor and an off-chip memory, the computer's processor sends a memory access request to the memory controller, disposed between the processor and off-chip memory, and the memory controller reads data from an on-chip cache from off-chip memory according to the read instruction, or writes data from on-chip cache to off-chip memory according to a write instruction. Here, memory access refers to an operation of reading data from or writing data to a memory address in memory outside the processor chip. Therefore, one type of a memory access request sent by the processor may be a read memory access request or a write memory access request. As the data of read or write requests sent by the processor has different granularities and the read requests or the write requests of the data with different granularities occur randomly, if a data granularity of a read request or a write request meets a size of a cache line in the on-chip cache, the memory access request needs to be executed only once, and the processor can directly exchange memory access request data with the on-chip cache later; If a data granularity of a read request or a write request is smaller than a cache memory line size, because the data granularity of the memory access operation does not match the cache line size in cache memory on-chip, each time the processor sends a memory access request, the processor needs to use the memory controller to exchange memory access request data with off-chip memory. In this case, the memory controller frequently performs memory access operations. As a result, it is not conducive to improvement over the memory controller's effective bandwidth usage, as memory access requests are congested in the memory controller and cannot be processed properly. In this embodiment of the present invention, the memory access processing apparatus disposed between the processor and the memory controller can acquire a memory access request sent by the processor, and can perform, in the following form of processing, data processing: combining memory access requests with different granularities sent by the processor, so as to improve memory controller bandwidth usage, and alleviate a problem that memory access requests are congested in the memory controller.Step 102 : Combining multiple memory access requests received within a predefined period of time to form a new memory access request, where the new memory access request includes a code bit vector consisting of code bits corresponding to addresses of memory, a base address of the memory addresses accessed by memory access requests that are combined, a granularity memory access request, and a memory access request type; and a first code bit identifier indicating that there is a memory access operation being set for the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the memory access requests that are combined.
[046] Currently, the memory controller communicates separately with the processor and off-chip memory using a limited number of pins. Therefore, the amount of memory access requests received and processed by the memory controller at the same time is limited. However, each time a memory access request whose granularity data does not satisfy the cache line size in on-chip cache memory is received, the memory controller is required to perform a memory access operation in memory outside the chip. Therefore, on the assumption that memory has a limited number of pins, where the processor sends a large amount of memory access requests with relatively fine granularity, or when a multi-core processor simultaneously sends a large amount of memory requests memory access to the memory controller, the memory access operation for each of the memory access requests takes up some memory access bandwidth, so some memory access requests are congested in the memory controller and cease to be processed in a timely manner. In this embodiment of the present invention, in order to ensure that a memory access request sent by the processor can be received and processed by the memory controller in a suitable manner, the memory access processing apparatus arranged between the processor and the memory controller multiplely combines the memory access requests received within a time period, i.e. the predefined time period, to form a new memory access request. The new memory access request includes a base address of the memory addresses accessed by the memory access requests that are combined, a memory access granularity, and a memory access request type, and a code bit vector. consists of bits of code corresponding to memory addresses. Memory addresses mapped to corresponding code bits in the code bit vector include the memory addresses accessed by memory access requests that are combined, may include a memory address that is not accessed. The first code bit identifier that indicates that there is a memory access operation is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the memory access requests that are combined . That is, the memory access processing apparatus can combine the various memory access requests, which need to be sent to the memory controller at different times, to form a memory access request with relatively fine granularity, and send the formed memory access request to the memory controller as it implements fast processing on the various memory access requests sent by the processor, and can alleviate a problem of a constraint by a memory controller pin amount .
[047] In this way, the access operations of the various memory access requests in the memory controller can be completed by executing an access operation in the memory controller only once, thus improving the controller's bandwidth utilization. memory, ensuring that memory access requests sent by the processor can be processed in a timely manner, and improve processor performance.
[048] The memory access request type of the new memory access request can be a read memory operation or a write memory operation. A base address (base_addr) is the first address of a block of memory space, and all addresses in the block of memory space can be obtained by adding the base address and an intra-block offset address. Memory access granularity is a volume of data that is accessed by a memory access request sent by the processor, and the memory access request can be a memory access request with different granularities such as 8 bytes or 16 bytes .
[049] In this embodiment of the present invention, to ensure that the newly formed memory access request matches the multiple memory access requests combined and that the new memory access request, when being processed, can be accessed with precisely the data of the memory addresses corresponding to the multiple memory access requests combined, when the new memory access request is obtained by combining, a first code bit identifier corresponding, indicating that there is a memory access in operation being set to a memory address accessed by each combined memory access request; Therefore, when the memory controller performs the memory access according to the new memory access request, the memory controller can determine, according to the first code bit identifier realized in the code bit vector of the new request memory access operation, which is not a memory access operation at a corresponding memory address, and perform a memory access operation at the corresponding memory address.
[050] In this embodiment of the present invention, a corresponding first code bit identifier is set in the code bit vector of the new memory access request for the memory addresses accessed by the memory access requests that are combined, so that the memory controller can correctly obtain, through parsing, multiple addresses to be accessed by the processor. These memory addresses can be non-contiguous, and the range of memory addresses of memory access requests that are combined are not limited by the size of the cache line in the on-chip cache. Therefore, the method of this embodiment of the present invention can further support irregular and skipping memory access, which improves the flexibility of setting a memory address. In an existing cache, data writing, replacement and removal are all performed on the drive of a cache line (cache line).
[051] If the cache line is set improperly, a memory access request with relatively fine granularity cannot be processed properly. Compared with the existing cache, in this embodiment of the present invention, a memory access granularity of a memory access request sent by the processor is not limited. In the specific application, the memory access processing apparatus can classify and combine several memory access requests by the same granularity, or the same request type, or the same memory access address range, so as to form a memory access request with relatively fine granularity, and send the formed memory access request to the memory controller to perform a memory access operation in a unified manner. In addition, the code bit identifiers set to the code bit vector of the new memory access request are mapped to the memory addresses of the multiple memory access requests combined, so that during a memory access process , a processing situation of the memory access requests that are combined can be determined according to the code bit identifiers, which guarantees the correct execution of the memory access requests sent by the processor. In a real operation, multiple memory access requests with relatively fine granularities can be combined into one memory access request with relatively fine granularity, so that the memory access operations of multiple memory access requests in the memory controller can be implemented by accessing the memory controller once, which improves memory bandwidth utilization by ensuring that the memory controller can process, in a timely manner, a memory access request sent by the processor, and even improves the flexibility of setting a memory address in the memory access request.Step 103: Send the new memory access request to the memory controller, so that the memory controller executes according to the new request access memory, a memory access operation at a memory address corresponding to the first code bit identifier.
[052] After combining the various memory access requests to form the new memory access request, the memory access processing apparatus can send the new memory access request as a memory access request to the memory access request. memory controller, which prevents a problem that memory bandwidth utilization is relatively low because the memory controller is accessed separately from the various memory access requests and this leads to a decrease in the throughput of processing the requests memory access by the memory controller.
[053] In this embodiment of the present invention, memory access requests sent by the processor with relatively fine memory access granularity can be combined into a memory access request with relatively fine granularity, and the requests memory access granularity with relatively large memory access granularity can also be combined. Memory access requests with a relatively large granularity can be combined into a memory access request with a greater granularity using the method in this embodiment of the present invention.
[054] Likewise, multiple access operations on the memory controller by the multiple memory access requests sent by the processor can be implemented by accessing the memory controller only once.
[055] In this embodiment of the present invention, multiple memory access requests received within a predefined time period are combined into a new memory access request, so that multiple memory access requests with low bandwidth utilization bandwidth are combined into a corresponding new memory access request with high bandwidth usage during the memory access process so as to perform an access operation on a memory controller in a unified way, which reduces the amount of access requests to memory that are sent to the memory controller, helps to improve memory bandwidth usage and further ensures the memory controller to perform timely processing on a memory access request sent by a processor. When the multiple memory access requests are combined to obtain the new memory access request, a first corresponding code bit identifier is set to a memory address accessed by each combined memory access request, so that the controller memory can accurately perform a memory access operation at a corresponding memory address according to the first code bit identifier when memory access is performed in accordance with the new memory access request, thus realizing effective exchange of memory data between the processor and off-chip memory. Therefore, in this embodiment of the present invention, the opportunity to process a memory access request sent by the processor is improved, and the bandwidth utilization is more efficient and improved when the memory controller is accessed only once.
[056] FIG. 2 is a flow diagram of one embodiment of a memory access processing method in accordance with the present invention. As shown in FIG. 2, the method of this embodiment includes: Step 201: receiving a memory access request sent by a processor. Step 202: collecting, in the same row of an address index table, several memory access requests that are received within a predefined period of time and that have the same type of memory access request, the same base address of memory addresses accessed by memory access requests and the same memory access granularity.Step 203: configure accordingly with the base address of the memory addresses accessed by the memory access requests, a first code bit identifier, which indicates that there is a memory access operation, for the code bits that are in a code bit vector in each row of the address index table and that correspond to the memory addresses accessed by the memory access requests that are combined in the row.
[057] In this embodiment of the present invention, to allow a memory controller to quickly analyze and process a memory address to be accessed by a memory access request collected by a memory access processing apparatus and to simplify a structure of the memory access processing apparatus, the various memory access requests that are received within the predefined time period, e.g. 20 milliseconds, and that have the same type of memory access request, the same address base memory addresses corresponding to memory access requests, and the same memory access granularity, are collected for the same address index table row, and the first code bit identifier that indicates that there is an access to the memory. memory operation being set to the code bits that are in the code bit vector in the address index table row and that correspond to the memory addresses memory accessed by the memory access requests that are combined.
[058] In this embodiment, after the memory access request sent by the processor is acquired, the multiple memory access requests that have the same memory access request type, the same base address, and the same granularity memory access requests are collected for the same row of the address index table, and subsequently, the memory access processing apparatus can combine the various memory access requests collected on the same row of the address index table to form a new memory access request, where the new memory access request corresponds to a memory controller access time. After the memory controller receives the new memory access request, the controller performs a memory access memory operation for each of the memory access requests that are combined according to each first code bit identifier configured in the memory controller. new memory access request. Memory access requests simultaneously sent by the processor, especially a multi-core processor, may have different granularities, may include both a read memory access request and a write memory access request, and may still be used by the processor to access base data in different address areas. Therefore, after combination processing is performed on a large number of memory access requests according to the same memory access granularity, the same type of memory access request, and the same base address, multiple access requests new memory access requests are formed, where each new memory access request corresponds to an access operation in the memory controller. When the memory access processing apparatus sends a new memory access request corresponding to a row to the memory controller, the memory controller may perform a memory access operation corresponding to the memory access requests that are combined. on the line. An address index table consists of one row being used as an example for the following description.
[059] FIG. 3 is a structural schematic diagram of an address index table in accordance with an embodiment of the present invention. As shown in FIG. 3 , a memory access request type of address index table type can be a read memory operation or a write memory operation, which are represented by 0 and 1, respectively. The memory access request type indicates which memory access request types of the memory access requests that are combined are all read memory operations or all write memory operations; a base address is the base address of memory addresses accessed by memory access requests that are combined; a memory access granularity indicates a volume of data accessed by the memory access requests that are combined; each code bit, in a code bit vector is corresponding to a memory space memory address, where the memory addresses accessed by the memory access requests that are combined can be encoded by encoding the memory bits. code in the code bit vector.
[060] In practical application, if a memory access request is received within a pre-set time period, and the memory access request indicates access to a memory address, a code bit that is in the code bit vector that corresponds to the memory address is marked as 1, which indicates that: in a new memory access request formed by combining the memory access requests received within the predefined time period, the address memory corresponding to the code bit is to be accessed during a memory access operation corresponding to the new memory access request; if no memory access request indicating access to a memory address is received within a pre-set period of time, a code bit that is in the code bit vector and that corresponds to the memory address is marked as 0, which indicates that: in a new memory access request formed by combining the memory access requests received within the predefined time period, the memory address corresponding to the bitcode is not to be accessed during a memory access operation corresponding to the new memory access request. Therefore, after the new memory access request is formed by the combination, the memory controller can determine, by determining whether a code bit value in the code bit vector is 1 or 0, whether the memory address corresponding to the code bit code is accessed or not during memory access operation. So the code bit vector in the address index table is corresponding to a block of an address space starting from a base address, each code bit in the code bit vector is mapped to a range of addresses whose data volume is a memory access granularity in a memory, and the bitcode identifier indicates whether data within the address range is accessed when the memory controller performs the memory access operation. In this embodiment of the present invention, the first code bit identifier indicates that there is a memory access operation at the memory address mapped to the code bit, and a second code bit identifier indicates that there is no code bit operation. memory access at the memory address mapped to the code bit.
[061] When the multiple memory access requests combined have the same memory access request type, the same base address of the memory addresses corresponding to the memory access requests, and the same memory access granularity, an address memory mapped to bit i of the code bit vector is a memory address that is obtained by adding an offset "granularity *i" to the base address of the address index table, i.e. "base address + granularity *i".
[062] In this way, when the memory controller receives the new memory access request, the memory addresses accessed by the memory access requests that are combined and sent by the processor can be conveniently calculated. That is, when the memory access processing apparatus uses the above method to perform encoding, the memory controller can determine, according to a correspondence between the code bits and the memory addresses, the memory addresses of data to be accessed by memory access requests sent by the processor, so that a memory access operation is performed properly.
[063] In this embodiment of the present invention, if an amount of bits of a memory address in a computer system is A, an amount of bits of the address index table code bit vector is N, and the granularity memory access is L, the base address of collected memory access requests whose memory access granularity is L in the address index table row has (a - log2 (N * L)) bits. Therefore, after the number of bits of the system memory address is determined, a number of bits of the base address can be calculated according to the number of bits of the code bit vector and the granularity of memory access, and the first address of a segment of memory address can be determined. When memory access requests are received, the base address of memory addresses can be determined according to the memory addresses accessed by memory access requests. The following is a system with a 32-bit (bit) memory address and memory access for reading data with a memory access granularity of 8-Byte as an example for description, where memory access with a granularity of (n * 8) Bytes can be thought of as accessing memory n 8 bytes with the same base address. That is, a new memory access request with one (n * 8) -Byte granularity executed by the memory controller can be formed by combining n 8 byte memory access requests with the same base address. In the real application, a match between an address index table granularity and a memory access granularity of a memory access request can be predefined, and the memory controller can determine the memory access granularity of the requests access memory which are matched accordingly upon receiving the new access memory sent by the memory access processing apparatus so as to calculate the base address and a memory address of each memory access request. For example, when an address index table granularity value is set to 0, it indicates that multiple memory access requests with a granularity of 8 bytes are combined, and a memory range mapped to any 1-bit piece of code. in the address index table code bit vector is 8 bytes. If the code bit vector is 128 bits long, the memory range mapped to the code bit new memory access request vector is 1 KB (1024 bits), so it can be determined that the base address in the address index table has 22 bits, and the base address value is the upper 22 bits in the 32-bit memory address. If a memory access granularity mapped to any 1-bit code bit in the code bit vector is 32 bytes, that is, a range of memory mapped to any 1-bit code bit is 32 bytes, and the code bit vector is 128 bits, the memory range mapped to the code bit vector of the newly formed memory access request is 4 KB, and it can be determined that the base address has 20 bits and a value of the base address is the upper 20 bits in the 32-bit memory address.Step 204: Extract the memory access request type, the base address, the memory access granularity, and the code bit vector of the memory requests. Memory access collected from the same code bit address index table row to form a new memory access request.
[064] To timely process memory access requests sent by the processor and to reduce memory access latency, the memory access processing apparatus in the present embodiment of the present extract of the invention, indicated in the address index, memory access request type, base address of memory addresses, memory access granularity, and code bit vector of memory access requests that are collected during the predefined time period of little code, to form the new memory access request.Step 205: Send the new memory access request to a memory controller, so that the memory controller executes according to the new memory access request, a memory access operation on a memory address that is in off-chip memory and that corresponds to the first code bit identifier.
[065] Because the memory addresses accessed by the memory access requests that are combined have the same base address and the same memory access granularity, and the memory addresses accessed by the memory access requests that are combined are addresses in a block of memory, the memory controller can quickly obtain, by parsing the new memory access request, the memory addresses accessed by the combined memory access requests, and perform a memory access operation. That is, the memory controller can quickly calculate the memory addresses accessed according to the base address of the new memory access request and the code bit identifier in the code bit vector.
[066] Furthermore, by using this combination mode in this embodiment of the present invention, the memory access processing apparatus only needs to store, upon receiving the memory access requests sent by the processor, the memory access requests sequentially according to the memory access request type, the base address of the memory addresses accessed by the memory access requests, and the memory access granularity, and perform real-time encoding on the code bit in the memory vector. code bit according to memory addresses accessed by memory access requests. Therefore, the memory access processing apparatus can implement this embodiment of the present invention only by fixing a data table with a simple structure. The simple structure is conducive to the implementation of the memory access processing apparatus structure. In the actual application, multiple rows can be defined for the address index table in the memory access processing apparatus, where each row is used to collect, within a predefined time period, and match the memory access requests that cater for different granularities of memory access, the memory access request having base types or addresses. When a memory access request type, base address, memory access granularity and code bit vector are extracted from the same line, a new memory access request corresponding to the line can be obtained. Step 206: Determining whether the memory access request type is a read memory operation or a write memory operation. If the memory access request is the read memory operation, perform Step 207 and Step 208; if memory access request type is memory write operation, execute Step 209 and Step 210.Step 207: Write data, which is returned after memory controller performs memory read operation according to the new memory access request, to a cache built into the processor.Step 208: Update the first code bit identifier, which is in the code bit vector of the address index table and corresponds to the memory access operation performed, to a second code bit identifier that indicates that there is no memory access operation.
[067] After the new memory access request is sent to the memory controller, the memory controller implements a memory access operation in off-chip memory, interacting with off-chip memory. If the memory access request type is read memory operation, the new memory access operation is to read the memory access request data from off-chip memory into an on-chip cache. During a memory access process, the memory controller returns the request data, which is returned by off-chip memory, to the memory access processing apparatus, so that the memory access processing apparatus can write the returned data to the on-chip cache, that is, the data cache on the home node of the data in the on-chip cache, so as to complete the memory access request sent by the processor.
[068] During this memory access process, the memory controller can parse the code bit vector according to the new memory access request to acquire a memory address mapped to each code bit, so as to acquire the memory addresses accessed by the memory access requests that are combined, and accessing off-chip memory using the acquired memory addresses. A code bit, configured with the first code bit identifier, in the code bit vector of the new memory access request is mapped to a memory address accessed by each memory access request sent by the processor. Therefore, the memory controller can return the data of these memory access requests to cache on the chip, in any sequence multiple times, and register a memory access request processed using the memory access processing apparatus to update a code bit which is in the code bit vector and which corresponds to the memory access request whose data is returned. A status of returning data from read memory operation to on-chip cache can be maintained in real-time in a way of updating a code bit. Specifically, when the code bit identifier is 1, this indicates that the code bit is mapped to a memory access request for off-chip memory. When the memory access request data is written to the on-chip cache, the memory access processing apparatus updates the code bit, which corresponds to the memory access request whose data is returned, from 1 to 0. When the code bit identifiers of all code bits in the code bit vector of the new memory access request are 0, this indicates that all memory access requests that are combined into the new memory access request were executed. Therefore, the entire content of the address index table item can be deleted, so as to collect a new memory access request.Step 209: Send data, which correspond to the write memory operation and are read from a processor cache, to the memory controller, so that the memory controller writes the corresponding data for the memory write operation to a memory address corresponding to the new memory access request.Step 210: Update the first memory identifier code bit, which is in the code bit vector of the address index table and corresponds to the memory access operation performed, to a second code bit identifier that indicates that there is no memory access operation.
[069] If memory access request type is memory write operation, memory write operation is to write memory access request data in on-chip cache to off-chip memory.
[070] During a memory access process, the memory access processing apparatus extracts, according to the memory access requests and the on-chip cache, the data to be written to the off-chip memory; the memory controller generates a memory address from off-chip memory according to the new memory access request obtained by combining, and writes the data extracted by the memory access processing apparatus to the corresponding off-chip memory to complete the write memory operation. During the write operation, the memory access processing apparatus appropriately updates the code bit which is in the code bit vector of the address index table and which corresponds to the memory access request to which the write memory operation has completed, so as to record an execution situation of the write memory operation, i.e. update the code bit so that the write memory operation has completed for the second memory identifier. code bit that indicates that there is no memory access operation.
[071] In this embodiment of the present invention, multiple memory access requests that are received within a predefined period of time, and that have the same memory access request type, the same base address of corresponding memory addresses memory access requests, and the same memory access granularity, are collected from the same row of an address index table, and are combined to form a new memory access request, so that a processing device access memory can collect and combine memory access requests using the address index table which has a simple structure and is easy to implement. Because the memory addresses of the various memory access requests that are combined to form the new memory access request have the same base address, leading to memory access needing to be performed only in a specific memory area, so so the memory access efficiency is relatively high. Memory access requests collected and combined within the predefined time period are sent to the memory controller in a timely manner, which allows the memory controller to process a corresponding memory access operation in a timely manner, helping to reduce memory access latency.
[072] In the real application, a cache that can be integrated into a processor chip includes an on-chip programmable memory (On Chip Programmable Memory, POM for short), such as scratchpad memory (Scratchpad Memory, SPM). , for short), or the like, and/or includes an on-chip cache. In this type of cache, a POM is corresponding to a segment of memory address space, and a data storage location in the POM can be determined by using a memory address, where the storage location is a home node of the data in cache memory. Therefore, whether the data accessed by the processor being cached on the chip can be determined using the source node. When the on-chip cache only includes the POM, for cached data in the PoM, the location of the data in the cache can be determined according to the node. Therefore, when the processor sends a read memory access request, whether the data to be accessed is on the POM can be determined according to the memory address accessed by the read memory access request sent by the processor.
[073] When the memory access request data is read in the POM, the processor can directly obtain the accessed data; when the read memory access request data is not in the POM, the read memory access request needs to be sent to the memory controller for off-chip memory access. Therefore, when the on-chip cache includes only the POM, the memory access processing apparatus disposed between the processor and memory controller is used to perform combination processing on the various memory access requests, and the memory of Access processing returns and caches the data, which is obtained after the memory controller performs the memory access, for each home node in the POM. When the processor sends a write memory access request, the data to be written is cached in the PoM according to the memory address accessed by the write memory access request, and the write memory access request is sent to the memory controller to write cache data to be written to off-chip memory. During this write memory process, several write memory access requests are combined and processed by the memory access processing apparatus. After the memory controller performs the write memory operation, data stored in the off-chip memory is consistent with the data on the on-chip POM, and the processing of the write memory operation is implemented.
[074] When the on-chip cache includes only an on-chip cache, and when a memory access request is sent by the processor does not reach the cache data, the memory controller can be accessed directly, and the memory controller performs a memory access operation in off-chip memory, so as to write the data directly from the memory access request to off-chip memory or read the data into the off-chip memory cache. In the real application, when multiple memory access requests that did not reach the cache data are simultaneously sent to the memory controller, a memory access problem congestion still occurs. In order to ensure that memory access requests that have not reached the cache data can also be processed properly, in this embodiment of the present invention, an on-chip cache policy is adjusted accordingly. For example, an existing cache will be enhanced, and a data source node is defined in the cache, to ensure that whether the data is in the cache can also be determined according to a storage location when the cache is accessed. For the cache in which the data source node is defined, the way of processing the data of the memory access request sent by the processor is similar to that of POM above. Therefore, when the memory access request does not match the cache data, the cache can send the memory access request to the memory access processing apparatus for combination processing, so as to access the memory controller so unified.
[075] When the cache has both a POM and an on-chip cache, an address selector disposed on the processor chip can determine, according to a memory address of a memory access request, whether the memory access request is to access the POM or access the on-chip cache. When the memory address belongs to the PoM address space, the request is a PoM request; otherwise, the request is a cache request. In this case, the address selector can filter a request to access the POM. With respect to the POM access request, the POM can perform processing in the above form of processing that is used when the on-chip cache includes only the POM; as far as the on-chip cache access request is concerned, the on-chip cache can perform processing in the preceding form of processing that is used when the on-chip cache includes only the on-chip cache.
[076] FIG. 4 is a flow diagram of embodiment 3 of a memory access processing method in accordance with the present invention. As shown in FIG. 4 , the method in this embodiment is performed by a memory controller, and the method of this embodiment includes: Step 301: receiving a new memory access request, where the new memory access request is formed by combining several requests memory access requests received within a predefined time period, and the new memory access request includes a code bit vector consisting of code bits corresponding to memory addresses, a base address of the memory addresses accessed by the requests memory access that are combined, a memory access granularity, and a memory access request type; and a first code bit identifier indicating that there is a memory access operation being set for the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the memory access requests that are combined. Step 302: Obtain, when parsing the new memory access request, the memory addresses accessed by the combined memory access requests, and perform a memory access operation on memory addresses that are obtained by the analysis.
[077] In this embodiment, after the memory controller receives the new memory access request which is formed by combining the various memory access requests sent by a memory access processing apparatus, the memory controller acquires them. memory, when parsing the new memory access request, the memory addresses accessed by the memory access requests that are combined, so as to perform a memory access operation in an off-chip memory according to the memory addresses acquired. The new memory access request, which is obtained by combining the several memory access requests, is sent as the memory access request, in a joined manner when it is being sent by the memory access processing apparatus to the memory controller, thereby reducing memory bandwidth usage and improving memory bandwidth utilization. In addition, the code bits corresponding to the first code bit identifier set by the memory access processing apparatus to the code bit vector are mapped to the memory addresses accessed by the memory access requests which are combined, so so that the memory controller can obtain, through analysis, a memory address of off-chip memory accessed by memory access requests sent by a processor; Therefore, memory access requests sent by the processor can be performed properly.
[078] In the concrete application, to simplify a memory access processing apparatus structure and to allow the memory controller to quickly obtain, through analysis, the accessed memory address upon receipt of the new memory access request , the memory access processing apparatus in the present embodiment of the present invention combines the various memory access requests that are collected during the predefined period of time and that have the same type of memory as the access request, the same address basis of the memory addresses corresponding to the memory access requests, and the same memory access granularity, to form the new memory access request. After the memory controller receives the new memory access request, the memory controller first obtains, through parsing, base address information and memory access granularity of the new memory access request, and position information of each first code bit identifier in the code bit vector of the new memory access request, and then acquires, by parsing according to the first code bit identifier configured for the code bits in the vector bit code, the memory addresses accessed by the memory access requests matched by the memory access processing apparatus. A specific process of computing accessed memory addresses is: if the first code bit identifier acquired is in the i-th bit of the code bit vector, obtaining, by adding an offset address to the base address of the new memory access request, the memory addresses accessed by the memory access requests that are combined, where the offset address is a product of the acquired memory access granularity and I, and if a bit-vector bit quantity code of the new memory access request is N, a value of i ranges from 0 to N-1. Therefore, after the memory controller parses the new memory access request to acquire the base address, code bit vector, and memory access granularity, a memory address mapped to the i-th bit of the bit vector code, "base address + granularity *i", can be calculated. Finally, a memory access operation corresponding to the memory access request of type new memory access request is performed on the accessed memory address that is obtained by the analysis.
[079] In this embodiment of the present invention, upon receiving the new memory access request, the memory controller can determine, according to the type of memory access request of the new memory access request, whether to execute a read memory operation or a write memory operation. If the memory access request type of the new memory access request is a read memory operation, the memory controller performs a memory access operation, which corresponds to the memory access request type of the new memory access request. memory access, on accessed memory addresses that are obtained by the analysis, which specifically includes: reading data on accessed memory addresses that are obtained by the analysis; returning the read data to the memory access processing apparatus, such that the memory access processing apparatus writes the returned data to a cache integrated into a processor chip; and updating a code bit identifier, which is in the vector of a code bit address index table and corresponding to the memory access request whose data is returned, to a second code bit identifier indicating that no there is memory access operation. If the memory access request type of the new memory access request is a write memory operation, the memory controller performs a memory access operation, which corresponds to the memory access request type of the new memory access request. memory access, in the accessed memory addresses that are obtained by the analysis, which includes: acquiring data, sent by the memory access processing device, which corresponds to the write memory operation; and writing the corresponding data for the write memory operation to the accessed memory addresses that are obtained by the analysis.
[080] In this embodiment, a memory controller performs, according to a new memory access request received, a memory access operation of a memory address that is in an off-chip memory and that is corresponding to a code bit to which a first code bit identifier is set, thereby effecting processing on combined memory access requests by a memory access processing apparatus. During a memory access process, the memory controller implements a process of receiving and processing multiple memory access requests, receiving memory access requests once, which effectively improves memory bandwidth utilization and ensures that a memory access request sent by a processor is being processed properly.
[081] A person of ordinary skill in the art can understand that all or a part of the steps of the embodiments of the method can be implemented by relevant hardware for programming instructions. The program may be stored on a computer readable storage medium. When the program is executed, a processor, such as a central processing unit (central processing unit, the CPU), executes the steps of embodiments of the previous method. The foregoing storage medium includes: any medium that can store program code, such as read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), a magnetic disk or an optical disc.
[082] FIG. 5 is a schematic diagram of structural embodiment 1 of a memory access processing apparatus in accordance with the present invention. As shown in FIG. 5 , the apparatus in this embodiment of the present invention includes: a first acquisition unit 40 configured to receive a memory access request sent by a processor; a combining unit 41, configured to combine multiple memory access requests received within a predefined period of time to form a new memory access request, wherein the new memory access request includes a code bit vector consisting of in bits of code corresponding to memory addresses, a base address of the memory addresses accessed by the memory access requests that are combined, a memory access granularity, and a memory access request type, and a first memory access identifier. code bit indicating that it is not a memory access operation being set to the code bits that are in the code bit of the vector and corresponding to the memory addresses accessed by the memory access requests that are combined; and a sending unit 42, configured to send the new memory access request to a memory controller, so that the memory controller executes, in accordance with the new memory access request, a memory access operation of a memory address corresponding to the first code bit identifier.
[083] The memory access processing apparatus in the present embodiment of the present invention is arranged in a memory access path between the processor and memory controller, and is configured to: combine multiple memory access requests sent by the memory processor to form a new memory access request, and send the new memory access request to the memory controller in a unified manner so as to reduce memory bandwidth usage; and use the memory controller to access off-chip memory. The first acquisition unit of 40 receives memory access requests sent by the processor; the combining unit 41 combines the various memory access requests received by the first acquisition unit 40 within the predefined time period, and sets the first code bit identifier corresponding to the memory addresses accessed by the memory access requests, so that the memory controller can accurately obtain, through analysis, the memory addresses accessed; the sending unit 42 sends, to the memory controller, the new memory access request that is obtained by combining performed by the combining unit 41, so that the memory controller performs the memory access operation in the memory outside the chip according to the new memory access request.
[084] In this embodiment of the present invention, a combining unit combines multiple memory access requests received within a predefined period of time to form a new memory access request, such that multiple memory access requests with relatively low bandwidth usage are combined into a new memory access request corresponding to high bandwidth usage during a memory access process so as to perform a memory controller access operation in a way unified memory, which reduces the amount of memory access requests that are sent to the memory controller, helps improve memory bandwidth utilization, and even ensures that the memory controller performs timely processing on a request memory access sent by a processor. When the multiple memory access requests are combined to obtain the new memory access request, a first corresponding code bit identifier is set to a memory address accessed by each combined memory access request, so that the memory controller can accurately perform a memory access operation on the corresponding memory address according to the first code bit identifier when performing memory access according to the new memory access request, thus realizing effective swap of data between the processor and off-chip memory. Therefore, in this embodiment of the present invention, the timeliness of processing a memory access request sent by the processor is improved, and the memory bandwidth utilization is more efficient and improved during a memory access process.
[085] FIG. 6 is a schematic diagram of structural embodiment 2 of a memory access processing apparatus in accordance with the present invention. As shown in FIG. 6 , in this embodiment, a combining unit 41 is specifically configured to: collect, on the same row of an address index table, multiple memory access requests that are received within a predefined time period and that have the same type of memory access request, the same base address of memory addresses corresponding to the memory access requests and the same memory access granularity, where each row of the address index table includes a type of access request to memory, a base address of memory addresses corresponding to memory access requests, a granularity of memory access, and a code bit vector, and memory addresses corresponding to all code bits that form a bit vector of code on each line has the same base address; and extracting the memory access request type, base address, memory access granularity, and memory access request vector collected from the same row of code bit address index table to form a new memory access request. The determining unit 47 is configured to determine, according to the type of memory access request in each row of the address index table, whether the new memory access request corresponding to the row is a read memory operation or a write memory operation. A data writing unit 43 is configured for: when the memory access request type of the new memory access request is a read memory operation, write data, which is returned after a memory controller performs the operation memory according to the new memory access request, to a cache integrated in a processor. A first update unit 44 is configured to update a first code bit identifier, which is in the code bit vector of the address index table and corresponds to the memory access operation performed, to a second code bit identifier. code indicating that there is no access to operating memory. A data read unit 45 is configured for: when the memory access request type of the new memory access request is a write memory operation, send data, which corresponds to the write memory operation and is read from a processor cache to the memory controller, so that the memory controller writes the corresponding data for the memory write operation to a memory address corresponding to the new memory access request. A second update unit 46 is configured to update the first code bit identifier, which is in the code bit vector of the address index table and corresponds to the memory access operation performed, to the second code bit identifier. which indicates that there is no access to working memory.
[086] In this embodiment, the combination unit 41 collects, for the same row of the address index table, several memory access requests that are received within a period and that have the same type of memory access request. memory, a same base address of memory addresses corresponding to the memory access requests, and the same memory access granularity, and combines the various memory access requests into a new memory access request. The sending unit 42 sends the new memory access request to the memory controller which is acquired by combination. When the determination unit 47 determines that the corresponding new memory access request is read in the memory operation, i.e., the memory access request sent by the processor indicates the reading of data from an off-chip memory to a On-chip cache, the memory controller interacts with the off-chip memory to execute the new memory access request, receives the data returned from the off-chip memory, and returns the returned data to a first acquisition unit 40 of the memory device. memory access processing, whereby the data writing unit 43 of the memory access processing apparatus writes the memory access request data acquired by the first acquisition unit 40 to a data node in the on-chip cache.
[087] During a data stuffing process, data can be written to the cache progressively many times, and the first update unit 44 updates a configured identifier for a code bit in the code bit vector of the index table. address in order to register the memory access request whose data was returned. When the determination unit 47 determines that the corresponding new memory access request is a write memory operation, that is, the memory access request sent by the processor indicates the writing of data in an on-chip cache to an off-chip memory from the chip, the data reading unit 45 of the memory access processing apparatus reads the data from the on-chip cache; the sending unit 42 sends the read data to the memory controller; After receiving the new memory access request and the corresponding data, the memory controller generates an off-chip memory memory address according to the code bit vector and the base address, and writes the corresponding data to the generated memory address. During a data write operation, the second update unit 46 has changes, in real time, to a code bit identifier that is in the code bit vector and that corresponds to the memory access request for which the write memory operation has been completed. During a process in which the memory access processing apparatus collects a memory access request to store that address index table, if a number of bits of a memory address is A, a number of bits of the vector of code bit of the address index table is N, and a memory access granularity is L, the base address in a row of the memory access request collected with the memory access granularity L in the address index table has (A - log2(N*L)) bits. That is, after the number of bits of the memory address in a system is determined, a number of bits of the base address can be calculated according to the number of bits in the code bit vector and the granularity of memory access, and the first address of a segment of memory address can be determined. In this case, the received memory access request can be collected into the address index table that corresponds to the base address and memory access granularity. After the memory access processing apparatus combines the various memory access requests that have the same type of memory access request, the same base address of the memory addresses corresponding to the memory access requests, and the same granularity access memory, the memory controller can accurately obtain, through analysis and in accordance with the first code bit identifier configured for the code bit vector, the memory addresses accessed by the memory access requests that are combined to perform a memory access operation.
[088] In this embodiment, several memory access requests, which have the same type of memory access request, the same base address of memory addresses corresponding to the memory access requests, and the same memory access granularity memory, are combined, which allows a memory controller to process memory access requests sent by a processor in a timely and accurate manner, helping to improve the memory controller's bandwidth utilization, and even make a memory structure a simple and easy to implement memory access processing apparatus.
[089] FIG. 7 is a schematic diagram of structural embodiment 3 of a memory access processing apparatus in accordance with the present invention. As shown in FIG. 7 , the memory access processing apparatus in the present embodiment includes a processor 80, a memory 82, a communications interface 84, and a bus 83, where the processor 80, the communications interface 84, and the memory 82 meet. communicate with each other using bus 83; memory 82 is configured to store a program instruction, for example, instruction code corresponding to the operating steps of the memory access processing method in the previous embodiment; processor 80 may be configured to execute the program instruction stored in memory 82; communications interface 84 may be configured to send or receive the program instruction between the processor and memory or data that is generated in accordance with the program instruction; and bus 83 is configured to implement communication between function units within the memory access processing apparatus.
[090] FIG. 8 is a schematic structural diagram of an embodiment of a memory controller in accordance with the present invention. As shown in FIG. 8 , in this embodiment, the memory controller includes: a second acquisition unit 50 configured to receive a new memory access request, where the new memory access request is formed by combining several memory access requests received within a predefined period of time, and the new memory access request includes a code bit vector consisting of code bits corresponding to memory addresses, a base address of the memory addresses accessed by memory access requests which are combined, a memory access granularity and a memory access request type, and a first code bit identifier, indicating that there is a memory access operation being configured for the code bits that are in the vector of code bits and that correspond to the memory addresses accessed by the memory access requests that are combined; and a memory access unit 51 configured to obtain, by parsing the new memory access request, the memory addresses accessed by the combined memory access requests, and perform a memory access operation on memory addresses that are obtained by the analysis.
[091] In this embodiment, after the second acquisition unit 50 of the memory controller receives the new memory access request which is formed by combination performed by a memory access processing apparatus, because the new memory access request memory is configured with the first code bit identifier corresponding to memory addresses accessed by memory access requests, the memory controller can obtain, through analysis, a memory address to be accessed according to the first memory identifier set code bit, and performing a corresponding memory access operation according to the memory access granularity and memory access request type of the new memory access request, so as to complete the memory access operation for a processor.
[092] Upon receiving a new memory access request in a unified way, the memory controller can complete receive processing in multiple memory access requests sent by the processor, thus improving bandwidth utilization and reducing memory access latency. .
[093] To allow the memory controller to quickly calculate a memory address for a memory access operation and to implement a simple structure of the memory access processing apparatus, when the memory access processing apparatus combines the various memory access requests that are received within the predefined time period and that have the same memory access request type, the same base address as the memory addresses corresponding to the memory access requests, and the same memory access granularity. memory, to form the new memory access request, after the second acquisition unit 50 of the memory acquisition controller the new memory access request sent by the memory access processing apparatus, the memory access unit 51 has obtained , through parsing, the base address and memory access granularity of the memory access requests that are combined into the new memory access request, and the position information of each first code bit identifier in the code bit vector of the new memory access request; if the acquired position information indicates that the first code bit identifier is in the ith bit of the code bit vector, the memory access unit 51 obtains, by adding a shift address to the base address of the new memory access request, the memory addresses accessed by the memory access requests that are combined, where the offset address is a product of the acquired memory access granularity and I, and if a bit-vector bit quantity code of the new memory access request is N, a value of i ranges from 0 to N-1; the memory access unit 51 performs a memory access operation on memory addresses accessed by the combined memory access requests that are obtained by the second acquisition unit 50.
[094] If the memory access request type of the new memory access request is a read memory operation, the memory access unit is configured specifically to read the data in the accessed memory addresses that are obtained by the analysis , and return the read data to the memory access processing apparatus, whereby the memory access apparatus writes the returned data to a cache built into the processor. If the memory access request type of the new memory access request is a write memory operation, the memory access unit is specifically configured to acquire data corresponding to the write memory operation and sent by the memory device. memory access processing, and writing the corresponding data for the memory write operation to the accessed memory addresses that are obtained by the analysis.
[095] In this embodiment of the present invention, after a second acquisition unit of a memory controller acquiring a new memory access request which is formed by combination performed by a memory access processing apparatus, a memory access acquires, through analysis and in accordance with a first code bit identifier configured to a code bit vector of the new memory access request, memory addresses accessed by memory access requests which are combined, and perform a memory access operation on memory addresses that are obtained by the analysis. In this way, instead of separately executing an access operation for many times in the memory controller for multiple memory access requests sent by a processor, an access operation is properly performed in off-chip memory for a new memory request. memory access, thus improving memory bandwidth utilization and reducing memory access latency.
[096] An embodiment of the present invention further provides a memory access system, including: at least one processor, off-chip memory, the above memory access processing apparatus shown in FIG. 5, FIG. 6 or Fig. 7, and the memory controller shown in fig. 8. The memory access processing apparatus is configured to: combine multiple memory access requests that are sent by the processor and received within a predefined time period to form a new memory access request, where the new request memory access memory includes a code bit vector consisting of code bits corresponding to the memory addresses, a base address of the memory addresses accessed by the memory access requests that are combined, a memory access granularity, and a type memory access request; and a first code bit identifier indicating that there is a memory access operation that is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the memory access requests that are combined ; and sending the new memory access request to the memory controller. The memory controller is configured to: receive the new memory access request, obtain, when parsing the new memory access request, the memory addresses accessed by the combined memory access requests, and perform an access operation memory over the memory addresses that are obtained by the analysis.
[097] FIG. 9 is a schematic diagram of structural embodiment 1 of a memory access system in accordance with the present invention. As shown in FIG. 9, the system in this embodiment includes multiple processing logic 601, multiple on-chip memories 602, memory access processing apparatus 603, memory controller 604, and off-chip memory 605, wherein the logic processor 601 may correspond to multiple processor cores; the multiple on-chip 602 memories are on-chip caches; and the memory access processing apparatus 603 is configured to combine the memory access requests of different granularities, which are sent by the processing logic 601 through the memories on the chip 602, to form a memory access request with a relatively fine-grained, where the process of combining memory access requests includes: receiving a memory access request sent by a processor; combining multiple memory access requests received within a predefined period of time to form a new access request to memory, where the new memory access request includes a code bit vector consisting of code bits corresponding to memory addresses, a base address of the memory addresses accessed by memory access requests that are combined, a granularity of memory access, and a memory access request type, and a first code bit identifier indicating that an operation exists memory access that is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the memory access requests that are combined; and sending the new memory access request to the memory controller 604, so that the memory controller performs, in accordance with the new memory access request, a memory access operation of a memory address that is in the memory outside of chip 605 and which corresponds to the first code bit identifier.
[098] The memory access processing apparatus 603 can combine the various memory access requests and send the memory access requests to the memory controller in a unified manner, and then the memory controller performs the operation memory access in off-chip memory, thus improving memory bandwidth utilization effectively. The memory access processing apparatus 603 in this embodiment may be the prior apparatus shown in FIG. 5, FIG. 6 or Fig. 7.
[099] In real applications, what precedes on-chip memory in FIG. 9 may include a POM and a cache, and FIG. 10 is a schematic diagram of structural embodiment 2 of an actual application memory access system in accordance with the present invention. As shown in FIG. 10, a processor chip in the system includes multiple address selectors 702, which are separately corresponding to multiple processing logic 701, where an address selector 702 is configured to determine, in accordance with a memory access request sent by each logic of processing 701, if a memory address access for the memory access request is in a POM address space; and if the memory access address for the memory access request is in the address space of the POM, sending the memory access request to a POM 704; Otherwise, send the memory access request to a cache 703. The memory access request sent to the POM 704 is sent to an address index table in a memory access processing apparatus 705 via the POM 704, and the memory access request is collected and combined into the address index table. If a memory access request type, base address, and current memory access request granularity are different from those in any existing row in the address index table, a new row is allocated in the address index table. according to the memory access request type of the current memory access request, the base address corresponding to the memory address accessed by the current memory access request, and the memory access granularity; and a code bit in a memory access request vector current of the code bit being encoded. If the memory access request type, base address and memory access granularity of the current memory access request are the same as an existing row in the address index table, the current memory access request is matched to the line, and a code bit corresponding to the memory address of the current memory access request is encoded. When address selector 702 determines that the memory address is not in the POM address space, address selector 702 sends the memory access request to cache 703, and Cache 703 sends the memory access request to a memory controller 706 for performing a memory access operation.
[100] In actual application, if cache 703 is an on-chip cache on which a data source node is defined, i.e., a cache policy on the management chip is partially modified to add a data node, the cache it may also send the memory access request from the memory access processing apparatus for combination processing. Therefore, when the cache 703 receives the memory access request, if the lookup data is in the cache, the data is directly forwarded to the processing logic 701; If the request data is not in the cache, i.e. the cache data is not reached, the cache can send the memory access request that did not reach the data (Lost Cache Request) to the memory access processing apparatus. memory 705. The memory access processing apparatus 705 can combine the memory access requests that have not reached the data and send the memory access requests to the memory controller in a unified manner. For a process of handling the combination performed by the memory access processing apparatus on memory access requests that did not reach the data, refer to the embodiment shown in FIG. 1 or FIG. 2, and the details are not described again in this document. If all of the above on-chip memories in the embodiment shown in FIG. 9 are caches, a mode in which the memory access processing apparatus performs, by setting a data source node, combination processing on memory access requests that have not reached the Cache data may also be used. The memory access processing apparatus 705 sends the new memory access requests, formed by the combination, in the address index table to the memory controller 706, so that the memory controller interacts with an off-chip memory 707. in a suitable way to implement a memory access operation.
[101] The following is a system in which a 32-bit memory address is used, a read memory operation and a write memory operation with a memory access granularity of 8 bytes as an example for a detailed description .
[102] FIG. 11 is a schematic diagram for a result of combining read memory access requests into an address index table of a memory access processing apparatus; FIG. 12A is a schematic diagram of a memory access process and a new memory access request obtained through the combination in FIG. 11; FIG. 12B is a schematic diagram of a data stuffing process after memory access is performed for the new memory access request obtained by combining in FIG. 11; FIG. 12C is a schematic diagram of a completed state data rewrite after the memory access being performed for the new memory access request obtained through the combination in FIG. 11. As shown in FIG. 11, and FIG. 12A to FIG. 12C, which can be determined, according to a granularity value of 8 bytes and a 128-bit vector code bit, that a base address is 22 bits, and two memory read access requests with a granularity of 8 bytes are combined to new memory from the access request, that is, a read memory operation is performed by the new memory access request from a memory address that is corresponding to a code bit whose identifier is 1 in the vector of code bit in FIG. 11.
[103] Since the operation is a read-memory operation, a memory controller can directly perform the read-memory operation on an off-chip memory according to the new memory access request. Specifically, the memory controller calculates the memory address according to the code bit whose identifier is 1 and the base address of the new memory access request, and performs an off-chip memory read operation; after data from a memory address corresponds to a code bit is reloaded with a POM, the corresponding code bit is updated. After the data is reloaded the address index table in FIG. 11, the address index table is in a state shown in FIG. 12B. When all code bits in a code bit vector in a row of the address index table are 0, it indicates that the padding of all memory access requests that are combined in the data row is complete. As shown in FIG. 12C, the input contents in the address index table row can be deleted.
[104] FIG. 13 is a schematic diagram for a result of combining write memory access requests into an address index table of a memory access processing apparatus; FIG. 14 is a schematic diagram of a memory access process of a new memory access request obtained through the combination in FIG. 13. As shown in FIG. 13 and FIG. 14, it can be determined, according to a granularity value of 8 bytes and a code bit vector of 128 bits, that a base address is 22 bits long, and two write memory access requests with a granularity of 8 bytes are combined for the new memory access request, i.e. a write memory operation is performed by the new memory access request of a memory address that is corresponding to a code bit whose identifier is 1 in the bit vector code in FIG. 13; the memory access processing apparatus reads data from the memory address corresponding to the code bit of a POM or a cache. Since the operation is a write memory operation, after the new memory access request is sent to a memory controller, the memory controller generates the memory address by computing according to the code bit in the memory. code bit vector and base address, and writes the data, which is read by the memory access processing apparatus, to the memory address of an off-chip memory generated by the memory controller. During the write memory operation, the memory access processing apparatus updates the code bit of the corresponding memory address where the write operation was completed by the memory controller, and the write memory operation is complete until all code bits are 0 in the code bit vector. The memory access processing apparatus can erase the input content in a row, in which a code bit vector whose code bits are all 0 lies, from the address index table.
[105] It should be noted that the foregoing embodiments are intended merely to describe the technical solutions of the present invention, but not to limit the present invention. While the present invention is described in detail with reference to exemplary embodiments, a person of ordinary skill in the art should understand that they can still make equivalent modifications or substitutions to the technical solutions of the present invention without departing from the scope of the present invention.

权利要求:
Claims (16)
[0001]
1. A memory access processing method, CHARACTERIZED by comprising: receiving (101) a memory access request sent by a processor; combining (102) several memory access requests received within a predefined period of time to form a new memory access request, wherein the new memory access request comprises a code bit vector consisting of code bits corresponding to the memory addresses, a base address of the memory addresses accessed by the various memory access requests , a memory access granularity, and a memory access request type; and a first code bit identifier indicating that there is a memory access operation is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the various memory access requests; and send (103) the new memory access request to a memory controller, so that the memory controller performs, in accordance with the new memory access request, a memory access operation at a memory address corresponding to the first code bit identifier; wherein combining (102) the various memory access requests received within a predefined period of time to form a new memory access request, wherein the new memory access request comprises an array bit code consisting of code bits corresponding to memory addresses, a base address of the memory addresses accessed by the various memory access requests, a memory access granularity, and a memory access request type, comprises :collect (202), on the same row of an address index table, the various memory access requests that are received within the predefined period of time and that have the same type of memory access request the same base address of the memory addresses corresponding to the various memory access requests, and the same memory access granularity, where each row of the address index table comprises a type of memory access request, an address base of memory addresses accessed by memory access requests, a memory access granularity, and a code bit vector, where memory addresses corresponding to all code bits that form a code bit vector in each line has the same base address; and extract (204) the memory access request type, base address, memory access granularity, and code bit vector of the collected memory access requests from the same address index table row for form the new memory access request.
[0002]
2. Method, according to claim 1, CHARACTERIZED by the fact that: if the type of memory access request of the new memory access request is a read memory operation, after sending the new memory access request memory to a memory controller, the method further comprises: writing (207) data, which is returned after the memory controller performs the read memory operation in accordance with the new memory access request, to a cache integrated in the memory controller. processor; and updating (208) the first code bit identifier, which is in the code bit vector of the address index table and corresponding to the performed read memory operation, to a second code bit identifier that indicates that there is no the memory access operation.
[0003]
3. Method, according to claim 1, CHARACTERIZED by the fact that: if the type of memory access request of the new memory access request is a write memory operation, after sending the new memory access request memory to a memory controller, the method further comprises: sending (209) data, which corresponds to the write memory operation and is read from a processor cache, to the memory controller, so that the controller memory writes the data corresponding to the write memory operation to a memory address corresponding to the new memory access request; and updating (210) the first code bit identifier, which is in the code bit vector of the address index table and corresponding to the performed write memory operation, to a second code bit identifier that indicates that there is no memory access operation.
[0004]
4. Method according to any one of claims 1 to 3, CHARACTERIZED by the fact that: if an amount of bits of each memory address is A, an amount of bits of the code bit vector is N, and the granularity memory access is L, the base address of the memory addresses accessed by the various memory access requests whose memory access granularity is L has (A - log2(N * L)) bits.
[0005]
5. Memory access processing method, CHARACTERIZED by comprising: receiving (301) a new memory access request, wherein the new memory access request is formed by combining several memory access requests received within a predefined period of time, and the new memory access request comprises a base address of the memory addresses accessed by the various memory access requests, a memory access granularity, and a memory access request type, and an array code bit consisting of code bits corresponding to memory addresses; and a first code bit identifier indicating that there is a memory access operation is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the various memory access requests; and get (302), by parsing the new memory access request, the memory addresses accessed by the various memory access requests, and performing a memory access operation on the memory addresses that are obtained by the analysis; wherein the new memory access request is formed by combining several memory access requests received within a predefined period of time comprises: the new memory access request is formed by combining several memory access requests that are received within the period time and which have the same type of memory access request, the same base address of the memory addresses corresponding to the various memory access requests, and the same memory access granularity.
[0006]
6. Method, according to claim 5, CHARACTERIZED by the fact that obtaining, when analyzing the new memory access request, the memory addresses accessed by the various memory access requests comprises: acquiring the base address and the granularity of accessing the memory of the various memory access requests in the new memory access request, and position information of each first code bit identifier in the code bit vector of the new memory access request; If the acquired position information indicates that the first code bit identifier is in the i-th bit of the code bit vector, obtain, by adding an offset address to the base address of the new memory access request, the memory addresses accessed by the various memory access requests, where the offset address is a product of the acquired memory access granularity ei, and, if a number of bits of the code bit vector of the new memory access request is N, a value of i ranges from 0 to N-1.
[0007]
7. Method according to claim 5 or 6, CHARACTERIZED by the fact that: if the memory access request type of the new memory access request is a read memory operation, perform a memory access operation in the corresponding memory addresses that are in an off-chip memory and are obtained by the analysis comprises: reading data in the accessed memory addresses that are obtained by the analysis; and return the read data.
[0008]
8. Method, according to claim 5 or 6, CHARACTERIZED by the fact that: if the memory access request type of the new memory access request is a write memory operation, perform a memory access operation memory at the corresponding memory addresses that are in an off-chip memory and are obtained by the analysis comprises: acquiring the corresponding data for the memory write operation; e write the corresponding data for the memory write operation to the accessed memory addresses that are obtained by the analysis.
[0009]
9. Memory access processing apparatus, CHARACTERIZED in that it comprises: a first acquisition unit (40), configured to receive a memory access request sent by a processor; a combination unit (41), configured to combine several requests memory access requests received within a predefined period of time to form a new memory access request, wherein the new memory access request comprises a code bit vector consisting of code bits corresponding to memory addresses, a base address of the memory addresses accessed by the various memory access requests, a memory access granularity, and a memory access request type; and a first code bit identifier indicating that there is a memory access operation is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the various memory access requests; and a sending unit (42) configured to send the new memory access request to a memory controller, so that the memory controller performs, in accordance with the new memory access request, a memory access operation at a memory address corresponding to the first code bit identifier; wherein the combining unit (41) is specifically configured to: collect, for the same row of an address index table, the various memory access requests that are received within the predefined period of time and that have the same type of memory access request, the same base address of the memory addresses accessed by the various memory access requests, and the same memory access granularity, in which each The address index table row comprises a memory access request type, a base address of memory addresses corresponding to memory access requests, a memory access granularity, and a memory access granularity. code bit tor, where memory addresses corresponding to all code bits that form a code bit vector on each line have the same base address; and extracting the memory access request type, base address, memory access granularity, and code bit vector of the collected memory access requests from the same address index table row to form the new memory access request.
[0010]
10. Device, according to claim 9, CHARACTERIZED by the fact that: if the type of memory access request of the new memory access request is a read memory operation, the device further comprises: a unit of writing data (43), configured to write data, which is returned after the memory controller performs the read memory operation in accordance with the new memory access request, to a cache integrated in the processor; and a first update unit (44), configured to update the first code bit identifier, which is in the code bit vector of the address index table and corresponds to the performed read memory operation, to a second code identifier. code bit that indicates that there is no memory access operation.
[0011]
11. Device, according to claim 9, CHARACTERIZED by the fact that: if the type of memory access request of the new memory access request is a write memory operation, the device further comprises: a unit of read data (45), configured to send the data, which corresponds to the write memory operation and is read from a processor cache, to the memory controller, so that the memory controller writes the corresponding data for the memory operation writing to a memory address corresponding to the new memory access request; and a second update unit (46), configured to update the first code bit identifier, which is in the code bit vector of the address index table and corresponds to the executed write memory operation, to a second code identifier. code bit that indicates that there is no memory access operation.
[0012]
12. Apparatus according to any one of claims 9 to 11, CHARACTERIZED by the fact that: if an amount of bits of each memory address is A, an amount of bits of the code bit vector is N, and the granularity memory access is L, the base address of the memory addresses accessed by the various memory access requests whose memory access granularity is L has (A - log2(N * L)) bits.
[0013]
13. Memory controller, CHARACTERIZED in that it comprises: a second acquisition unit (50), configured to receive a new memory access request, wherein the new memory access request is formed by the combination of several memory access requests received within a predefined period of time, and the new memory access request comprises a code bit vector consisting of code bits corresponding to the memory addresses, a base address of the memory addresses accessed by the various memory access requests , a memory access granularity, and a memory access request type; and a first code bit identifier indicating that there is a memory access operation is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the various memory access requests; and a memory access unit (51) configured to: obtain, upon parsing the new memory access request, the memory addresses accessed by the various memory access requests, and perform a memory access operation on the memory addresses which are obtained by the analysis; wherein if the new memory access request is formed by combining the various memory access requests that are received within the predefined period of time and that have the same type of memory access request, a same base address of the memory addresses corresponding to the various memory access requests, and the same memory access granularity, the memory access unit (51) is specifically configured to: acquire the base address and memory access granularity of the various memory access requests in the new memory access request, and position information of each first code bit identifier in the code bit vector of the new memory access request; if the acquired position information indicates that the first code bit identifier is in the ith bit of the code bit vector, obtain, by adding an offset address to the base address of the new memory access request, the memory addresses accessed by the various memory access requests, where the offset address is a product of the acquired memory access granularity ei, and if a number of bits of the code bit vector of the new memory access request is N, the value of i ranges from 0 to N-1; and performing a memory access operation on the obtained memory addresses accessed by the various memory access requests.
[0014]
14. Memory controller, according to claim 13, CHARACTERIZED by the fact that: if the memory access request type of the new memory access request is a read memory operation, the memory access unit ( 51) is specifically configured to: read data in accessed memory addresses that are retrieved by the analysis; and return the read data.
[0015]
15. Memory controller, according to claim 13, CHARACTERIZED by the fact that: if the memory access request type of the new memory access request is a write memory operation, the memory access unit ( 51) is specifically configured to: acquire data corresponding to the write memory operation; and writing the data corresponding to the write memory operation to the accessed memory addresses that are obtained by the analysis.
[0016]
16. Memory access system, CHARACTERIZED in that it comprises at least a processor (601) and an off-chip memory (605), wherein the system further comprises a memory access processing apparatus (603) and a memory controller (604), wherein: the memory access processing apparatus (603) is configured to: combine multiple memory access requests that are sent by the processor (601) and received within a predefined period of time, to form a new memory access request, wherein the new memory access request comprises a code bit vector consisting of code bits corresponding to memory addresses, a base address of the memory addresses accessed by the various memory requests memory access, a memory access granularity, and a memory access request type; and a first code bit identifier indicating that there is a memory access operation is set to the code bits that are in the code bit vector and that correspond to the memory addresses accessed by the various memory access requests; and sending the new memory access request to the memory controller (604); and the memory controller (604) is configured to: receive the new memory access request; and obtaining, by analyzing the new memory access request, the memory addresses accessed by the various memory access requests, and performing a memory access operation on the memory addresses that are obtained by the analysis; wherein the processing apparatus access memory (603) is specifically configured to: collect, for the same row of an address index table, the various memory access requests that are received within the predefined time period and that have the same request type access memory, the same base address of the memory addresses accessed by the various memory access requests, and the same memory access granularity, where each row of the address index table comprises a type of memory access request , a base address of memory addresses corresponding to memory access requests, a memory access granularity, and a code bit vector, where memory addresses corresponding to all the The code bits that form a code bit vector on each line have the same base address; and extracting the memory access request type, base address, memory access granularity, and code bit vector of the collected memory access requests from the same address index table row to form the new memory access request.

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公开号 | 公开日

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CA2920528C|2020-09-22|

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CN104346285A|2015-02-11|

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EP3018588B1|2020-04-01|

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BR112016002568A2|2017-08-01|

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AU2014305469B2|2017-11-30|

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KR101844522B1|2018-04-02|

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KR20160040274A|2016-04-12|

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CA2920528A1|2015-02-12|

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US20160154590A1|2016-06-02|

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CN104346285B|2018-05-11|

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WO2015018290A1|2015-02-12|

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EP3018588A4|2016-12-07|

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EP3018588A1|2016-05-11|

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AU2014305469A1|2016-03-10|

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2020-03-03| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

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2021-10-26| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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