• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    1/1 hard macro having lock locations, integrated circuit including the same and method of routing through a hard macro. a hard macro (208, 308, 500) includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from top to bottom, the hard macro including a plurality of pathways (216, 318, 404) extending through the thickness of the rigid macro from the top to the bottom. also an integrated circuit (200, 300) having an upper layer (202, 302), a lower layer (210, 310) and at least one intermediate layer (206, 306), the upper layer (202, 302) including a dash upper layer conductor, middle layer including a rigid macro (208, 308) and the lower layer (210, 310) including a lower layer conductor trace, wherein the upper layer conductor trace is connected to the lower layer conductor trace by a pathway (216, 318, 404) that extends through the macrorigid (208, 308, 500).
    公开号:BR112015010159B1
    申请号:R112015010159-3
    申请日:2013-11-14
    公开日:2021-07-20
    发明作者:Kambiz Samadi；Shreepad A. Panth；Yang Du；Robert P. Gilmore
    申请人:Qualcomm Incorporated；
    IPC主号:
    专利说明:

    Cross Reference to Related Orders
    [0001] This patent application claims priority to Provisional Patent Application No. 61/726,031, entitled "HARD MACRO HAVING BLOCKAGE AREAS, INTEGRATED CIRCUIT INCLUDING SAME AND METHOD OF ROUTING THROUGH A HARD MACRO", filed on November 14, 2012 and assigned to this assignee and expressly incorporated herein by reference. Disclosure Field
    [0002] The present invention is directed to a rigid macro having blocking locations and a routing method through the rigid macro, and more specifically to a macro disk having a plurality of blocking locations in which it can be formed of pathways and for a method of routing an electrical connection through the rigid macro by pathways that form at blocking sites. Fundamentals
    [0003] "Macros" or "cores" are functional circuit elements or building blocks or logic units that can be used by chip manufacturers to create an application-specific integrated circuit (ASIC) or a programmable gate array in a hood (FPGA). Two common types of macros are referred to as "soft" and "hard" macros. Soft macros include logic for performing a particular function, along with various interconnect rules for connecting soft macro sub-portions and/or for connecting soft macro portions to other elements outside the soft macro. They can comprise, for example, a port-level netlist. Soft macros do not specify a physical cabling pattern and thus allow flexibility in the final physical implementation; however, due to the lack of a pre-specified physical cabling standard, it may need to be optimized for the desired performance and/or final layout in a plant. Rigid macros specify a fixed wiring pattern and are not modifiable. Hard macros are thus less flexible than soft macros but can be optimized for performance and physical layout before use.
    [0004] Hard and soft macros are used in two three-dimensional integrated circuits. However, it is increasingly common to stack multiple layers of integrated circuits and form three three-dimensional integrated circuits or "3D IC" to achieve higher device packing density, lower interconnect RC delay, and lower cost. The size and configuration of macros must be considered when planning to flatten a chip, especially a 3D IC. Soft macros can be modified to a degree and therefore it may sometimes be possible to allow connections from elements on a layer above the soft macro to elements on a layer below the soft macro to run through the soft macro. Difficult macros, however, have a fixed form factor, and it is often necessary to route the interlayer connections around them. This increases the length of various interconnects and may require the use of additional stores to compensate. Regions near the edges of hard macros can also become congested with conduction paths from elements above or below the hard macro that need to pass through the hard macro to reach another layer of the chip.
    [0005] Figure 1 shows a multilayer chip system 100 having a first layer 102 having a first circuit element 104, a second layer 106 having a rigid macro 108, and a third layer 110 having a second circuit element 112. The first circuit element 104 and/or second circuit element 112 alternately could represent pins or pads connecting with the multilayer chip 100 rather than actual circuit elements. The design of the chip 100 requires that the first circuit element 104 be connected to the second circuit element 112 located in the layer below the hard macro and two layers below the first circuit element 104. In order to make this connection, a path 114 is provided at a distance from the rigid macro 108, and the first circuit element 104 is connected to the path 114 through a first trace 116 and the second circuit element is connected to the path 114 through a second trace 118. If the macro rigid 108 were not present, a path may be provided directly below or closer to the first circuit element 104 or the second circuit element 112 to shorten the connection path between them. The presence of the rigid macro 108 in the second layer 106 between the first and second circuit elements 104, 112 increases the length of the connection between the first and second circuit elements 104, 112.
    [0006] In some cases, it may be possible to break a single large hard macro into two or more smaller hard macros and provide the necessary interconnection rules to allow the hard macros to communicate and operate as if they were a single hard macro. This arrangement, however, requires on-chip optimization and can lead to a decrease in chip performance. Therefore, it would be desirable to provide a hard macro that retains the benefits of the hard macros discussed above and that allows for greater flexibility in routing. SUMMARY
    [0007] The following summary is not a broad overview of all aspects covered. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that follows later.
    [0008] One aspect of the invention comprises a rigid macro having a periphery defining an area of rigid macro and having an upper and a lower portion and a thickness of rigid macro from the top to the bottom, the rigid macro including a plurality of pathways that extend through the thickness of the rigid macro from the top to the bottom.
    [0009] Another aspect of the invention comprises a non-volatile computer readable medium that stores instructions that, when executed by a computer, cause a computer-controlled device to create a hard macro having a periphery that defines a hard macro area and having an upper part and a lower part and a rigid macro thickness from the top to the bottom, and a plurality of pathways extending through the rigid macro from the top to the bottom.
    [0010] A further aspect of the invention comprises a rigid macro with a periphery defining a rigid macro area and having an upper and a lower portion and a rigid macro thickness from the top to the bottom. Hard macro includes a regular pattern of lock locations at the top of the hard macro, the lock locations extend through the hard macro from the top to the bottom.
    [0011] Yet another aspect of the invention comprises a non-volatile computer readable medium that stores instructions that, when executed by a computer, cause a computer-controlled device to create a hard macro with a periphery that defines a hard macro area. and having a top and a bottom and a hard macro thickness from the top to the bottom, and a regular pattern of lock locations over the top of the hard macro, the lock locations that extend through the hard macro to from top to bottom.
    [0012] Yet another aspect of the invention comprises an integrated circuit, including an upper layer, a lower layer and at least one middle layer, the upper layer including an upper layer conductive trace, the intermediate layer including a rigid macro and the lower layer including a lower layer conductive trace. The upper-layer leader trace is connected to the lower-layer leader trace by a pathway that extends through the rigid macro.
    [0013] Another aspect of the invention comprises a non-volatile computer-readable medium that stores instructions that, when executed by a computer, cause a computer-controlled device to create an integrated circuit that has a top layer, a bottom layer, and a minus one intermediate layer, the top layer including an upper layer conductive trace, the intermediate layer including a rigid macro, and the bottom layer including a lower layer conductive trace. The upper-layer leader trace is connected to the lower-layer leader trace by a pathway that extends through the rigid macro.
    [0014] Another aspect of the invention comprises a method including forming a first layer of an integrated circuit, forming a second layer of an integrated circuit on the first layer of an integrated circuit, the second layer including at least one rigid macro, forming at least one pathway through the rigid macro, forming a third layer on top of the second layer, and electrically connecting an element on the first layer to an element on the third layer using the at least one pathway.
    [0015] Yet another aspect of the invention comprises an integrated circuit comprising an upper layer, a lower layer and at least one intermediate layer, the upper layer including an upper layer conductive trace, the intermediate layer including rigid macro means form that performs an operation and the lower layer including a lower layer tracer. The upper-layer leader trace is connected to the lower-layer leader trace by rigid macro means.
    [0016] Another aspect of the disclosure further comprises a method including the steps of forming a first layer of an integrated circuit, steps for forming a second layer of an integrated circuit on the first layer of an integrated circuit, the second layer includes by the minus a rigid macro, steps for forming a pathway through the rigid macro, steps for forming a third layer on top of the second layer, and steps for electrically connecting an element over the first layer of an element in the third layer using the pathway . BRIEF DESCRIPTION OF THE DRAWINGS
    [0017] The attached drawings found in the annexes are presented to assist in describing embodiments of the invention and are provided for illustrative embodiments only and not as a limitation thereof.
    [0018] Figure 1 is a schematic cross-sectional side elevation view of a conventional multilevel chip having a hard macro in a central layer and showing the routing required to connect the elements above and below the hard macro.
    [0019] Figure 2 is a schematic cross-sectional side elevation view of a multilevel chip according to the present disclosure having a rigid macro with at least one pathway formed therethrough and showing a first connection path through the rigid macro.
    [0020] Figure 3 is a schematic cross-sectional side elevation view of a multilevel chip in accordance with the present disclosure having a rigid macro and showing a first connection path through a locking location in the rigid macro.
    [0021] Figure 4 is a schematic cross-sectional side elevation view of the multilevel chip of Figure 3, showing an alternative connection path through another locking location in the rigid macro.
    [0022] Figure 5 is a schematic plan view of a rigid macro showing a first arrangement of locking locations in which tracks can be formed.
    [0023] Figure 6 is a schematic diagram of an exemplary wireless communication system where embodiments of the disclosure may be used.
    [0024] Figure 7 is a flowchart illustrating a method in accordance with the present disclosure. DETAILED DESCRIPTION
    [0025] Aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternative modalities can be conceived without departing from the scope of the invention. Furthermore, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant data of the invention.
    [0026] The word "exemplary" is used here to mean "to serve as an example, case, or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the discussed mode of operation, feature, or advantage.
    [0027] The terminology used herein is only for the purpose of describing specific examples according to embodiments, and is not intended to be limiting of embodiments of the invention. As used herein, the singular forms "a", "an" and "a/o" are intended to include the plural forms, too, unless the context clearly indicates otherwise. As used herein, the terms "comprises", "comprising", "includes" and/or "including" specify the presence of indicated structural and functional characteristics, steps, operations, elements and/or components, but do not exclude the presence or addition of one or more other structural and functional characteristics, steps, operations, elements, components and/or groups thereof.
    [0028] Spatially related terms such as "under", "below", "bottom", "across", "top", "side", "top", "bottom", "left", "right" and the like , may be used herein for ease of description to describe an element or feature in relation to another element or feature as illustrated in the figures. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the apparatus in the figures is inverted, the elements depicted as "under" or "under" other elements or features would then be oriented "across" the other elements or features. The device may be oriented otherwise (rotated by 90 degrees or in other orientations) and the relative spatial relationship descriptors used herein are interpreted accordingly.
    [0029] Those skilled in the art will appreciate that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, commands, instructions, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields, spin particles electrons, electrospins, or any combination thereof.
    [0030] The term "topology" as used herein refers to the interconnection of circuit components and, unless otherwise indicated, does not indicate anything of the physical arrangement of the components or their physical locations relative to others. Figures depicted or otherwise identified as presenting a topology are no more than a graphical representation of the topology and do not necessarily describe anything about physical layout or relative locations of components.
    [0031] Figure 2 illustrates a multilayer chip 200 having a first layer 202, which has a first circuit element 204, a second layer 206 having a rigid macro 208, and a third layer 210 having a second circuit element 212. First circuit element 204 and/or second circuit element 212 alternately could represent pins or connector pads for multilayer chip 200 rather than actual circuit elements. The design of the multilayer chip 200 requires that the first circuit element 204 be connected to the second circuit element 212 located in the layer below the rigid macro 208 and two layers below the first circuit element 204. The rigid macro 208 is provided with at least one and preferably a plurality of locking locations 214 which are formed without logic elements or connections and wherein at locking locations 214 pathways 216 can be formed without adversely affecting the operation of rigid macro 208. In Figure 2, three locking locations 214 are illustrated; however, a greater or lesser number of locking locations 214 may be provided on the chip 200. Instead of routing a connection from the first circuit element 204 to the second circuit element 212 around the edge of the rigid macro 208 , a pathway 216 is formed at one of the locking locations 214 to provide a lower connecting path from the first circuit element 204 to the second circuit element 212. The locking locations 214 extend linearly through the rigid macro 208.
    [0032] Figures 3 and 4 illustrate a multilayer chip 300 having a first layer 302 with a first circuit element 304, a second layer 306 having a rigid macro 308, and a third layer 310 having a second circuit element 312. First circuit element 304 and/or second circuit element 312 alternately could represent pins or connector pads for multilayer chip 300 rather than actual circuit elements. The design of the multilayer chip 300 requires that the first circuit element 304 be connected to the second circuit element 312 located in the layer below the rigid macro 308 and two layers below the first circuit element 304. The rigid macro 308 is provided with at least one and preferably a plurality of locking locations 314 which are formed without logic elements or connections and wherein at locking locations 314 pathways 318 can be formed without adversely affecting the operation of rigid macro 308. Only two locking locations 314 are found. illustrated in Figs. 3 and 4, but a larger number can generally be provided. Unlike the multilayer chip 200 of Figure 2, the blocking chip locations 314 to 300 are offset horizontally from at least one element of the first circuit 304 and the second circuit element 312. However, even with such offsets, the connection of the first circuit element 304 to second circuit element 312 is shorter than prior art connections, which would need routing completely around rigid macro 308.
    [0033] Figure 3 shows a first connection route 316 that connects the first circuit element 304 to the second circuit element 312 via a pathway 318 at one of the locking locations 314 to close the first circuit element 304. Figure 4 shows a second connection route 402 connecting the first circuit element 304 to the second circuit element 312 via a way 404 formed at the blocking location 314 closest to the second circuit element 312. Which of these two ways is selected for track placement may depend on the other connections to and between the first and second circuit elements 304, 312 and/or the other circuit elements (not shown) and/or other electrical paths (not shown) on the first, second and third layers 302, 306 and 310.
    [0034] It may be possible to design a rigid macro with the lockout locations located at predetermined locations based on the final desired design of the 3D integrated circuit and the various elements it will contain. However, it may be more practical to provide a relatively large number of lockout locations in the rigid macro to provide flexibility for circuit designers who can place tracks at as few or as many of the lockout locations as needed when establishing circuit interconnects. Referring to Figure 5, rigid macro 500 includes a plurality of locking locations 502 arranged in a regular pattern having a constant spacing therebetween in the X and Y directions, a mesh or a matrix of rows and columns in the present case. The regular pattern could alternately be evenly spaced in one direction only or be arranged in a zigzag or non-rectangular pattern. The locations of the blocking sites can also be arranged in an irregular pattern. It should be noted that blocking locations take up very little space and only need to be large enough to accommodate multiple lanes. The pathways are so small that some can form even in very small areas of blockage. The size of lock locations in relation to rigid macros and circuit elements are greatly exaggerated in the drawings.
    [0035] It is unlikely that a circuit designer will finally form a road at each of these blocking locations. It is also unlikely that elements requiring interconnection will be located directly above and below the lockout location and such that they can be connected by a single vertical electrical connection. However, the large number of lock locations spread across the hard macro surface provides improved routing flexibility and reduces the need to route around the edge of a hard macro, instead providing multiple paths through the hard macro that can be used as needed.
    [0036] Locations for lock locations are determined, in part, based on block-by-block pin statistics from the block-level project netlist. Based on relevant design rules (including via interlayer / landing pad pitch, etc.) and block-by-block pin statistics the available area for blocking locations is calculated. Given the allowable area overhead budget (which is minimal due to extremely small sizes of monolithic 3D interlayer roads) the number of blocking locations in the entire block can be determined. After lock insertion, the modified block is done through physical execution, eg positioning and routing ("Q&A").
    [0037] Figure 6 illustrates an exemplary wireless communication system 600 in which one or more embodiments of the present description may be advantageously employed. For purposes of illustration, Figure 6 shows three remote units 620, 630 and 650, and two base stations 640. It will be recognized that conventional wireless communication systems can have many more remote units and base stations. Remote units 620, 630 and 650 include integrated circuits or other semiconductor devices 625, 635 and 655 (including hard macros as disclosed herein), which are among embodiments of the present description, as discussed further below. Figure 6 shows forward link signals 680 from base stations 640 and remote units 620, 630, and 650 and 690 reverse link signals from remote units 620, 630, and 650 to base stations 640.
    [0038] In Figure 6, remote unit 620 is shown as a mobile phone, remote unit 630 is shown as a portable computer, and remote unit 650 is shown as a fixed local remote unit in a wireless local loop system. . For example, the remote units can be any or a combination of a cell phone, portable personal communication system unit (PCS), portable data unit such as a personal data assistant (PDA), navigation device ( such as GPS enabled devices), set top box, music player, video player, entertainment device, fixed location data unit, such as meter reading equipment, or any other device that stores and retrieves instruction data or computer, or any combination of these. While Figure 6 illustrates remote units in accordance with the teachings of the present description, this disclosure is not limited to these exemplary illustrated units. Disclosure modalities can be suitably employed in any device with an active integrated circuit, including memory and on-chip circuitry for testing and characterization.
    [0039] A method according to an embodiment comprises a block 702 of forming a first layer of an integrated circuit, a block 704 of forming a second layer of an integrated circuit on the first layer of an integrated circuit, the second layer includes by the minus a rigid macro, a block 706 of forming a way through the rigid macro, a block 708 of forming a third layer on top of the second layer, and an electrical connection block 710 of an element on the first layer of an element in the third layer using the pathway.
    [0040] Previously disclosed devices and functionalities (such as the devices of figures 2-5, or any combination thereof) can be designed and configured in computer files (e.g., RTL, GDSII, Gerber, etc.) stored in media computer readable. Some or all of these files can be provided to manufacturing operators who manufacture devices based on such files. The resulting products include semiconductor chips which are then cut into semiconductor arrays and packaged onto a semiconductor chip. Semiconductor chips can be employed in electronic devices such as described herein above.
    [0041] The methods, sequences and/or algorithms described in connection with the modalities described herein can be incorporated directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium can be an integral part of the processor.
    [0042] Accordingly, an embodiment of the invention may include a computer-readable medium that contains a method for the application. Therefore, the invention is not limited to the illustrated examples and any means for realizing the functionality described herein are included in embodiments of the invention.
    [0043] Although the foregoing description shows illustrative embodiments of the invention, it should be noted that various changes and modifications can be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims according to the embodiments of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
    权利要求:
    Claims (6)
    [0001]
    1. Integrated circuit characterized in that it comprises an upper layer, a lower layer and at least one intermediate layer, the upper layer including an upper layer conductive trace, the at least one intermediate layer including a rigid macro and the lower layer including a lower layer tracer, wherein the upper layer tracer is connected to the lower layer tracer by a plurality of pathways extending through the rigid macro, the rigid macro including a plurality of blocking locations at the top of the rigid macro, the locking sites extending through the rigid macro, where the plurality of pathways are formed in at least some of the locking locations, where the locking locations are formed without logical elements or connections, and in which locking pathways locking sites are formed without adversely affecting rigid macro operation, and additionally where the locking sites extend li nearly through the rigid macro.
    [0002]
    2. Integrated circuit according to claim 1, characterized in that the upper layer includes an upper layer active element and the lower layer includes a lower layer active element and wherein the upper layer active element is connected to the active element of lower layer by way.
    [0003]
    3. Integrated circuit, according to claim 1 or 2, characterized in that it is integrated in at least one semiconductor chip.
    [0004]
    4. Device characterized in that it is selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal assistant digital, PDA, a fixed location data unit, and a computer including the integrated circuit as defined in claim 1 or 2.
    [0005]
    5. Method characterized in that it comprises: forming a first layer of an integrated circuit; forming a second integrated circuit layer on top of the first integrated circuit layer, the second layer including at least one rigid macro; form at least one pathway through the rigid macro; forming a third layer on top of the second layer; and electrically connecting an element on the first layer to an element on the third layer using the at least one pathway, wherein the rigid macro includes a plurality of locking locations and wherein forming the at least one pathway comprises forming the at least one via in one or more of the plurality of locking locations, where the locking locations are formed without logical elements or connections and in which locking location pathways are formed without adversely affecting the operation of the rigid macro, and additionally in that lock locations extend linearly across the rigid macro.
    [0006]
    6. Computer-readable memory characterized in that it comprises instructions stored therein, the instructions being computer-executable to carry out the method steps as defined in claim 5.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    JPH0964190A|1995-08-28|1997-03-07|Oki Electric Ind Co Ltd|Automatic wiring method for macro circuitry of lsi of embedded array system|
    JPH09172072A|1995-12-18|1997-06-30|Nec Corp|Semiconductor device and its manufacture|
    JPH1167923A|1997-08-25|1999-03-09|Nec Corp|Semiconductor integrated circuit, wiring routing method thereof and recording medium recording the method|
    US6543040B1|2000-03-15|2003-04-01|International Business Machines Corporation|Macro design techniques to accommodate chip level wiring and circuit placement across the macro|
    JP4063796B2|2004-06-30|2008-03-19|日本電気株式会社|Multilayer semiconductor device|
    US7334206B2|2004-12-13|2008-02-19|Lsi Logic Corporation|Cell builder for different layer stacks|
    JP2009015491A|2007-07-03|2009-01-22|Nec Electronics Corp|Layout design method for semiconductor integrated circuit|
    US8558320B2|2009-12-15|2013-10-15|Qualcomm Incorporated|Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior|
    US8775998B2|2010-12-09|2014-07-08|Panasonic Corporation|Support device of three-dimensional integrated circuit and method thereof|
    US10192813B2|2012-11-14|2019-01-29|Qualcomm Incorporated|Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro|US6245166B1|1997-07-02|2001-06-12|Mabuchi Motor Co., Ltd|Material for sliding contact, composite clad material, and small-sized direct current motor using the same|
    US8058137B1|2009-04-14|2011-11-15|Monolithic 3D Inc.|Method for fabrication of a semiconductor device and structure|
    US11211279B2|2010-11-18|2021-12-28|Monolithic 3D Inc.|Method for processing a 3D integrated circuit and structure|
    US11018042B1|2010-11-18|2021-05-25|Monolithic 3D Inc.|3D semiconductor memory device and structure|
    US11121021B2|2010-11-18|2021-09-14|Monolithic 3D Inc.|3D semiconductor device and structure|
    US9509313B2|2009-04-14|2016-11-29|Monolithic 3D Inc.|3D semiconductor device|
    US9385088B2|2009-10-12|2016-07-05|Monolithic 3D Inc.|3D semiconductor device and structure|
    US11004719B1|2010-11-18|2021-05-11|Monolithic 3D Inc.|Methods for producing a 3D semiconductor memory device and structure|
    US10354995B2|2009-10-12|2019-07-16|Monolithic 3D Inc.|Semiconductor memory device and structure|
    US11164770B1|2010-11-18|2021-11-02|Monolithic 3D Inc.|Method for producing a 3D semiconductor memory device and structure|
    US10043781B2|2009-10-12|2018-08-07|Monolithic 3D Inc.|3D semiconductor device and structure|
    US11094576B1|2010-11-18|2021-08-17|Monolithic 3D Inc.|Methods for producing a 3D semiconductor memory device and structure|
    US10366970B2|2009-10-12|2019-07-30|Monolithic 3D Inc.|3D semiconductor device and structure|
    US11018133B2|2009-10-12|2021-05-25|Monolithic 3D Inc.|3D integrated circuit|
    US10157909B2|2009-10-12|2018-12-18|Monolithic 3D Inc.|3D semiconductor device and structure|
    US10388863B2|2009-10-12|2019-08-20|Monolithic 3D Inc.|3D memory device and structure|
    US10910364B2|2009-10-12|2021-02-02|Monolitaic 3D Inc.|3D semiconductor device|
    US11107721B2|2010-11-18|2021-08-31|Monolithic 3D Inc.|3D semiconductor device and structure with NAND logic|
    US9099526B2|2010-02-16|2015-08-04|Monolithic 3D Inc.|Integrated circuit device and structure|
    US8395191B2|2009-10-12|2013-03-12|Monolithic 3D Inc.|Semiconductor device and structure|
    US11031275B2|2010-11-18|2021-06-08|Monolithic 3D Inc.|3D semiconductor device and structure with memory|
    US10497713B2|2010-11-18|2019-12-03|Monolithic 3D Inc.|3D semiconductor memory device and structure|
    US8669778B1|2009-04-14|2014-03-11|Monolithic 3D Inc.|Method for design and manufacturing of a 3D semiconductor device|
    US10388568B2|2011-06-28|2019-08-20|Monolithic 3D Inc.|3D semiconductor device and system|
    US9953925B2|2011-06-28|2018-04-24|Monolithic 3D Inc.|Semiconductor system and device|
    US10217667B2|2011-06-28|2019-02-26|Monolithic 3D Inc.|3D semiconductor device, fabrication method and system|
    US11018191B1|2010-10-11|2021-05-25|Monolithic 3D Inc.|3D semiconductor device and structure|
    US11227897B2|2010-10-11|2022-01-18|Monolithic 3D Inc.|Method for producing a 3D semiconductor memory device and structure|
    US11024673B1|2010-10-11|2021-06-01|Monolithic 3D Inc.|3D semiconductor device and structure|
    US11257867B1|2010-10-11|2022-02-22|Monolithic 3D Inc.|3D semiconductor device and structure with oxide bonds|
    US8026521B1|2010-10-11|2011-09-27|Monolithic 3D Inc.|Semiconductor device and structure|
    US10896931B1|2010-10-11|2021-01-19|Monolithic 3D Inc.|3D semiconductor device and structure|
    US10290682B2|2010-10-11|2019-05-14|Monolithic 3D Inc.|3D IC semiconductor device and structure with stacked memory|
    US11158674B2|2010-10-11|2021-10-26|Monolithic 3D Inc.|Method to produce a 3D semiconductor device and structure|
    US11133344B2|2010-10-13|2021-09-28|Monolithic 3D Inc.|Multilevel semiconductor device and structure with image sensors|
    US10978501B1|2010-10-13|2021-04-13|Monolithic 3D Inc.|Multilevel semiconductor device and structure with waveguides|
    US11164898B2|2010-10-13|2021-11-02|Monolithic 3D Inc.|Multilevel semiconductor device and structure|
    US11063071B1|2010-10-13|2021-07-13|Monolithic 3D Inc.|Multilevel semiconductor device and structure with waveguides|
    US8163581B1|2010-10-13|2012-04-24|Monolith IC 3D|Semiconductor and optoelectronic devices|
    US11163112B2|2010-10-13|2021-11-02|Monolithic 3D Inc.|Multilevel semiconductor device and structure with electromagnetic modulators|
    US10679977B2|2010-10-13|2020-06-09|Monolithic 3D Inc.|3D microdisplay device and structure|
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    US11043523B1|2010-10-13|2021-06-22|Monolithic 3D Inc.|Multilevel semiconductor device and structure with image sensors|
    US10998374B1|2010-10-13|2021-05-04|Monolithic 3D Inc.|Multilevel semiconductor device and structure|
    US10943934B2|2010-10-13|2021-03-09|Monolithic 3D Inc.|Multilevel semiconductor device and structure|
    US9099424B1|2012-08-10|2015-08-04|Monolithic 3D Inc.|Semiconductor system, device and structure with heat removal|
    US8557632B1|2012-04-09|2013-10-15|Monolithic 3D Inc.|Method for fabrication of a semiconductor device and structure|
    US10600888B2|2012-04-09|2020-03-24|Monolithic 3D Inc.|3D semiconductor device|
    US11164811B2|2012-04-09|2021-11-02|Monolithic 3D Inc.|3D semiconductor device with isolation layers and oxide-to-oxide bonding|
    US11088050B2|2012-04-09|2021-08-10|Monolithic 3D Inc.|3D semiconductor device with isolation layers|
    US10192813B2|2012-11-14|2019-01-29|Qualcomm Incorporated|Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro|
    US11063024B1|2012-12-22|2021-07-13|Monlithic 3D Inc.|Method to form a 3D semiconductor device and structure|
    US8674470B1|2012-12-22|2014-03-18|Monolithic 3D Inc.|Semiconductor device and structure|
    US11018116B2|2012-12-22|2021-05-25|Monolithic 3D Inc.|Method to form a 3D semiconductor device and structure|
    US11217565B2|2012-12-22|2022-01-04|Monolithic 3D Inc.|Method to form a 3D semiconductor device and structure|
    US11177140B2|2012-12-29|2021-11-16|Monolithic 3D Inc.|3D semiconductor device and structure|
    US10892169B2|2012-12-29|2021-01-12|Monolithic 3D Inc.|3D semiconductor device and structure|
    US10651054B2|2012-12-29|2020-05-12|Monolithic 3D Inc.|3D semiconductor device and structure|
    US9385058B1|2012-12-29|2016-07-05|Monolithic 3D Inc.|Semiconductor device and structure|
    US11004694B1|2012-12-29|2021-05-11|Monolithic 3D Inc.|3D semiconductor device and structure|
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    US11087995B1|2012-12-29|2021-08-10|Monolithic 3D Inc.|3D semiconductor device and structure|
    US9871034B1|2012-12-29|2018-01-16|Monolithic 3D Inc.|Semiconductor device and structure|
    US10600657B2|2012-12-29|2020-03-24|Monolithic 3D Inc|3D semiconductor device and structure|
    US10903089B1|2012-12-29|2021-01-26|Monolithic 3D Inc.|3D semiconductor device and structure|
    US8902663B1|2013-03-11|2014-12-02|Monolithic 3D Inc.|Method of maintaining a memory state|
    US10325651B2|2013-03-11|2019-06-18|Monolithic 3D Inc.|3D semiconductor device with stacked memory|
    US8994404B1|2013-03-12|2015-03-31|Monolithic 3D Inc.|Semiconductor device and structure|
    US11107808B1|2014-01-28|2021-08-31|Monolithic 3D Inc.|3D semiconductor device and structure|
    US11031394B1|2014-01-28|2021-06-08|Monolithic 3D Inc.|3D semiconductor device and structure|
    US9117749B1|2013-03-15|2015-08-25|Monolithic 3D Inc.|Semiconductor device and structure|
    US10224279B2|2013-03-15|2019-03-05|Monolithic 3D Inc.|Semiconductor device and structure|
    US11030371B2|2013-04-15|2021-06-08|Monolithic 3D Inc.|Automation for monolithic 3D devices|
    US9021414B1|2013-04-15|2015-04-28|Monolithic 3D Inc.|Automation for monolithic 3D devices|
    US11270055B1|2013-04-15|2022-03-08|Monolithic 3D Inc.|Automation for monolithic 3D devices|
    US10840239B2|2014-08-26|2020-11-17|Monolithic 3D Inc.|3D semiconductor device and structure|
    US11088130B2|2014-01-28|2021-08-10|Monolithic 3D Inc.|3D semiconductor device and structure|
    US10297586B2|2015-03-09|2019-05-21|Monolithic 3D Inc.|Methods for processing a 3D semiconductor device|
    US11056468B1|2015-04-19|2021-07-06|Monolithic 3D Inc.|3D semiconductor device and structure|
    US10825779B2|2015-04-19|2020-11-03|Monolithic 3D Inc.|3D semiconductor device and structure|
    US11011507B1|2015-04-19|2021-05-18|Monolithic 3D Inc.|3D semiconductor device and structure|
    US10381328B2|2015-04-19|2019-08-13|Monolithic 3D Inc.|Semiconductor device and structure|
    CN108401468A|2015-09-21|2018-08-14|莫诺利特斯3D有限公司|3D semiconductor devices and structure|
    US10522225B1|2015-10-02|2019-12-31|Monolithic 3D Inc.|Semiconductor device with non-volatile memory|
    US10847540B2|2015-10-24|2020-11-24|Monolithic 3D Inc.|3D semiconductor memory device and structure|
    US11114464B2|2015-10-24|2021-09-07|Monolithic 3D Inc.|3D semiconductor device and structure|
    US10418369B2|2015-10-24|2019-09-17|Monolithic 3D Inc.|Multi-level semiconductor memory device and structure|
    US11114427B2|2015-11-07|2021-09-07|Monolithic 3D Inc.|3D semiconductor processor and memory device and structure|
    US11251149B2|2016-10-10|2022-02-15|Monolithic 3D Inc.|3D memory device and structure|
    US10719654B2|2017-11-28|2020-07-21|International Business Machines Corporation|Placement and timing aware wire tagging|
    US11018156B2|2019-04-08|2021-05-25|Monolithic 3D Inc.|3D memory semiconductor devices and structures|
    US11158652B1|2019-04-08|2021-10-26|Monolithic 3D Inc.|3D memory semiconductor devices and structures|
    US10892016B1|2019-04-08|2021-01-12|Monolithic 3D Inc.|3D memory semiconductor devices and structures|
    法律状态:
    2020-01-21| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-11-03| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2021-05-11| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2021-05-11| B15K| Others concerning applications: alteration of classification|Free format text: A CLASSIFICACAO ANTERIOR ERA: G06F 17/50 Ipc: G06F 30/39 (2020.01), H01L 23/498 (2006.01), H01L |
    2021-07-20| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 14/11/2013, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US201261726031P| true| 2012-11-14|2012-11-14|
    US61/726,031|2012-11-14|
    US13/753,193|US10192813B2|2012-11-14|2013-01-29|Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro|
    US13/753,193|2013-01-29|
    PCT/US2013/070014|WO2014078487A1|2012-11-14|2013-11-14|Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro|
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