巴西专利BR102012021854B1 APPARATUS FOR THE CONTROL OF AN EXTERNAL INTERFACE IN AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT, MET

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专利摘要:
high property command waiting for peripheral component. in one embodiment, a peripheral component can include a low priority command wait configured to store a set of commands for executing a transfer on the peripheral interface and a high priority command wait configured to store a second set of commands for performing a transfer on the interface. commands in low priority waiting may include indications that identify points at which the command set can be interrupted for the execution of the second set of commands. a control circuit can be coupled to the low priority command waiting and can interrupt the processing of commands from the low priority waiting that responds to the indications, and can process the commands from the high priority command waiting.
公开号:BR102012021854B1
申请号:R102012021854-2
申请日:2012-08-30
公开日:2020-09-15
发明作者:Diarmuid P. Ross；Douglas C. Lee
申请人:Apple Inc；
IPC主号:

专利说明:

BACKGROUND Field of the invention
[001] This invention relates to the field of integrated circuits and, more particularly, to command processing in a peripheral component in an integrated circuit. Description of the Related Art
[002] In a peripheral interface controller that has significant data bandwidth, one of the challenges that can occur is the supply of control input to the peripheral interface controller from an external processor. Typically, the same internal interface as the peripheral controller that transfers data between the peripheral interface controller and memory is used to provide control input from the external processor (for example, through a series of scripts for controlling records in the peripheral interface controller). While data transfer takes place, the memory of the peripheral interface can be saturated with data transfer. Accordingly, the control inputs for the disposition of the next data transfer group can be effectively locked out until the current data transfer is completed. During the time that the control inputs are being provided, the external peripheral interface controlled by the peripheral interface controller can be inactive.
[003] A mechanism for reducing the peripheral contention of the memory interface is the inclusion of the processor in the peripheral interface controller, which executes a program for the control of the peripheral interface controller hardware. However, such a mechanism is expensive in several ways: in monetary terms for the acquisition of the processor (either as a discrete component or as an intellectual property that can be incorporated into the design of the peripheral interface controller); in terms of space occupied by the peripheral interface controller when the processor is included; and in terms of energy consumed by the processor. In addition, the program to be executed is stored in the system memory, so that the instruction can compete with the transfer of data on the periphery of the memory interface.
[004] Additionally, it is complicated to interrupt one of the data transfers for the execution of another, in the case of the need for more important execution (or with a higher priority), the data transfer is identified after the given data transfer has been started. SUMMARY
[005] In one embodiment, an integrated circuit includes a peripheral component configured to control an external interface of the integrated circuit. For example, the peripheral component can be the memory interface unit as well as a flash memory interface unit. The internal interface of the peripheral component can be shared between the transfer of data to / from the external interface and control communications of the peripheral component. The peripheral component can include a low priority command queue configured to store a set of commands for executing a transfer on the interface. In addition, the peripheral component can include a high priority command queue configured to store a second set of commands for performing an interface transfer. The commands in the low priority queue can include indications that identify points at which the command set can be interrupted for the execution of the second command set. A control circuit can be attached to the low priority command queue and can read the commands and communicate with the interface controller to cause the transfer on the interface that responds to the commands. In addition, the control circuit can interrupt the processing of commands from the low priority queue that responds to the indications, and can process commands from the high priority command queue.
[006] In one mode, the high priority transfer represented by the second set of commands can be executed more quickly than if it was necessary to empty the low priority queue first. In addition, by interrupting the low priority transfer at a point that could be interrupted, the low priority transfer can be resumed when the high priority transfer has been completed. The processing that takes place before the high priority transfer may have been completed correctly and does not need to be repeated. BRIEF DESCRIPTION OF THE DRAWINGS
[007] The following detailed description refers to the attached drawings, which are now briefly described.
[008] Figure 1 is a block diagram of a modality of an integrated circuit, a memory, and a flash memory.
[009] Figure 2 is a block diagram of a modality of a flash memory interface illustrated in figure 1.
[0010] Figure 3 is a flowchart that illustrates the operation of a modality of a flash memory interface control circuit illustrated in figure 2 in response to receiving a written operation.
[0011] Figure 4 is a table that illustrates a modality of the commands supported by the flash memory interface control circuit.
[0012] Figure 5 is a flow chart illustrating the operation of a flash memory interface control circuit shown in figure 2 in response to reading a command from the first-in and first-low command isolator out (FIFO).
[0013] Figure 6 is a flow chart illustrating the operation of a flash memory interface control circuit shown in Figure 2 in response to reading a command from the first-in-first and first-in-command isolator out (FIFO).
[0014] Figure 7 is a block diagram of an exemplary use of a macro memory.
[0015] Figure 8 is a flow chart that illustrates the operation of a flash memory interface code mode performed by the processor mode shown in figure 1.
[0016] Figure 9 is a block diagram of a modality of a system that includes the apparatus illustrated in figure 1.
[0017] Figure 10 is a block diagram of a modality of a storage medium accessible by computer.
[0018] While the invention is susceptible to several modifications and alternative forms, the specific modalities of it are shown by way of example in the drawings and will be described in detail here. It must be understood, however, that the drawings and their detailed description are not intended to limit the invention to the particular form presented, but on the contrary, the intention is to cover all modifications, equivalents and alternatives included within the essence and scope of the present invention, as defined by the embodiments. The headings used here are for organizational purposes only and are not intended to be used as limiting the scope of the description. As used throughout this patent application, the word "can" is used in a permissive sense (that is, it means that it has the potential for), rather than a mandatory sense (that is, meaning must). Similarly, the words "includes", "including", and "including" mean included, but not limited to.
[0019] Several units, circuits, or other components can be described as "configured for the" execution of a task or tasks. In such contexts, "configured for" is a broad structure quote which generally means "that has circuits that" perform the task or tasks during the operation. As such, the unit / circuit / component can be configured to perform the task even when the unit / circuit / component is not currently active. In general, the circuits that form the structure that corresponds to the "configured for" may include executable hardware circuits and / or memory storage program instructions for the use of the operation. The memory may include volatile memory, such as static or dynamic random access memory and / or non-volatile memory such as optical or magnetic disk storage, flash memory, programmable read-only memories, etc. Similarly, several units / circuits / components can be described as executing a task or tasks, for the convenience of description. Such descriptions should be interpreted as including the phrase "configured for." The citation of a unit / circuit / component that is configured to perform one or more tasks is expressly not intended to invoke the interpretation of paragraph 6 of document 35 U.S.C. § 112, for this unit / circuit / component. DETAILED DESCRIPTION OF THE MODALITIES
[0020] In focus now on figure 1, a block diagram of an integrated circuit modality 10 coupled to an external memory 12 and one or more flash memory devices 28A and 28B are shown. In the illustrated embodiment, integrated circuit 10 includes a memory controller 14, an interconnectable mesh 16, a set of peripheral components such as components 18A and 18B, a flash memory interface unit 30, a central DMA controller (CDMA) 20 , a processor 22 that includes a level 1 (L1) cache 24, a level 2 (L2) cache 26, and an input / output (I / O) processor (IOP) 32. Memory controller 14 is coupled to a memory interface to which memory 12 can be coupled, and is coupled to interconnectable mesh 16. CDMA Controller 20, L2 cache 26, and processor 22 (through cache 26 of L2) are also coupled to the interconnectable mesh 16 in the illustrated mode. The L2 cache is coupled to processor 22, and the CDMA controller 20 is coupled to components 18A through 18B, the flash memory interface unit 30, and IOP 32. One or more peripheral components 18A and 18B can be coupled to external interfaces as well, like the peripheral component 18A. In other embodiments, other components can be coupled to the interconnectable mesh 16 directly (for example, other peripheral components).
[0021] The CDMA controller 20 can be configured to perform DMA operations between memory 12, several peripheral components 18A to 18B, and / or the flash memory interface unit 30. Various modalities can include any amount of component peripherals and / or flash memory interface unit 30 coupled via the CDMA 20 controller. Processor 22 (and more particularly, instructions executed by processor 22) can program CDMA controller 20 to perform DMA Operations. Several modes can program the CDMA 20 controller in several ways. For example, DMA Descriptors can be written in memory 12, describing the DMA operations to be performed, and the CDMA controller 20 can include records that are programmable for the location of DMA descriptors in memory 12. Multiple descriptors can be created by a DMA channel, and the DMA operations described in the descriptors can be performed as specified. Alternatively, the CDMA 20 controller can include records that are programmable to describe the DMA operations to be performed, and the CDMA 20 controller programming may include records writings.
[0022] In general, a DMA operation can be a transfer of data from a source to a target that is performed by hardware separate from a processor that executes instructions. The hardware can be programmed using instructions executed by the processor, but the transfer itself is performed by the hardware regardless of the instruction execution on the processor. At least one of the sources and the target may be a memory. The memory can be system memory (e.g., memory 12), flash memory devices 28A and 28B, or it can be internal memory within integrated circuit 10, in some embodiments. Some DMA operations can have memory as a source and target (for example, a DMA operation between memory 12 and flash memory devices 28A and 28B, or a copy operation from memory block 12 to the other). Other DMA operations can have a peripheral component as a source or target. The peripheral component can be coupled to an external interface on which the DMA data must be transferred or on which the DMA data is received. For example, peripheral component 18A can be coupled to an interface on which DMA data must be transferred or on which DMA data must be received. In this way, a DMA operation can include the read data from the CDMA controller 20 from the source and write data from the destination. Data can flow through the CDMA 20 controller as part of the DMA operation. In particular, DMA data for a DMA reading from memory 12 can flow through memory controller 14, over interconnectable loop 16, through CDMA controller 20, to peripheral component 18A and 18B or the interface unit flash memory 30 (and possibly over the interface to which the peripheral component is attached, if applicable). The data for a DMA write to memory can flow in the opposite direction.
[0023] In one embodiment, the instructions executed by processor 22 and / or IOP 32 can also communicate with peripheral components 18A through 18B and the flash memory interface unit 30 using read and / or writing calls for scheduled input / output operations (PIO). PIO operations can have an address that is mapped by integrated circuit 10 to a peripheral component 18A and 18B or the flash memory interface unit 30 (and, more particularly, to a register or other readable / writable resource on the component ). The address mapping can be fixed in the address space, or it can be programmable. Alternatively, the PIO operation can be transmitted in a way that is distinguishable from memory read / write operations (for example using a different command that encodes memory read / write operations on the interconnectable mesh 16, using a sideband signal or control signal for the indication of memory vs. PIO, etc.). The PIO transmission may further include the address, which may identify peripheral component 18A and 18B or flash memory interface unit 30 (and the addressed resource) within a PIO address space, for such uses. The addressed resource can be any resource within the addressed component / unit, such as a control or configuration register, a logical resource (for example, the PIO can be interpreted as a command), etc.
[0024] In one embodiment, PIO operations can use the same interconnection as the CDMA 20 controller, and can flow through the CDMA 20 controller, for peripheral components 18A to 18B and the flash memory interface unit 30. In this way, the PIO operation can be sent by the processor 22 over the interconnectable mesh 16 (via the L2 cache, in this mode), to the CDMA controller 20, and to be the target of the peripheral component / memory interface unit. in flash. Similarly, IOP 32 can send PIO operations to the CDMA controller 20, which can transmit PIO Operation on the same interconnect to peripheral components 18A and 18B or the flash memory interface unit 30.
[0025] Consequently, the data transfer for a DMA operation to / from a peripheral component 18A and 18B or the flash memory interface unit 30 may conflict with PIO operations to / from the same peripheral component 18A and 18B or the flash memory interface unit 30. For example, the flash memory interface unit 30 can be programmed via PIO operations to perform memory transfer to / from flash memory devices 28A and 28B. For writing purposes, the CDMA 20 controller can DMA the data to be written to the flash memory interface unit 30. For read operations, the CDMA 20 controller can DMA the data to be read from the interface unit flash memory 30. In one embodiment, flash memory devices 28A through 28D can support a data transfer page to / from the devices. The page size depends on the device, and may not be the same page size used for translating virtual-to-physical address into memory 12. For example, page sizes 512 bytes, 2048 bytes, and 4096 bytes are used many times. Consequently, a page can be the unit for transferring data to the memory device in this context.
[0026] The flash memory interface unit 30 can be programmed to execute a data transfer page, and the CDMA unit 20 can perform DMA operations for data transfer. If several pages need to be transferred, additional PIO operations can be used to program the flash memory interface unit 30 to perform the next transfer. However, DMA operations can effectively stop additional PIO operations until the current page is completed. Thus, the time that elapses when programming the flash memory interface unit 30 to the next page can result in idle time on the interface of the flash memory devices.
[0027] Additionally, a DMA transfer can be initiated and then a transfer of data with a higher priority may be required in the IC 10. For example, in relation to the flash memory interface unit 30, the transfer of DMA in occurrence can be initiated by an application and then the operating system may need to remove data from flash page 28A and 28B from the page or read data from flash memory 28A and 28B to satisfy the missing page. Alternatively, an application that is running in the background may have initiated the transfer of DMA, and an application that is used actively (advance) may need to execute a transfer. In another example, applications can be designated priorities. In yet another example, the hardware in the IC 10 may require access to flash memory 28A and 28B and may have a higher priority than software access.
[0028] In one embodiment, the flash memory interface unit 30 can support several command queues. The command programs of a flash memory interface unit 30 in a set of pages that will be transferred can be queued in one of the command queues. Once the DMA operations for the first page begin, the data for programming the flash memory interface unit 30 for subsequent pages can already be stored in the command queue. Consequently, there can be no conflict between PIO operations for programming the flash memory interface unit 30 and DMA operations for data transfer. The usage on the interface of the flash memory devices 28A and 28B can be increased due to the ability to process the commands from the command queue for the configuration of the flash memory controller 30 to the next page that will be transferred while the CDMA drive 30 completes DMA operations for the current page.
[0029] In addition, command queues may have a priority associated with them. For example, two queues can be added: one can be a low priority queue and the other can be a high priority queue. The flash memory interface unit 30 can be configured to stop processing commands in the low priority queue if there are commands in the high priority queue to be processed. In this way, a higher priority transfer can interrupt a lower priority transfer. In one embodiment, the low priority queue may include one or more indications that identify the locations in the chain of commands in which interruption is permitted. The indications can guarantee that the interruption occurs in a "good" place in the commands (for example, at the end of a page, at a synchronization point, etc.). That is, operations that were taking place in the low priority queue at the time that commands were written to the high priority queue can be completed, so that these operations do not have to be performed again after the high priority processing has been completed. In one embodiment, queues can be statically designated as high priority or low priority. In other modalities, the priority can be programmable.
[0030] In one embodiment, the flash memory interface unit 30 can support macro memory for storing one or more macros. A macro can be a sequence of two or more commands that can be invoked using a macro command. For example, the macro command can be written in one of the command queues, and you can invoke the macro when the macro command is executed by the flash memory interface unit 30. Macros using the commonly used command sequences can be downloaded via download in macro memory, and therefore less commands need to be downloaded by downloading subsequently. That is, macros commands can be written to the command queue instead of typing commands stored in the macro repeatedly. In one mode, the macro command can specify a macro start address and a number of words in the macro. Once the number of words has been read from the macro and the corresponding commands have been executed, the next command in the corresponding command queue after the macro command can be executed. Accordingly, the return commands can be avoided in this macro, allowing more dense macros in one mode. Other modalities can use the starting address and several commands as operands. In addition, other modalities may employ a return command and the macro command may include the starting address (but not word / command count) as an operand. In one embodiment, the macro command can also include a link count operand. The link count operand can specify a number of macro repetitions that are performed. Thus, the execution of the macro command can include reading several words starting with the starting address and executing commands, repetitions of the link count several times, before proceeding with the next command in the command queue after the macro command.
[0031] Commands in command queues and / or commands in macro memory can use operands to control their operations. In some cases, operands can be stored in the corresponding command queue. In other cases, operands can be stored in an operand queue. The commands in the command queue or in macro memory can specify the unit of the operands for loading the flash memory interface 30 from the operand queue and the operation on the operands. The operand queue can be used with a macro to provide specific example data for the generic macro (for example, flash memory addresses, chip capacitors, etc.). Similarly, the operand queue can provide operands for the commands in the command queue.
[0032] A memory transfer, as used in this document, can refer to the transfer of data to / from a memory device (through the interface to the memory device). Thus, a transfer of memory to / from flash memory devices 28A and 28B can occur over the interface between flash memory devices 28A and 28B and flash memory interface unit 30. Similarly, a transfer of memory to / of memory 12 can occur over the interface between memory 12 and memory controller 14. Memory transfer can occur using a protocol defined by the memory devices. In addition, a command can refer to one or more bytes of data that are interpreted by the hardware in the peripheral component (for example, the flash memory interface unit 30) as specified by a particular operation to be performed by the hardware.
[0033] In general, a peripheral component can be any desired circuit to be included on the integrated circuit 10 with the processor. A peripheral component can have defined functionality and the interface through which other components of integrated circuit 10 can communicate with the peripheral component. For example, peripheral components can include video components, such as display controllers, graphics processors, etc .; audio components, such as digital signal processors, mixer, etc .; network components, such as an Ethernet media access controller (MAC) or a wireless internet controller (WiFi); controllers for communication with various interfaces, such as universal serial bus (USB), peripheral component interconnection (PCI) or its variants, such as PCI Express (PCIe), serial peripheral interface (SPI), flash memory interface, etc. The flash memory interface unit 30 can be an example of a peripheral component, and the general properties of a peripheral component described herein may be applicable to the flash memory interface unit 30.
[0034] Processor 22 can employ any instruction set architecture, and can be configured to execute defined instructions, including instruction set architecture. Processor 22 can employ any microarchitecture, including scalar, superscalar, with pipeline technology, super pipeline technology, non-sequential, sequential, speculative, non-speculative, etc., or combinations thereof. Processor 22 may include circuitry, and optionally may employ microcoding techniques. In the illustrated embodiment, processor 22 may include an L1 cache 24 for storing data and instructions for using processor 22. There may be separate L1 data and instruction caches. The L1 cache (s) can have any capacity and organization (associated with a group, directly mapped, etc.). In the illustrated embodiment, an L2 cache is also provided. The L2 cache can have any capacity and organization, similar to the L1 cache (s).
[0035] Similarly, IOP 32 can employ any instruction set architecture, and can be configured to execute instructions defined in the instruction set architecture. The instruction set architecture employed by IOP 32 does not have to be the same instruction set architecture used by processor 22. In one embodiment, IOP 32 can be a processor with less power and less execution than processor 22. The IOP 32 can handle several I / O interface issues (peripheral configuration components to perform desired operations, handle certain errors, etc.). IOP 32 can execute instructions for writing commands to the command queue on the flash memory interface unit 30, writing macros to the macro memory on the flash memory interface unit 30, and / or writing operands on the operand queue on the flash interface. flash memory 30. IOP 32 can additionally execute instructions for serving other peripheral components 18A and 18B. In this way, processor 22 can perform other computing tasks, or can be disabled for energy conservation if there are no other computing tasks to be performed. IOP 32 can employ any microarchitecture, including scalar, superscalar, with pipeline technology, with super-pipeline technology, non-sequential, sequential, speculative, non-speculative, etc., or combinations thereof. IOP 32 can include circuits, and optionally can employ microcoding techniques.
[0036] The interconnectable mesh 16 can be any interconnection over which the memory controller 14, processor 22 (through the L2 cache), the L2 cache, and the CDMA Controller 20 can communicate. The interconnectable mesh 16 can employ any type of interconnection (for example, a bus, a packet interface, point-to-point links, etc.). In one embodiment, the interconnectable mesh 16 can be a hierarchy of interconnections. For example, processor 22 and caches 24 and 26 can be employed in a "core complex" that includes a coherence port and a port for memory controller 14. CDMA Controller 20 can be coupled to the coherence port. In some embodiments, the memory controller 14 may have several ports. In some embodiments, the CDMA 20 controller can be coupled to a separate port on the memory controller 14. In other embodiments, the CDMA 20 controller can also be coupled via the ACP port.
[0037] The memory controller 14 can be configured to receive memory requests from the system interface unit 16. The memory controller 14 can be configured to access memory 12 to complete the requests (write the data received in the memory 12 for a write request, or supply of data from memory 12 in response to a read request) using the interface defined by the attached memory12. The memory controller 14 can be configured to interface with any type of memory 12, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), dual data rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. The memory can be arranged as multiple memory banks, as double-row memory modules (DIMMs), single-row memory modules (SIMMs), etc. In one embodiment, one or more memory chips are attached to the integrated circuit 10 in a packet-on-packet (POP) or chip-on-chip (COC) configuration.
[0038] Memory 12 can include one or more memory devices. In general, a memory device can be any component that is designed for storing data according to an address provided with the data in a write operation, and for providing data when the address is used in a read operation. Any of the examples of memory types mentioned above can be used in a memory device, and flash memory devices 28A and 28B can be memory devices as well. A memory device can be a chip, several chips connected to a substrate such as a printed circuit board (for example, a SIMM or DIMM, or directly connected to a circuit board to which the IC 10 is attached), etc.
[0039] The flash memory interface unit 30 may include circuits configured to receive write and read requests from flash memory devices 28A and 28B, and configured to interface via flash memory devices 28A and 28B to complete read / write requests. In one embodiment, read / write requests can originate from the CDMA 20 controller. The flash memory interface unit 30 can be programmable through one or more control registers (see figure 2 described below) to performing memory transfers to / from flash memory devices 28A and 28B (for example, through PIO operations). Flash memory devices 28A and 28B can be flash memory, a type of non-volatile memory that is known in the art. In other embodiments, other forms of non-volatile memory can be used. For example, battery-backed SRAM, various types of programmable ROMs, such as electrically erasable programmable ROMs (EEPROMs), etc. can be used. In still other modalities, volatile memory can be used similar to memory 12.
[0040] While the present mode describes using command queues (FIFO), the macro memory, and / or operand queue (FIFO) in the flash memory interface unit 30, other modalities can employ the characteristics in any peripheral component, with any type of memory or peripheral interface.
[0041] Note that other modalities may include other combinations of the components, including subgroups or supergroups of the components shown in figure 1 and / or other components. While an example of a given component can be shown in Figure 1, other embodiments can include one or more examples of the given component.
[0042] Now looking at figure 2, a block diagram of an embodiment of the flash memory interface unit 30 is shown. In the illustrated embodiment, the flash memory interface unit 30 includes a low priority (LP) FIFO 40 command, a high priority command queue 41 (HP), a flash memory interface control circuit 42 (IMF) , a macro memory 44, a FIFO operand 46, a flash memory controller (FMC) 48, control registers of the FMC set 50 including register 51, the intermediate data stores 52A and 52B, and a correction / error checking (ECO) 54. The FIFOs command 40 and 41, control circuit FMI 42, macro memory 44, operating FIFO 46, and intermediate stores 52A and 52B are all coupled to an internal interface of the CDMA 20 controller. control unit 42 is additionally coupled to the FIFOs 40 and 41 command, macro memory 44, the FIFO operand 46, and the FMC 50 control registers. The FMC 50 control registers are additionally coupled to the FMC 48, which is coupled to a external interface of flash memory devices. FMC 48 is additionally coupled to intermediate storage 52A and 52B. The ECC 54 unit is also coupled to intermediate storage 52A and 52B.
[0043] The FMI 42 control circuit can be configured to receive PIO operations from the CDMA 20 controller. Some PIO operations can be directed to the FIFOs 40 and 41 command, to macro memory 44, or to the operand FIFO 46. For example, PIO writing can be used to write commands inside FIFOs 40 or 41 commands, to download macros to download into macro memory 44, or to write operands inside the operand FIFO 46. Addresses can be assigned to each of FIFOs 40 and 41, macro memory 44, and FIFO 46 operand, which can be used in PIO operands to address the desired resource. For example, FIFOs 40, 41, and 46 can have a single designated address, since they can operate in a first-in and out-of-the-way manner. A PIO write to the address can cause the FMI control circuit 42 to store the data provided with the write in the next open input on FIFOs 40, 41, or 46. That is, the data can be appended to the end of FIFO 40, 41 , or 46, where commands or operands are removed from the beginning of FIFO 40, 41, or 46. Macro memory 44 can have a range of addresses assigned to it, for example, an address per word from macro memory 44. The PIO writes to the address that can store the data words provided in the macro memory address word 44.
[0044] The FMI 42 control circuit can process the commands in the FIFOs 40 or 41 commands to program several FMC 50 control registers to make the FMC 48 perform a particular memory transfer to / from the control devices. flash memory 28A and 28B. In one embodiment, the FMC 48 is configured to receive relatively low level control through the FMC 50 control registers, including the address, chip capacity, transfer commands, etc. the commands in the FIFOs 40 and 41 commands can be interpreted through the FMI 42 control circuit and the corresponding FMC 50 control registers can be written by the FMI 42 control circuit. Similarly, the commands queuing through the event can be interpreted by the control circuit. FMI control 42 to read one or more FMC 50 control registers in order to detect the event. It is also possible to have direct control signals between the control circuit FMI 42 to FMC 48, in some modalities (not shown in figure 2) that can be taken to the control circuit FMI 42 that responds to commands and / or monitored by the circuit control panel 42 that responds to commands.
[0045] The FMI 42 control circuit can be configured to read the commands from the FIFO 40 or 41 commands in the order written by the FIFO. More generally, command queues can be supported (for example, FIFOs 40 and 41 commands may not be specifically developed as FIFOs, so that each entry in the queues can be visible at the same time via the FMI 42 control circuit). Similarly, the FIFO 46 operand can be an operand queue, and the FMI control circuit 42 can read the operands from the FIFO 46 operands that respond to commands in the command queue or macro memory 44 in the order of which the operands. operands were written.
[0046] If both FIFOs 40 and 41 are empty, then the commands are written to the LP FIFO 40 command, the FMI 42 control circuit can read the commands from the LP FIFO 40 command and they can execute the commands. If the commands are written on the HP FIFO 41 while the FMI 42 control circuit is processing the LP FIFO 40 commands, the FMI 42 control circuit can determine a point at which it stops processing commands from the FIFO 40 to start processing the FIFO 41 commands. In figure 2, several entries in the LP FIFO 40 command are illustrated for this mode. In this mode, each entry in the LP FIFO 40 command can include storage for the command, along with a yield bit ("Y"). If the throughput bit is set for a given command, the processing of the commands can be interrupted after the given command is processed. If the processing bit is clear, processing cannot be interrupted. The performance bits can be part of the PIO data for writing PIO in the LP FIFO 40 command. In other modalities, other indications can be used (for example, a bit with the opposite meanings for the set and clear states, values of multibit, etc.). In addition, other modes can use a separate command on FIFO 40 to indicate the possibility of interruption. That is, a command can be defined whose operation is to allow the FMI 40 control circuit to interrupt the processing of FIFO 40 for the processing of commands from FIFO 41, if there are such commands. If no command is filing processing on FIFO 41, processing on FIFO 40 can continue with the next command.
[0047] In response to the interrupt processing of the commands in the LP FIFO 40 command for the processing of the HP FIFO 41 commands, the FMI 42 control circuit can be configured to set the HPE bit in register 51 in this mode. Once the HPE Bit is established, the FMI 42 control circuit can be configured for processing commands from the HP FIFO 41 Command, if any, but may not process the commands from the LP FIFO 40 command until the HPE bit is clear. The FMI 42 control circuit may not make the HPE bit clear, but software preferably can do the task by writing register 51. That way, if the FMI 42 control circuit empties the HP FIFO 41 command before the software ends filling in the FIFO 41 command (for example, due to software interruption, delay in transmitting the commands to the flash memory interface unit 30, etc.), the FMI control circuit 42 may not return prematurely to the processing of commands from the LP FIFO 40 command. Additionally, since the high priority sequence of the commands is complete, the software can read the LP FIFO 40 command to determine where the low priority sequence of the commands was interrupted.
[0048] In some modalities, the software can also write register 51 to set the HPE bit. This action can cause the FMI control circuit 42 to stop processing the LP FIFO 40 command at the next boundary (as indicated by the Y bits). Such an operation may allow the software to stop processing the LP FIFO 40 Command and may allow the software to examine the position of the LP FIFO 40 Command. Similarly, the software may write a standby command (or other command that does not cause configuration changes of the flash memory interface 30 or the control registers 50) on the HP FIFO 41 command, which can cause the FMI control circuit 42 to stop processing commands from the LP FIFO 40 command at an appropriate point.
[0049] As mentioned earlier, a macro command can be in one of the FIFOs 40 or 41 commands, and the FMI control circuit 42 can execute the commands from macro memory 44 in response to the macro command. In other modalities, the macro command can be transmitted as a PIO operation to the FMI 42 control circuit. In still other modalities, the macro commands can be found in FIFO 40 or 41 commands, or in PIO operations. The macro command can include a starting address in macro memory and a word count that indicates the number of words to be read from macro memory 44. The FMI control circuit 42 can execute commands in the macro before reading the next command (following the macro command) in the corresponding FIFO 40 or 41 command. The words in the macro can include operands in addition to the commands, in one mode. Other modalities may use a command count instead of a word count. As mentioned above, the macro command can also include a loop count and the macro can be repeated the number of times indicated in the loop count.
[0050] The reading of words from the FIFO 40 and 41 commands, and from the FIFO 46 operand, can include the FMI 42 control circuit by deleting those words from the FIFO. Reading words from macro memory 44, on the other hand, may not involve deleting words so that macros can be executed repeatedly.
[0051] The FMC 48 can perform the memory transfer in response to the contents of the FMC 50 control registers, the written data read from the flash memory devices 28A and 28B of the intermediate storage 52A and 52B or the written data read from intermediate storage 52A and 52B of flash memory devices 28A and 28B. The intermediate stores 52A and 52B can be used in a round-trip manner, in which one of the intermediate stores 52A and 52B is filled with data while the other is emptied. For example, readings from flash memory devices 28A and 28B may include FMC 48 filling one of the intermediate stores 52A and 52B while the other temporary storage 52A and 52B is emptied by the CDMA controller 20 that performs DMA operations from memory 12. The writings of the flash memory devices 28A and 28B may include the CDMA controller 20 filling one of the intermediate stores 52A and 52B with the data while the FMC 48 empties the other temporary storage 52A and 52B. The ECC unit 54 can generate ECC data for writing to flash memory devices 28A and 28B, and can check ECC data for readings from flash memory devices 28A and 28B.
[0052] Now checking figure 3, a flow chart is shown that illustrates the operation of a modality of the control circuit FMI 42 in response to the receipt of a PIO operation from the CDMA 20 controller. While the blocks are shown in an order particularly for ease of understanding, other orders can be used. The blocks can be executed in parallel in combinatorial logic in the control circuit FMI 42. For example, the decision blocks illustrated in figure 3 can be independent and can be executed in parallel. The blocks, combinations of blocks, and / or the flowchart as a whole can have pipeline technology over different clock cycles. The control circuit FMI 42 can be configured to use the operation illustrated in figure 3.
[0053] If the PIO write is addressed to the LP FIFO 40 command (decision block 60, "yes" side), the FMI 42 control circuit can be configured to update the next entry in the LP FIFO 40 command with the data to from PIO writing (block62). That is, the data from the PIO writing can be appended to the end of the LP FIFO 40 command. As mentioned above, the PIO data in this mode can be the command and the yield bit. If the PIO writing is addressed to the HP FIFO 41 command (decision block 61, "yes" strand), the FMI 42 control circuit can be configured to update the next entry in the HP FIFO 41 command with the data from the writing PIO (block 63). That is, the data from the PIO writing can be appended to the end of the HP FIFO 41 command. As mentioned above, the PIO data in this mode can be the command. If the PIO writing is addressed to macro memory 44 (decision block 64, strand "yes"), the control circuit FMI 42 can be configured to update the addressed address in macro memory 44 with data from the PIO writing (block 66). If the PIO writing is addressed to the FIFO 46 operand (decision block 68, "yes" strand), the FMI 42 control circuit can be configured to update the next entry in the FIFO 46 operand with the data from the PIO writing (block 70). That is, the data from the PIO write can be appended to the FIFO operand 46. If the PIO write is addressed to a register within the FMC 50 control registers (or other registers in the flash memory interface unit 30, in different modalities - decision block 72, "yes" side), the control circuit FMI 42 can be configured to update the addressed record (block74).
[0054] Now looking at figure 4, a table 76 is shown that illustrates an example command set that can be supported by a flash memory interface unit modality 30, and more particularly the FMI control circuit 42. Other modalities they can support any other set of commands, including subsets of the commands shown in figure 4, subsets of the commands and other commands, and / or a superset of the commands and other commands. The table includes a "command" column that lists each command, a "operand" column that indicates the operands for a given command, and a "word" column that indicates the number of words in the FIFO 40 or 41 commands that are occupied by the command.
[0055] The format of the commands can vary from modality to modality. For example, in one embodiment, each command can include an operational code byte that indicates the command within the command set (that is, each entry in table 76 can be identified using a different operational code encoding). The remaining bytes in the word or words that make up the command can be used to specify the operands for the command. The commands can be stored in FIFOs 40 or 41 commands, or in macro memory 44, in several modalities.
[0056] The address commands (addrO to addr7 in table 76) can be used to send address bytes over the interface to the flash memory devices 28A and 28B (more succinctly called the flash memory interface). The digit after "addr" indicates the number of bytes of the transmitted address, starting with byte 0 of the addresses on the flash memory interface. The FMI control circuit 42 can be configured to stop until the address bytes are transmitted before executing the next command, in one mode. The addrX commands can be equivalent to programming the following FMC 50 control registers, in one modality: One or more address registers with the address bytes, and transfer number programming and read / write mode in one or more records. Responsive to the read / write mode, the FMC 48 can transmit the address bytes over the flash memory interface and can signal an address whose interruption ended in a situation record within the FMC 50 control registers. In addition, addrX commands can include additionally wait for and clear and terminate address interruption in the situation record. The addrO command can differ from the addrl to addr7 commands in that the address transfer and address transfer number registration are not programmed. Instead, these registers can be pre-programmed using other commands such as the load_próximo_word or load_from_fifo commands described below.
[0057] The cmd command can be used to send the flash memory command out of the flash memory interface. In one embodiment, the flash memory interface commands are one byte. Accordingly, the operand of the cmd command can be the command byte that can be transmitted over the flash memory interface. The FMI 42 control circuit can be configured to stall until the cmd command is completed on the flash memory interface. The cmd command can be equivalent to programming a command register in the FMC 50 control registers with the command byte; which sets a command mode bit in another FMC 50 control register; and wait for and clear a cmd interrupt completion in a situation record within the FMC 50 control registers. In response to the command mode bit setting, the FMC 48 can be configured to transmit the command byte over the flash memory interface and can write the cmd interrupt completion in the situation record.
[0058] The enable_chip command can be used to write a chip enable record from the FMC 50 control registers, which can cause the FMC 48 to direct chip enable signals over the flash memory interface based on the operating on chip training.
[0059] The command xfer_page can be used to initiate a page transfer to / from flash memory devices 28A and 28B. In response to the xfer_page command, the FMI 42 control circuit can be configured to set a start bit in an FMC 50 control register and wait for and clear a page interrupt completion bit in another FMC control register 50. In response to the initiation bit, FMC 48 can be configured to perform the transfer of the specified page, and configuration of the interrupt completion page after the task is completed.
[0060] There may be several synchronization commands supported by the FMI 42 control circuit. In general, a synchronization command can be used to specify an event that the FMI 42 control circuit must monitor, and can cause the circuit FMI 42 control panel wait for the event to occur (ie wait until the FMI 42 control circuit detects the event) before executing the next command. In this way, the synchronization commands can allow sequences of commands to be programmed, and the synchronization commands can help ensure the correct time. For example, multi-page transfers can be pre-programmed, and synchronization commands can be used to delay programming the FMC 50 control registers to the next page until the records are no longer needed for the current page (for example , after the last data from the page is loaded into temporary storage 52A and 52B for reading).
[0061] In the mode of figure 4, the synchronization commands can include wait_for_rdy, pause, timed_wait, and wait_for_int. The wait_for_rdy command can be used to monitor the status of the 28A and 28B flash memory devices during a page transfer. The wait_for_rdy command can include waiting for and clearing a specific interrupt completion (for example, page) in the FMC 50 control record status record; masking a situation byte in the situation record with the mask type operand, and comparing the mask situation byte to the condition operand. If the masked status byte matches the condition operand, the FMI 42 control circuit can be configured to execute the next command. Otherwise, the control circuit FMI 42 can signal an interruption (for example, from IOP 32 or processor 22, in various modalities) and can pause the execution of additional commands until the IOP 32 / processor 22 serves to interrupt.
[0062] The pause command can be used to stop the execution of the command by the control circuit FMI 42. The control circuit FMI 42 can stop the execution of commands until it is specifically removed from pause by the execution of the software in IOP 32 / processor 22 which writes a specified enable bit in one of the FMC 50 control registers.
[0063] The FMI 42 control circuit can be configured to pause and resume after a number of clock cycles using the timed_wait command. The number of clock cycles is specified according to the operand of the timed_wait command. In some embodiments, the timed_wait command can be used to slow down the flash memory interface unit 30, due to the possible execution using the FIFO 40 command, the macro memory 44, and the FIFO 46 operand can exceed the rate in which activities can be performed by flash memory devices 28A and 28B.
[0064] The wait_for_int command can be used to make the FMI 42 control circuit wait for a specified break value. Operands can specify the interrupt (irq) to be expected, and the state of the irq bit to be expected (for example, configuration or clearing), using the "bit" operand.
[0065] The sendjnterrupt command can be used to send a specified interrupt to IOP 32 or processor 22. The sendjnterrupt command operand can specify an interrupt code to write into an interrupt code record in the FMC 50 control registers, which can cause the interrupt to be sent.
[0066] The commands load_next_word and load_from_fifop can be used to program several registers in the FMC 50 control registers. One of the operands of these commands is the register address of the control register to be written. In response to the load_next_word command, the FMI control circuit 42 can read the next word from the FIFO command 40 and write a word to the addressed register. In response to the load_from_fifo command, the FMI control circuit 42 can be configured to read the word at the beginning of the FIFO 46 operand and write the word to be addressed in the register.
[0067] The macro command can be used to make the FMI control circuit 42 read the commands from macro memory 44. The macro command includes an address operand, a length operand, and a link count operand . The address can identify the first word to be read from macro memory 44, and the length can identify the length of the macro (for example, in terms of number of commands or number of words). In one embodiment, length is the number of words. The link count can indicate a number of repetitions of the macro to be executed. In one embodiment, the link count operand can be one less than the number of repetitions (for example, a link count of zero is one repetition, a link count of one is two repetitions, etc.). Once the macro completes, the next FIFO command 42 can be read (that is, there can be no return command in the macro).
[0068] The poly command can be to name any record in the FMC 50 control registers for a specified value (after masking the value read from the record using the mask field). The FMI control circuit 42 can name the registrations until the specified value is detected, it then proceeds to the next command.
[0069] As noted in the description above, the FMI 42 control circuit can monitor several interruptions recorded in one or more situation records within the FMC 50 control records as part of the execution of certain commands. The control circuit FMI 42 can clear the interruption and complete the corresponding command. In the absence of commands on the FIFO 40 command, the interrupt can instead be routed to IOP 32 / processor 22 (if enabled). Consequently, the PIO write operations on the FMC 50 control and IOP 32 / processor 22 interrupt registers may be another mechanism to perform memory transfers to / from flash memory devices 28A and 28B.
[0070] Now looking at figure 5, a flow chart illustrating the operation of a modality of the control circuit FMI 42 for processing the command from command line LP 40 is shown. While the blocks are shown in a particular order to facilitate understanding, other orders can be used. The blocks can be executed in parallel in a combinatorial logic in the control circuit FMI 42. The blocks, block combinations, and / or the flowchart as a whole can have the pipeline technology over several clock cycles. The control circuit FMI 42 can be configured to use the operation illustrated in figure 5.
[0071] The FMI 42 control circuit can be configured to read a command from the LP FIFO 40 command (block 80). If the command is not a macro command (decision block 82, strand "no"), the control circuit FMI 42 can be configured to execute the command (block 84). Once the command is complete, and if the yield bit (Y) is set and there is a valid command in command line HP 41 (decision block 85, strand "yes"), the control circuit FMI 42 can be configured for the HPE Bit configuration in register 51 and output of the HP command processing (for example, figure 6) (block 87). Similarly, in some embodiments, the FMI 42 control circuit can be configured to output HP command processing (or at least to decrease low priority processing) that responds to the HPE Bit being configured (for example by the software that writes record 51). Otherwise (decision block 84, strand "no"), the control circuit FMI 42 can be configured to check the word count used to determine whether a macro has reached its end. If the command is not part of a macro, the word count can be zero (decision block 86, "no" strand). The FMI 42 control circuit can be configured to check the link count associated with the macro command. If the command is not part of a macro, the link count can be zero (decision block 95, "no" strand). The FMI control circuit 42 can be configured to determine if there is another valid command in the FIFO 40 command (decision block 88). That is, the control circuit FMI 42 can be configured to determine if the FIFO command 40 is empty. If there is another valid command (decision block 88, strand "yes"), the control circuit FMI 42 can be configured to read and process the next command. Otherwise, the FMI 42's control circuit command processing circuits may be inactive until another valid command is written to the FIFO 40 command (decision block 88, "no" side).
[0072] If the command is a macro command (decision block 82, strand "yes"), the control circuit FMI 42 can be configured for the initialization of the word count of the length operand of the macro command and for the initialization of the link count of the macro command link count operand (block 90). The FMI control circuit 42 can also read a command from macro memory 44 (block 92). Specifically, in this case, the FMI control circuit 42 can read the first word from the address in macro memory 44 provided as the address operand of the macro command. The control circuit FMI 42 can be configured to execute the command (block 84), and can be configured to check the word count (in this case there may be no Y bit and, therefore, decision block 85 can result in the "no" strand). The word count can be greater than zero (decision block 86, strand "yes"), and the FMI control circuit 42 can be configured to reduce the word count and to read the next command from macro memory 44 ( for example, by increasing the address) (blocks 94 and 96). The control circuit FMI 42 can be configured to process the next command (returning to decision block 82 in the flowchart of figure 5). If the word count is zero (decision block 86, strand "no"), the control circuit FMI 42 can be configured to check the link count. If the link count is greater than zero (decision block 95, "yes" side), another macro delay must be performed. The FMI control circuit 42 can decrease the link count (block 97), reset the word count and macro address (block 99), and read the next command from macro memory 44 (that is, the first command of the macro) (block 96). If both the word count and link count are zero (decision block 86 and 5, strand "no"), the macro is complete and the control circuit FMI 42 can check the next valid command in command row 40 (block Decision 88).
[0073] It can be seen that, since each command is verified to be a macro command, the macro commands can be stored in macro memory 44 as well. Consequently, macros can be "docked", although the last macro to be executed returns to the FIFO 40 command so that there is no real docking in the sense that macros do not return to the macros that call them.
[0074] Figure 6 is a flowchart that illustrates the operation of an FMI control circuit modality 42 for processing a command from the HP 41 command queue. That is, processing as shown in figure 6 can be initiated in response to the existing LP processing as discussed above in relation to figure 5 (block 87). While the blocks are shown in a particular order for ease of understanding, other orders can be used. The blocks can be executed in parallel in combinatorial logic in the control circuit FMI 42. The blocks, block combinations, and / or the flowchart as a whole can have pipeline technology over several clock cycles. The control circuit FMI 42 can be configured to use the operation illustrated in figure 6.
[0075] The FMI 42 control circuit can be configured to read a command from the HP FIFO 40 command (block 180). If the command is not a macro command (decision block 182, strand "no"), the control circuit FMI 42 can be configured to execute the command (block 184). Once the command is completed, the FMI 42 control circuit can be configured to check a word count used to determine if a macro has reached its end. If the command is not part of a macro, the word count can be zero (decision block 186, "no" strand). The FMI 42 control circuit can be configured to check the link count associated with the macro command. If the command is not part of a macro, the link count can be zero (decision block 195, "no" strand). The FMI control circuit 42 can be configured to determine whether there is another valid command in the HP FIFO 41 command (decision block 188). That is, the FMI 42 control circuit can be configured to determine whether the HP FIFO 41 command is empty. If there is another valid command (decision block 188, strand "yes"), the control circuit FMI 42 can be configured to read and process the next command. Otherwise, the control circuit FMI 42 can check whether the HPE bit is clear (decision block 198). If so, the control circuit FMI 42 can return to LP command processing (decision block 198, strand "yes"). If not (decision block 198, strand "no"), the control circuit FMI 42 can be inactive until any valid command appears in the HP FIFO 41 command or the HPE bit is cleared.
[0076] If the command is a macro command (decision block 182, strand "yes"), the control circuit FMI 42 can be configured for the initialization of the word count of the length operand of the macro command and for the initialization of the link count of the link count operand of the macro command (block 190). The FMI control circuit 42 can also read a command from macro memory 44 (block 192). Specifically, in this case, the FMI control circuit 42 can read the first Word from the address in macro memory 44 provided as the address operand of the macro command. The FMI control circuit 42 can be configured to execute the command (block 184), and can be configured to check the word count. The word count can be greater than zero (decision block 186, strand "yes"), and the control circuit FMI 42 can be configured to decrease the word count and to read the next command from macro memory 44 (for example, by increasing the address) (blocks 194 and 196). The FMI control circuit 42 can be configured to process the next command (returning to decision block 182 in the flowchart of figure 6). If the word count is zero (decision block 186, strand "no"), the control circuit FMI 42 can be configured to check the link count. If the link count is greater than zero (decision block 195, "yes" strand), another macro delay must be performed. The FMI control circuit 42 can decrease the link count (block 197), reset the word count and the macro address (block 199), and read the next command from macro memory 44 (that is, the first command of the macro) (block 196). If both word count and link count are zero (decision block 186 and 195, strand "no"), the macro is completed and the control circuit FMI 42 can verify the next valid command in the HP FIFO 41 command (block Decision 188).
[0077] Checking now figure 7, a block diagram of an example of a use of macros for the execution of several page scripts on a 28A or 28B flash memory device is shown. A content of macro memory 44 is shown, including three sections of the commands. Between the macro memory addresses 0 and N-1, N macro words 100 to complete the writing on the previous page are stored. Between the macro memory addresses N and N + M-1, M macro words 102 to start writing the next page are stored. Between the macro memory address N + M and N + M + P-1, P macro words 104 are stored for the finalization of the last page of a write in memory.
[0078] A set of commands in the LP FIFO 40 command is illustrated in figure 7, with the beginning of the FIFO at the top of the LP FIFO 40 command and the subsequent commands in the next FIFO in order of the LP FIFO 40 command, as shown in figure 7 The first command is macro N, M. The command calls macro 104, starting with the word N, and executing M words (that is, macro 102 as shown in figure 6). In this way, the writing on the first page is started. Subsequent page writes can be performed using macro 0, N + M commands. These commands cause macro 100 and macro 102 to be executed. Writing on the previous page can be completed (macro 100) and writing on the next page can be started (macro 102). The last page can be written using the macro command 0, N + M + P. This command causes macros 100, 102, and 104 to be executed, completing the writing from the second to the last page (macro 100), executing the writing on the last page (macro 102), and completing the writing on the last page and closing the flash memory device 28A or 28B (macro 104). In this example, the link count operand for each macro command is zero (a delay). However, in another example, shown below in the first example in figure 7, the link count operand can be used to make commands in the command queue even more efficient. The link count of the macro command N, M for the first page and the macro command 0, N + M + P of the last page can still be zero, specifying a delay. However, the middle pages of the script can all be fulfilled using a macro command (macro 0, N + M) with a link count operand equal to the page count (C) minus 3. The link count is C-3 that counts for the first and last pages, as well as the fact that the link count operand is one less than the desired number of delays in this mode. As macros 100, 102, and 104 illustrate, by carefully placing macros in macro memory 44, they can result in dense and effective macros. Macros can use the load_from_fifo commands to use different operands for each page writing operand, and the operands of each page can be loaded inside the FIFO 46 operand before the commands start in the LP FIFO 40 command.
[0079] The commands included in macro 102 can establish the address to be written, enable the chip, etc. the commands included in macro 100 can cause xfer_page to transfer the previous page

权利要求:
Claims (12)
[0001]
1. Apparatus for controlling an external interface in an integrated circuit (10), the apparatus comprising: a first command row (40) configured to store a first plurality of commands, the first command row (40) it is additionally configured to store one or more indications that identify points within the first plurality of commands in which the interruption of the first plurality of commands is permissible; and a second command row (41) configured to store a second plurality of commands; a control circuit (42) coupled to the first command row (40) and the second command row (41), characterized by the fact that the control circuit (42) is configured to interrupt the processing of the first plurality of commands in a first command identified as a breakable point in response to the detection of at least a second command in the second command row (41), and the control circuit (42) is configured to initiate the processing of the second command in response to interruption; and a plurality of control registers (50) coupled to the control circuit (42), the control circuit (42) being configured to update one (51) among the plurality of control registers (50) to indicate that the second plurality of commands are being processed, and the control circuit (42) is configured to inhibit processing of the first plurality of commands, even if the second command row (41) is empty of the second plurality of commands, until that one (51) of the plurality of control records (52) is updated again to indicate that processing of the first plurality of commands must be continued.
[0002]
2. Apparatus according to claim 1, characterized by the fact that the one or more indications are a plurality of indications, each indication being associated with a respective command of the first plurality of commands and indicating whether the first plurality of commands is liable interruption or not in the respective control.
[0003]
3. Integrated circuit (10) characterized by the fact that it comprises: a memory controller (14) configured to be coupled to one or more memory devices (12); a flash memory interface unit (30) configured to be coupled to one or more flash memory devices (28A, 28B), the flash memory interface unit (30) comprising the apparatus as defined in claim 1 ; a direct memory access controller (DMA) (20) coupled to the memory controller (14) and the flash memory interface unit (30), where the DMA controller (20) is configured to perform DMA operations between the memory controller (14) and the flash memory interface unit (30); and a processor (22) coupled to the DMA controller (20), in which the processor (22) is configured to control the flash memory interface unit (30), and in which communications from the processor (22) pass through the DMA controller (20) to the flash memory interface unit (30) through an interconnection between the DMA controller (20) and the flash memory interface unit (30), and where the interconnection also it is used in DMA operations between the flash memory interface unit (30) and the memory controller (14); wherein the processor (22) is configured to write a first plurality of commands from the first command row (40) to control a first transfer between the flash memory interface unit (30) and the one or more flash memory devices (28A, 28B), and where the processor (22) is configured to write the second plurality of commands to the second command row (41) to control a second transfer between the flash memory interface unit (30) and one or more flash memory devices (28A, 28B) before completing the first transfer.
[0004]
4. Method comprising the steps of: processing commands from a first command row (40) on an interface controller (30) to perform one or more transfers on an external interface; detecting an indication associated with a first command within the commands from the first command row (40); detecting at least a second command in a second command row (41) at a time when the indication is detected; characterized by the fact that: interrupting additional command processing from the first command row (40) to process commands from the second command row (41) in response to the detection of the indication and at least a second command; write a control record (51) to indicate that the commands in the second command row (41) are being processed; and avoiding further command processing from the second command row (41) in response to the contents of the control register.
[0005]
5. Method, according to claim 4, characterized by the fact that it additionally comprises receiving a write operation that updates the control register to allow the continuous processing of the commands in the first command row (40).
[0006]
6. Method, according to claim 5, characterized by the fact that the write operation is sent by a processor (22).
[0007]
7. Method, according to claim 4, characterized by the fact that it still comprises: loading a first plurality of commands within the first command row (40), in which the performance of the first plurality of commands causes a first transfer at the interface external; detect a need for a higher priority transfer than the first transfer; and loading a second plurality of commands into the second command row (41) to perform the highest priority transfer, where the interface controller (30) is configured to stop processing the first transfer to perform the highest priority transfer .
[0008]
8. Method, according to claim 7, characterized by the fact that it further comprises: writing the control register (51) to indicate that the commands in the second command row (41) are not being processed.
[0009]
9. Method, according to claim 8, characterized by the fact that it further comprises: reading the first command row (40) to determine a point in the first plurality of commands in which the interruption occurred.
[0010]
10. Method according to any of claims 7 to 9, characterized in that loading the first plurality of commands into the first command row (40) comprises loading corresponding indications of points at which the first plurality of commands is interruptible.
[0011]
11. Method, according to claim 10, characterized by the fact that it still comprises: detecting a need for a third transfer that has no higher priority than the first transfer; and loading a third plurality of commands into the first command row (40) to perform a third transfer.
[0012]
12. Computer-readable storage medium (200) characterized by the fact that it stores a plurality of instructions that, when executed, implement the method as defined in any of claims 4 to 11.

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法律状态:
2013-10-08| B03A| Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]|

2018-12-11| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|

2019-10-15| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

2020-04-28| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

2020-09-15| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 30/08/2012, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

申请号 | 申请日 | 专利标题

US13/220,940|US9021146B2|2011-08-30|2011-08-30|High priority command queue for peripheral component|

US13/220,940|2011-08-30|

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