• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Focal plane array (FPA) comprising a photodiode array (PDA) and a read integrated circuit (ROIC), where the FPA can include a plurality of conductive bumps that electrically couple the circuits of the PDA to the circuits of the ROIC. In one embodiment, a visually transparent cover can include a plurality of traces electrically coupled to circuitry on the ROIC, and it can be used as a conductive path between the ROIC and the outer pads.
    公开号:BE1023572B1
    申请号:E2014/0171
    申请日:2014-03-14
    公开日:2017-05-08
    发明作者:Peter E. Dixon
    申请人:Sensors Unlimited Inc.；
    IPC主号:
    专利说明:

    INTEGRATED INPUT CIRCUIT INPUT / OUTPUT ROUTING ON A PERMANENT SUPPORT
    DOMAIN OF MODES OF REALIZATION
    The present invention relates to the field of integrated circuits and, more particularly, to the provision of a focal plane array device comprising a photodiode array and an integrated readout circuit.
    HISTORY OF MODES OF REALIZATION
    [0002] Light-sensitive image sensors such as focal plane array (FPA) devices include a photodiode array (PDA) provided with an integrated reading circuit (ROIC). There are many configurations of FPA boxes, for example, wired and wireless enclosures. Each type of traditional FPA case can include several common features.
    Figure 3 shows a schematic cross-sectional view of an FPA 200 device provided as a wireless chip carrier (LCC). FIG. 3 comprises a ceramic, plastic or resin support body 202 comprising internal traces 204 electrically coupled to external studs or crenellations 206. The external studs 206 may be surface-mounted on a circuit board using of a conductor, or the device 200 can be placed in an LCC socket. FIG. 3 further represents a ROIC 208 physically fixed on the support 202 by means of an adhesive 210. The connection wires 212 electrically couple the connection pads (which are not shown individually for reasons of simplicity) on the ROIC 208 to the traces 204 inside the support body 202 so that it is possible to electrically access the circuits on the ROIC 208 through the external studs 206. A PDA 214 is mounted on the upper surface of the ROIC 208 using a non-conductive adhesive (not shown individually for simplicity). Other connection wires 218 electrically couple the circuits on the PDA 214 to the circuits on the ROIC 208. A case cover 216 hermetically sealed to the carrier 202 includes a transparent window 216A that exposes the PDA 214 to the outside light. In the device 200 of FIG. 3, the support 202 is configured so that the lower surface of the cover 216 does not come into contact with the loop in the connection wires 212 and 218. FPAs including ROICs and PDAs provided in different types of packages are well known.
    The design goals of the engineers manufacturing the semiconductor devices include the provision of smaller sized devices at reduced cost and increased reliability. A device design that achieves one or more of these objectives would be desirable.
    SUMMARY OF METHODS OF REALIZATION
    [0005] A simplified summary is presented below to provide a basic understanding of certain aspects of one or more embodiments of the present invention. This summary is not an exhaustive presentation, nor is it intended to identify the key or critical elements of the present invention nor to delimit the scope of the invention. Its main purpose is simply to present one or more concepts in a simplified form as a prelude to the detailed description given later.
    In one embodiment of the present invention, a focal plane array (FPA) may comprise an integrated readout circuit (ROIC) having a circuit side provided with circuits thereon, a photodiode array (PDA) comprising circuits having a plurality of photodiodes, and a conductor interposed between the PDA and the ROIC, wherein the conductor electrically couples the circuits on the PDA to the circuits on the ROIC.
    In another embodiment, a focal plane array (FPA) design method may comprise physically contacting a first plurality of receive pads on a photodiode array (PDA) with a conductor. physically contacting a second plurality of receive pads on an integrated read circuit (ROIC) with the conductor, where the conductor is interposed between the PDA and the ROIC, harden the conductor to physically secure the PDA and the ROIC. one over the other and to electrically couple the circuits on the PDA to the circuits on the ROIC, and secure the PDA on a visually transparent cover.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The accompanying drawings, which are incorporated herein by reference and form an integral part thereof, represent the embodiments of the present invention and, together with the description, serve to explain the principles of the invention. In the figures: [0009] Fig. 1 shows a cross-section of a focal plane array according to an embodiment of the present invention; FIG. 2 represents a cross-section of a plurality of focal plane arrays forming part of an integration process at the chip scale; and [0011] Figure 3 shows a traditional focal plane array.
    It should be emphasized that certain details of the figures have been simplified and are drawn to facilitate understanding of the present invention rather than to maintain structural accuracy, detail and scale.
    DESCRIPTION OF THE EMBODIMENTS
    [0013] Reference will now be made in detail to the exemplary embodiments of the present invention, which examples are shown in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.
    While the embodiments of the present invention are described with reference to a device provided in the form of wireless chip carrier (LCC), it will be understood that a device according to the present invention may be provided in the form of wire device or other wireless devices.
    It becomes more difficult to make reliable electrical connections in a traditional device housing with reduced device dimensions. The son 212 and 218 of connection such as those shown in Figure 3 are relatively large and therefore require large connection pads as a connection surface. For example, the connection pads of a conventional reading integrated circuit (ROIC) for focal plane array (FPA) devices may be about 100 μm by about 160 μm. In addition, the lower surface of the cover 216 must be located above the top of the loop in the connecting wire 212 as shown in Figure 3, which increases the overall height of the housing.
    An embodiment of the present invention can result in a more reliable electrical connection between the circuits on the ROIC and the connections outside the housing, and between the circuits on the ROIC and the circuits on the PDA, compared to the connection wires of traditional housings. Moreover, in one embodiment, the connection wires can be eliminated, which makes it possible to reduce the height of the housing, for example in view of the fact that the lower surface of the cover can be closer to the PDA than is possible with traditional devices.
    FIG. 1 is a schematic cross section showing an FPA device 10 according to an embodiment of the present invention, and comprises a first semiconductor chip which may be a PDA 12 and a second semiconductor chip which may be A ROIC 14. It will be understood that PDA 12 and ROIC 14 may be designed using conventional technology except where indicated. In the embodiment of Figure 1, the FPA device 10 may not include wire connections, particularly wire connections that provide power and grounding for the ROIC, and / or input / output (I / O) to and from ROIC 14, and / or electrical connections between PDA 12 and ROIC 14.
    In the device of Figure 1, a plurality of conductive bumps 16, for example studs or indium bumps 16 similar to bumps ball housing (B GA), can be designed between circuits such as pixels on the PDA 12 and the circuits on the ROIC 14. The bumps 16 can be designed according to known techniques. In one embodiment, a plurality of first receive pads (not shown individually in FIG. 1) on the PDA 12 are electrically coupled to a second plurality of receive pads (which are not shown individually in FIG. 1) on the ROIC 14 using the bumps 16. In one embodiment, a dielectric fill 18 may be provided around the plurality of bumps 16. The bumps 16 may provide the functionality of the receiving pads 218 (FIG. ) traditional devices.
    Before assembly of the device, a cover is prepared (for example, a window) 20. The cover can be made from a material that is visually transparent (which, for the purposes of the present invention, comprises a visually transparent material) at the light wavelength to be detected by the focal plane array (FPA) [completed Focal Plan Array] 10. In several embodiments, the cover 20 may be glass, a polymer or a material semiconductor such as silicone, according to the light wavelength to be detected. To prepare the lid 20, a plurality of patterned conductive patterns 22 are formed on the lower surface of the lid 20, where the bottom surface is within the completed APF 10.
    In one embodiment, a conductive coating layer may be formed on the bottom surface of the lid, for example using chemical vapor deposition (CVD) or a spraying process, which is structured and printed using known lithographic techniques. Using this method, the traces 22 will extend from the lower surface of the cover 20 by a distance equal to the thickness of the traces 22. In one embodiment, the traces 22 may have a width of between about 2 μm and about 25 μm, as needed for good conductivity or for current resistance requirements. The traces may also have a pitch of between about 10 μm and about 200 μm, providing a greater range of possibilities for handling a high interconnect density, thereby allowing design freedom previously limited by the arrangement of bond pads. In addition, the traces may have a thickness of between 1 μm and about 5 μm, depending on electrical or mechanical requirements. The formation of plots 22 at these dimensions makes it possible to align the plots 22 on the receiving pads 26 (see discussion below) on the ROIC 14 and provide an acceptable electrical resistance of the plots 22.
    In another embodiment for forming the traces 22, a plurality of trenches may be etched chemically or mechanically using a lithographic process or laser in the bottom surface of the cover. A conductive coating layer may be formed on the lower surface within the trenches, and then a polishing method may be used to remove the conductive coating layer from the lower surface of the cover except for the interior of the trenches ( a process usually called a damascene process). Using this method, the exposed surface of the traces will be coplanar or nearly coplanar with the bottom surface of the cover or may be embedded within the trenches.
    It is possible to use a conductor 24, such as an indium hump, to electrically couple each trace 22 to a third plurality of receiving pads 26 which connect to the circuit (which is not described individually for the sake of simplicity) on the ROIC surface 14. In one embodiment, a lower surface of the cover 20 may be physically attached to the PDA 12 using a dielectric 28 such as glass, polymer, thermoset or thermoplastic , which can provide additional support for different electrical interconnections.
    Figure 1 further describes a housing body 30. The housing body 30 of Figure 1 is a lead-free chip carrier (LCC) housing body, but it will be understood that this housing body 30 may also be represent several other embodiments of the present invention, such as other lead-free or lead-free form factors, or a printed circuit board (PCB) or other substrate. The housing body 30 has a second plurality of traces 32 made therein, which are electrically coupled to a plurality of pellets or crenellations 34 which are external to the housing body 30. A conductor 36 electrically couples the plurality first traces 22 on the cover 20 to the second plurality of traces 32 within the housing body 30. The physical connection of the cover 20 to the housing body 30 may include the use of a hermetic sealing material 38 such as a metal, epoxy, a polymer, a eutectic, etc. In one embodiment, the lower surface of the ROIC 14 may be attached to a surface of the housing body 30 as described with a conductive or dielectric connecting material 40, which secures the ROIC 14 in the housing body. housing 30 and can accommodate other connections such as connections 16, 24 and 36. In another embodiment, the structure 40 may schematically show a thermoelectric cooler (TEC).
    In a method for forming the structure of FIG. 1, several subassemblies including the PDA 12, the ROIC 14, the cover 20 and the housing body 30 are prepared, the assembly of the subsets of the device can be then start. Several different process streams for forming the FPA device of FIG. 1 are contemplated. In one embodiment, a plurality of FPA devices may be fabricated simultaneously in a wafer scale integration method and, after completion of the plurality of wafer scale connected devices 10. physically, the plurality of physically connected wafer-scale devices 10 are singularized to form a plurality of individual devices 10. The process flow described below describes the formation of a single device that can be individually formed or as one of a plurality of wafer scale devices.
    In a process flow, a PDA 12 may be manufactured as an epitaxial layer on a sacrificial carrier substrate 50 (FIG. 2, not described individually in FIG. 1 for the sake of simplicity) and a ROIC 14 may be manufactured separately. The plurality of conductive bumps 16 may be formed on a plurality of receiving pads on an exposed surface of the PDA 12 or on a plurality of receiving pads on the ROIC 14. The plurality of receiving pads of the ROIC 14 and receiving pads PDA 12, and the associated circuits, have been described individually for the sake of simplicity. The PDA 12 and the ROIC 14 are aligned with each other so that the receiving pads of each device come into contact with the plurality of bumps 16 so that the bumps 16 are interposed between the PDA 12 and the ROIC. 14, then the bumps 16 are remelted to physically connect and electrically couple the ROIC 14 to the PDA 12. It will be seen that other conductors and other methods can be used to interconnect the PDA 12 and the ROIC 14, so that a method using a conductive epoxy, a z-axis conductor, etc. After fixing, a dielectric underflow material 18 may be interposed between the ROIC 14 and the PDA 12, and around the bumps 18.
    Substrate 50 may then be refined, for example, by means of a back-grinding process of a semiconductor or by means of other chemical, mechanical or chemi-mechanical techniques. The PDA 12 connected to the ROIC 14 can be physically attached to the cover 20 with an adhesive or other bonding product 28 of this type which is visually transparent at the desired light wavelength. In one embodiment, the bonding product 28 may include a wafer assembly solution used in 3-D (3DIC) integrated circuit constructs, such as a sintered glass, a polymer, a thermoplastic or a thermoset.
    The cover 20, including the PDA 12 and the fixed ROIC 14, can then be physically fixed and electrically coupled to the housing body 30. A first end of each trace 22 can be physically fixed and electrically coupled to a stud. receiving the ROIC circuit 14 using a conductor 24, such as a fluid or curable conductor 24. A second end of each trace 22 may be physically attached and electronically coupled to a trace 32 within the housing body 30 with a conductor 36 similar to or different from the conductor 24. Attaching the cover 20 to the housing body 30 may also include the use of a hermetic sealant 38 such as a metal, an epoxy, a polymer, a eutectic, etc. After fixing the cover 20 to the housing body 30, a structure similar to that described in Figure 1 persists. The FPA 10 of FIG. 1 thus includes a PDA 12 and a ROIC 14 sealed inside an FPA box 10. A lower surface of the cover 20 on which the PDA 12 is attached has the plurality of traces 22 fixed to that Here, the traces 22 being inside the FPA box 10. It will be obvious to those skilled in the art that the FPA 10 described in FIG. 1 represents a generalized schematic illustration and that it is possible to add other components or remove or modify existing components.
    Thus an electrical path can be established between the circuit on the PDA 12 and the circuit of the ROIC 14 with the bumps 16. These bumps 16 can provide a more robust electrical connection, for example that the connection son 218 described in FIG. 3. In addition, a conductive path between a circuit on the ROIC 14 and the pads 34 external to the FPA box 10 (and thus also between the circuit on the PDA 12 and the pads 34) can be established through the receiving pads 26 on the ROIC 14 which are electrically coupled to a first plurality of traces 22 on the cover 20 through the conductor 24. The traces 22 on the cover 20 may be electrically coupled to a second plurality of traces 32 at the Inside the housing body 30 through the conductor 36. The traces 32 are electrically coupled to the pellets 34 by known techniques.
    Thus, the embodiment of FIG. 1 provides an FPA 10 which carries signals of the PDA circuit 12 and of the ROIC circuit 14 on the inside of the casing 10 to the pellets 34 on an external or external surface of the casing 10 without using connecting wires 212 such as those described in Figure 3. In addition, electrical coupling between the ROIC 14 and the PDA 12 is established using conductive bumps 16 rather than connection wires 218 (Figure 3 ).
    In addition, an FPA 10 having a smaller height may be formed, for example because the bottom surface of the lid 20 may be closer to, and even directly attached to, an upper surface of the PDA 12 as described in FIG. In addition, the plurality of electrical connections within the FPA 10 may be smaller and more reliable than the connecting wires 212. As shown in FIG. 1, in one embodiment, all the electrical connections between the PDA 12 and the ROIC 14 are provided inside an outer perimeter of the PDA 12.
    Figure 2 is a schematic view of a plurality of devices 10 formed using a wafer scale integration method. While Figure 2 depicts two related devices prior to singling, it will be appreciated that any number of devices can be formed using a wafer scaling method. The number of devices that can be formed is limited, for example, by the size of the semiconductor wafer 50 and the size of the FPA devices 10. After the formation, the structure of FIG. 3, for example, according to FIGS. As discussed above for a wafer-scale method, the plurality of PDAs 10 may be separated or singled out into a plurality of discrete PDA devices by splicing the structure along the line. 52 using a miter saw, laser ablation, etc.
    [0032] Notwithstanding that the digital ranges and parameters having the broad scope of the present invention are approximations, the numerical values in the specific examples are indicated as precisely as possible. However, any numerical value intrinsically contains some errors necessarily resulting from the standard deviation found in the respective test measurements of these values. In addition, all ranges disclosed herein are deemed to encompass each and all of the sub-ranges grouped herein. For example, the "less than 10" range may include all sub-ranges between the minimum values of zero and maximum of 10 (inclusive), i.e. each and all sub-ranges having a value. minimum equal to or greater than zero and a maximum value equal to or less than 10, e.g. 1 to 5. In some cases, numerical values, as indicated for the parameters, may take negative values. In this case, the range values of the example specified "less than 10" may take negative values, such as. -1, -2, -3, -10, -20, -30, etc.
    While the present invention has been illustrated with respect to one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit or scope of the claims herein. -jointes. For example, it will be appreciated that even if the process is described as a series of actions or events, the present teachings are not limited by the order of said actions or events. Some actions may occur in different orders and / or simultaneously with other actions or events than those described in this document. In addition, not all process steps may be required to implement a methodology in accordance with one or more aspects or embodiments of the present invention. It will be appreciated that structural components and / or processing steps can be added or that existing structural components and / or processing steps can be deleted or modified. In addition, one or more actions described herein may be performed in one or more separate actions and / or phases. Furthermore, to the extent that the terms "including", "includes", "having", "a", "with" or variations of these terms are used either in the detailed description or in the claims, said terms are intended inclusive as the term "including". The phrase "at least one of" is used to indicate that one or more of the enumerated items may be selected. In addition, in the discussion and claims of this document, the word "on" used for two materials, one "on" the other, expresses at least one contact of any kind between the materials, while " above "means that the materials are close to each other but potentially with one or more additional materials interposed so that contact is possible but not necessary. Neither "over" nor "above" imply any direction as used in this document. The term "compliant" describes a coating material in which the angles of the underlying material are protected by the conforming material. The term "about" indicates that the value mentioned may vary somewhat, as long as this variation does not result in a nonconformity of the process or structure with the illustrated embodiment. Finally, the term "illustrative" indicates that the description is used as an example, rather than implying that it is an ideal. Other embodiments of the present invention will be apparent to those skilled in the art having regard to the features and based on the practice of the invention disclosed herein. It is intended that the features and examples be considered merely illustrative, the actual scope and spirit of the present invention being indicated by the following claims: The relative position terms used in the present application are defined on the basis of a plane parallel to the conventional plane or to the work surface of a workpiece, regardless of the orientation of the workpiece. The terms "horizontal" or "lateral" as used in this application are defined as a plane parallel to the conventional plane or work surface of a workpiece, regardless of the orientation of the workpiece. The term "vertical" means a direction perpendicular to the horizontal. Terms such as "on", "lateral" (as in "sidewall"), "upper", "lower", "above", "high" and "below" are defined in relation to the conventional plan or to the work surface on the top surface of the workpiece, regardless of the orientation of the workpiece.
    权利要求:
    Claims (17)
    [1]
    CLAIMS:
    A focal plane array (FPA), comprising: a case body; a dielectric connecting material attaching the body of the housing to an integrated reading circuit (ROIC) comprising a circuit side on which circuits are located; a photodiode array (PDA) comprising circuitry including a plurality of photodiodes; and a conductor interposed between the PDA and the ROIC, the conductor electrically coupling the PDA circuits and those of the ROIC; a visually transparent cover in which the box body and lid define the interior of the FPA, and the PDA and ROIC being sealed within the FPA such that the lower surface of the visually transparent cover extends beyond the PDA and ROIC; and a plurality of conductive traces on the inner surface of the cover, the circuits on the ROIC being electrically coupled to the plurality of conductive traces on the inner surface of the cover.
    [2]
    A focal plane array according to claim 1, wherein: said case body extends continuously between an upper surface and a lower surface to define outer sides, the case body having a cavity formed therein to define inner side walls and an inner surface extending between the inner side walls; said visually transparent cover comprises an inner surface extending continuously between a pair of opposed outer edges, the outer edges being attached to the outer sides of said housing body through a hermetic sealing material interposed between said cover visually transparent and the outer sides; said plurality of conductive traces comprises a first plot and a second opposite plot, wherein the dielectric layer is interposed between the first and second traces so as to physically fix the visually transparent cover on the PDA.
    [3]
    The focal plane array according to one of claims 1 to 2, further comprising a plurality of trenches on the interior surface of the cover, wherein the plurality of traces are in the plurality of trenches.
    [4]
    The focal plane array of claim 3, further comprising a plurality of traces in the housing body, wherein the plurality of traces on the interior surface of the cover is electrically coupled to the plurality of traces located in the housing body.
    [5]
    The focal plane array of claim 4, further comprising a dielectric that physically fixes the PDA on the interior surface of the cover.
    [6]
    The focal plane array of claim 5, wherein the plurality of bumps are in the outer perimeter of the PDA.
    [7]
    A focal plane array according to claim 6, wherein: the PDA does not include any connecting wire electrically coupling the PDA to the ROIC; and the PDA does not include any connection wire electrically coupling the ROIC to the housing body.
    [8]
    8. focal plane array according to one of claims 1 to 2, wherein the housing body is a chip carrier.
    [9]
    9. focal plane array according to one of claims 1 to 2, wherein the housing body is a printed circuit board.
    [10]
    The focal plane array of one of claims 1 to 2, wherein: the PDA does not include any connection wire electrically coupling the PDA to the ROIC; the PDA does not include any connection wire electrically coupling the ROIC to the housing body;
    [11]
    A method of making a focal plane array (FPA), comprising: physically contacting a first plurality of receive pads on a photodiode array (PDA) with a conductor; physically contacting a second plurality of receive pads on an integrated readout circuit (ROIC) with the conductor, wherein the conductor is interposed between the PDA and the ROIC; harden the conductor to physically secure the PDA and ROIC on each other and electrically couple the circuits on the PDA to the circuits on the ROIC; attaching the PDA to a visually transparent cover such that the outer edges of the visually transparent cover extend beyond the sides of the PDA; attaching the visually transparent cover to an upper surface of the housing body; electrically coupling a first end of a first plurality of conductive traces on the cover to circuits on the ROIC; and electrically coupling a second end of a first plurality of conductive traces on the cover to a second plurality of conductive traces in the housing body. depositing a dielectric connecting material attaching the body of the housing to an integrated reading circuit (ROIC) comprising a circuit side on which circuits are located;
    [12]
    The method of claim 11 wherein said step of attaching the visually transparent cover to said housing body comprises electrically coupling said transparent cover to an upper surface of the housing body which extends between the opposite side walls, the outer edges. a visually transparent cover being attached to the upper surface by means of a hermetic sealing material interposed between the outer edges of the visually transparent cover and the side walls; said first plurality of conductive traces comprises a first lower path interposed between a first side wall of the opposite side walls and a first side of the PDA, and a second upper path interposed between a second side wall of the opposite side walls and a second side of the opposite PDA. on the first side; said second plurality of conductive traces comprises a first lower path interposed between the first side wall of the opposite side walls and a first lateral edge of the ROIC, and a second lower path interposed between a second side wall of the opposite side walls and a second side edge of the ROIC opposite the first side edge; said step of depositing said dielectric connecting material is performed prior to fixing the visually transparent cover; and wherein said dielectric layer is interposed between the first and second traces so as to physically secure the visually transparent cover to the PDA.
    [13]
    The method of claim 11 or 12, including electrically coupling the circuits on the ROIC to a plurality of crenellations on an exterior surface of the housing body during electrical coupling of the first end of the first plurality of conductive paths over the the cover to the circuits on the ROIC and the electrical coupling of the second end of the first plurality of conductive traces on the cover to the second plurality of conductive traces in the case body.
    [14]
    The method of claim 13, further comprising: forming a plurality of trenches on the inner surface of the lid; forming a metal coating layer above the inner surface of the lid and within the plurality of trenches on the inner surface of the lid; and flattening the metal coating layer to form the plurality of conductive traces.
    [15]
    The method of claim 11 or 12, further comprising: providing a package body as a chip carrier; and attaching the visually transparent cover to the housing body as a chip carrier.
    [16]
    The method of claim 11 or 12, further comprising: providing a package body in the form of a printed circuit board; and attaching the visually transparent cover to the housing body in the form of a printed circuit board.
    [17]
    The method of claim 11 or 12, further comprising: fabricating the FPA connected to a plurality of other FPA devices in a wafer scale integration method; singling out the plurality of FPAs to form a plurality of individual FPAs.
    类似技术:
    公开号 | 公开日 | 专利标题
    BE1023572B1|2017-05-08|INTEGRATED CIRCUIT INPUT / OUTPUT ROUTING ON A PERMANENT SUPPORT.
    KR20130025805A|2013-03-12|Stepped package for image sensor and method of making same
    FR2700416A1|1994-07-13|Semiconductor device having a semiconductor element on a mounting element.
    TWI573253B|2017-03-01|Sensor package with exposed sensor array and method of making same
    KR101386056B1|2014-04-16|Electronic and optical circuit integration through wafer bonding
    FR2805082A1|2001-08-17|THREE-DIMENSIONAL INTERCONNECTION METHOD AND ELECTRONIC DEVICE OBTAINED THEREBY
    FR2874456A1|2006-02-24|METHOD OF MANUFACTURING SEMIDONDUCTOR CHIP, SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE.
    EP0593330B1|1998-12-09|3D-interconnection method for electronic component housings and resulting 3D component
    EP0424262A1|1991-04-24|Portable electronics with connectable components
    EP3089211A1|2016-11-02|Moisture-resistant electronic component and method for packaging an electronic circuit for manufacturing such a component
    FR3018953A1|2015-09-25|INTEGRATED CIRCUIT CHIP MOUNTED ON AN INTERPOSER
    BE1021228B1|2015-08-18|SMALL SIZE, WEIGHT, AND PICTURE SENSOR PACKAGING
    BE1023972B1|2017-09-27|FOCUS PLANAR MATRIX PERIPHERAL VIAS FOR INTEGRATED READING CIRCUIT
    EP2816597A2|2014-12-24|Method for manufacturing a mechanically self-contained microelectronic device
    EP1427008B1|2008-04-23|Process of manufacturing an electronic module comprising an active component on a substrate
    FR3003400A1|2014-09-19|TRAVERSEE FOR HIGH FREQUENCY SIGNALS
    FR2877537A1|2006-05-05|Microelectronic box for e.g. radar, has upper and lower stages with printed circuits that along with intermediate structure are made of organic material, and channels interconnected with circuits` connection points to interconnect stages
    EP3579286B1|2021-01-20|Photonic chip penetrated by a via
    FR2922682A1|2009-04-24|Micromodule i.e. image capturing micromodule, fabricating method for e.g. mobile telephone, involves forming connection between lateral conductive layer and conductive layer of housing by depositing conductive material in cavity
    FR3060851A1|2018-06-22|OPTOELECTRONIC 3D IMAGING MODULE
    FR3076659A1|2019-07-12|INSULATING SPACER FOR RETRIEVING CONTACTS
    EP1162660A1|2001-12-12|Electronic assembly with high density of electrical interconnections
    EP2162915B1|2020-09-09|Method of producing a via in a reconstituted substrate and corresponding device
    JP6851773B2|2021-03-31|Semiconductor device
    WO2019030288A1|2019-02-14|Electronic system comprising a lower redistribution layer and method for producing such an electronic system
    同族专利:
    公开号 | 公开日
    US9276030B2|2016-03-01|
    IL231521A|2017-07-31|
    US20140263955A1|2014-09-18|
    IL231521D0|2014-08-31|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    EP1453097A1|2001-11-05|2004-09-01|Mitsumasa Koyanagi|Solid-state image sensor and its production method|
    EP1494277A2|2003-07-03|2005-01-05|Matsushita Electric Industrial Co., Ltd.|Module with a built-in semiconductor and method for producing the same|
    US20060043438A1|2003-10-31|2006-03-02|Paige Holm|Integrated photoserver for CMOS imagers|
    US20050163016A1|2004-01-27|2005-07-28|Sharp Kabushiki Kaisha|Module for optical devices, and manufacturing method of module for optical devices|
    US20080211045A1|2006-04-11|2008-09-04|Sharp Kabushik Kaisha|Module for optical apparatus and method of producing module for optical apparatus|
    US20070252227A1|2006-04-28|2007-11-01|Toshiyuki Fukuda|Optical apparatus and optical module using the same|
    EP2267776A1|2009-06-23|2010-12-29|John Trezza|Multicolor detectors and applications thereof|WO2020214719A1|2019-04-15|2020-10-22|Owl Autonomous Imaging, Inc.|Thermal ranging devices and methods|US6855572B2|2002-08-28|2005-02-15|Micron Technology, Inc.|Castellation wafer level packaging of integrated circuit chips|
    US7348671B2|2005-01-26|2008-03-25|Micron Technology, Inc.|Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same|
    KR100775058B1|2005-09-29|2007-11-08|삼성전자주식회사|Pixel Cell, Image Sensor Adopting The Pixel Cell, and Image Processing System Including The Image Sensor|
    US8232137B2|2009-12-10|2012-07-31|Intersil Americas Inc.|Heat conduction for chip stacks and 3-D circuits|
    US20120194719A1|2011-02-01|2012-08-02|Scott Churchwell|Image sensor units with stacked image sensors and image processors|JP2015115522A|2013-12-13|2015-06-22|ソニー株式会社|Solid-state imaging device, method of manufacturing the same, and electronic apparatus|
    US9831281B2|2015-05-01|2017-11-28|Sensors Unlimited, Inc.|Electrical interconnects for photodiode arrays and readout interface circuits in focal plane array assemblies|
    US20180226515A1|2017-02-06|2018-08-09|Semiconductor Components Industries, Llc|Semiconductor device and method of forming embedded thermoelectric cooler for heat dissipation of image sensor|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US13/838,265|US9276030B2|2013-03-15|2013-03-15|Read out integrated circuit input/output routing on permanent carrier|
    US13838265|2013-03-15|
    [返回顶部]