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    • 专利摘要:

    公开号:BE1020663A5
    申请号:E201200464
    申请日:2012-07-05
    公开日:2014-02-04
    发明作者:Bert Serneels；Tim Piessens；Eldert Geukens
    申请人:Icsence Nv；
    IPC主号:
    专利说明:

    DC-DC converter circuit
    FIELD OF THE INVENTION
    The present invention relates to the field of DC-DC conversion circuits in which a DC input voltage is increased.
    BACKGROUND OF THE INVENTION
    The pressure to integrate more functions and complexity on chips to reduce dimensions and costs and to reduce market introduction time is pushing IC technologies toward standard nanometer CMOS low-voltage circuits. A common practice to bridge the gap with high-voltage applications such as LED, MEMS, etc., is to use expensive extensions to digital CMOS technology to tolerate voltages higher than the nominal power supply. In the past, solutions have already been proposed for the regular CMOS based on the principle of stacked devices. However, the operation of these circuits depends on the presence of multiples of the nominal supply voltage (2V0D, 3V0D, ...) in order to function reliably. The external generation of these voltages and the high-voltage rail itself inevitably lead to a more expensive bill of material.
    In the paper "Digitally Assisted Discontinuous Conduction Mode 5V / 100MHz and 10V / 45MHz DC-DC Boost Converters with Integrated Schottky Diodes in Standard 0.13um CMOS" (P.Li et al., ISSCC Digest or Technical Papers, p. 206-207, February 2010) a step-up converter in CMOS technology with low voltage was proposed. However, the conversion is performed by a switched inductor phase followed by a floating capacitor configuration to process a 10 V output. This considerably lowers efficiency and limits use to low power applications.
    On the other hand, to generate the medium voltages, solutions are proposed with step-down converters. An example of this is described in “20uA to 100m DC-DC Converter with 2.8 to 4.2V Battery Supply for Portable Applications in 45nm CMOS” (S. Bandyopadhyay et al., ISSCC Digest of Technical Papers, pages 386-387, February 2011 Stacked controllers are used to generate medium voltage, both circuits operate directly from the high voltage power supply, so additional startup circuits are needed to ensure that the devices are not overloaded during startup.
    Therefore, there is a need for a DC-DC converter circuit where the use of a plurality of multiples of the nominal supply voltage is avoided. The DC-DC converter circuit must also be implemented in an efficient manner and be suitable for a wide range of applications.
    Summary of the invention
    It is an object of embodiments of the present invention to provide a circuit for increasing a DC input voltage signal to a DC output voltage signal, wherein no additional start-up circuits are required for generating medium voltages.
    The above object is achieved by a DC-DC converter circuit according to the present invention. The DC-DC converter circuit comprises an input terminal for applying a DC input voltage signal and an output terminal for outputting a DC output voltage signal being an elevated version of said DC input voltage signal. The DC-DC converter circuit comprises a semiconductor switch comprising a plurality of switching elements. The switching elements are switchable between an open state and a closed state. At least one of the switching elements cannot tolerate the (high) DC output voltage. The semiconductor switch is connected to a voltage pass element that receives a signal from the switch at a voltage level that is higher than the DC output voltage signal. The voltage pass element outputs the DC output voltage signal supplied to the output terminal. The DC-DC converter circuit further comprises a first biasing means which is fed with the DC output voltage signal and adapted to derive at least one medium voltage signal from the DC output voltage with a voltage level lower than the DC voltage output voltage signal. A second setting means receives the DC input voltage signal and said at least one medium voltage signal and is adapted to supply the DC input voltage signal and the at least one medium voltage signal to at least one switching element of the semiconductor switch. Due to the at least one medium voltage, the semiconductor switch is adapted to tolerate a voltage level in its open state that is higher than the DC output voltage signal.
    A control block receives the DC input voltage signal that constitutes the nominal supply voltage for the control block circuits. The control block also receives the DC output voltage signal. The control block comprises switch control logic for comparing the DC output voltage signal with a reference voltage signal, after which a drive signal is sent in accordance with the result of said comparison. A buffer is arranged to receive the drive signal and to supply a voltage signal corresponding to the DC input voltage signal to a switching element of the semiconductor switch.
    The proposed DC-DC converter circuit uses only the nominal DC voltage as input and produces an increased DC voltage signal as output. By generating and applying the medium voltages by means of the setting circuits, a circuit design is obtained which, when the switch opens and is exposed to a voltage higher than the DC output voltage, tolerates such high voltage. This higher voltage is usually supplied by an inductive coupling to which a DC battery voltage (preferably, but not necessarily, equal to the voltage level of the DC input voltage signal to be converted) is applied.
    The DC output voltage, for example, is derived from the higher voltage applied via a diode. The DC output voltage is not only supplied to the output terminal, but also to the aforementioned first setting means and to the control block.
    The semiconductor switch can be closed by means of the nominal supply voltage. To protect the switching elements stacked in the semiconductor switch when said switch is opened, a first setting means is provided in which at least one medium voltage signal with a voltage level below the DC output voltage is derived and applied to a switching element of the semiconductor switch. It should also be noted that the medium voltage signals are not present at start-up, but are gradually built up in the course of the start-up phase (i.e. while the switch is being opened), following the generated DC output voltage. This is explained in more detail later in this description. Consequently, it is possible with the invention to create from one (low) voltage signal at nominal value one or, preferably, more medium voltage levels that protect different switch elements of the switch.
    The medium voltage (s) is / are fed to a second setting means which is further also fed with the DC input voltage signal. The second setting means ensures that the DC input voltage signal and the medium voltage (s) are supplied to one or more switching elements of the switch.
    An important element in the circuit of the invention is the control block. The control block receives both the DC input voltage and the DC output voltage as input. The control block is equipped with control logic to compare the DC output voltage with a reference voltage signal. A drive signal is sent depending on the result of the aforementioned comparison. The drive signal is sent as input to a buffer, which in turn supplies a voltage signal corresponding to the DC input signal to a switching element of the semiconductor switch.
    The switching elements of the semiconductor switch are preferably field effect transistors, e.g., nMOS transistors. The switch generally comprises a number of stacked transistors. These low voltage switching elements are used to generate a high voltage.
    In a preferred embodiment, the first setting means comprises at least one circuit with matched, associated resistors. Nodes with equally distributed voltages are created via such an associated resistor network. These voltages are then used as medium voltages.
    In an advantageous embodiment of the invention, the first adjusting means comprises a push-pull output stage. This is advantageous for removing the MOS threshold voltage. The push-pull output phase can, for example, be implemented as a class AB output stage.
    In one embodiment of the invention, the control block further comprises a start circuit adapted to control the pulse width of the drive signal during the start-up of the DC-DC converter circuit.
    In another embodiment, the control block further comprises circuits to limit the current through the semiconductor switch.
    In an embodiment of the invention, the voltage pass element is designed as a diode element. In that case an asynchronous topology is obtained. Alternatively, the voltage-passing element can be designed as a second high-voltage semiconductor switch comprising a further multiple number of switching elements.
    The invention also relates to a circuit comprising a DC-DC converter circuit as described above and comprising an inductive coupling through which a DC battery voltage signal is applied to the DC-DC converter circuit. The DC battery voltage signal preferably has the same value as the DC input voltage signal, so that only one voltage level, namely the nominal supply voltage, is required to operate the circuit.
    In a preferred embodiment, the circuit comprises a DC-DC converter circuit as described and a switched output stage adapted to be supplied with the DC output voltage signal from the DC-DC converter circuit. Advantageously, the switched output stage is arranged as a class D amplifier.
    In yet another embodiment, the switched output stage further comprises switching elements to bring the DC output voltage signal to a different voltage level. In other words, they form a pull-up or plow-down network. Advantageously, at least two of the further switching elements are provided with inversely connected diodes to prevent leakage at the pin.
    In another preferred embodiment, the circuit comprises a clamping circuit for electrostatic discharge (ESD). The ESD terminal circuit preferably comprises a plurality of ESD terminals wherein a terminal voltage signal can be generated at the at least one medium voltage signal level.
    In order to summarize the invention and the realized advantages over the prior art, certain objects and advantages of the invention have been described above. It goes without saying that all such objectives or advantages are not necessarily achieved in accordance with one specific embodiment of the invention. Thus, for example, persons skilled in the art will recognize that the invention may be embodied or embodied in a manner that achieves or optimizes one advantage or group of benefits as described herein, without necessarily realizing other goals or benefits described or suggested herein. .
    The above and other aspects of the invention will become clear and further explained with reference to the embodiment (s) described below.
    Brief description of the drawings
    The invention will now be further described, by way of example, with reference to the accompanying drawings, in which:
    FIG. 1 represents an embodiment of a DC-DC converter circuit according to the invention.
    FIG. 2 represents a schematic overview of the first setting means (general setting circuit).
    FIG. 3 represents a schematic overview of the second setting means (local setting circuit).
    FIG. 4 represents a schematic overview of the high-voltage amplifier of class D and the ESD protection.
    FIG. 5 illustrates a measurement of the efficiency of the DC-DC converter circuit.
    FIG. 6 illustrates a measurement of the efficiency of the high-voltage amplifier of class D.
    FIG. 7 illustrates a measurement of the transient waveforms of the output voltage and the inductor voltage of the DC-DC converter circuit and the output voltage of the class D amplifier.
    FIG. 8 illustrates the leakage problem that can occur.
    FIG. 9 illustrates a schematic overview of the solution for the leak.
    The figures are only schematic and non-limiting. In the figures, the size of some of the elements can be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to the actual embodiments of the invention. Any references in the claims should not be construed as limiting the scope. In the various figures, the same references refer to the same or analogous elements.
    Detailed description of illustrative embodiments
    The present invention will be described with reference to specific embodiments and with reference to certain drawings, but the invention is not limited thereto, but is only limited by the claims.
    In addition, the terms first, second, etc. are used in the description and in the claims to distinguish between similar elements and not necessarily for describing a sequence, either in time, in space, in importance or in any other way. It is to be understood that the terms used are interchangeable under proper conditions and that the embodiments of the invention described herein are capable of operating in sequences other than those described or illustrated herein. In addition, the terms above, below, etc. in the description and claims are used for descriptive purposes and not necessarily to describe relative positions. It is to be understood that the terms used are interchangeable under proper conditions and that the embodiments of the invention described herein are capable of operating in orientations other than those described or illustrated herein.
    It is to be noted that the term "comprising" as used in the claims should not be interpreted as being limited to the means specified thereafter; it does not exclude other elements or steps. It must therefore be interpreted as a specification of the presence of the listed features, units, steps or components referred to, but it does not exclude the presence or addition of one or more other features, units, steps or components or groups thereof. Therefore, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of parts A and B. It means that with regard to the present invention, the only relevant parts of the device A and B to be.
    References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or feature described in connection with the embodiment is included in at least one embodiment of the present invention. Statements of the phrase "in one embodiment" or "in an embodiment" at different places in this specification do not necessarily all refer to the same embodiment, but it is possible. Furthermore, the specific features, structures or characteristics may be combined in any suitable manner in one or more embodiments, as will be apparent to those skilled in the art from this disclosure.
    In a similar manner, it should be noted that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped into a single embodiment, figure, or description thereof to streamline the disclosure and understanding of one or more of the facilitate various inventive aspects. However, this method of disclosure should not be interpreted as an expression of an intention that the claimed invention requires more features than expressly stated in each claim. As shown in the following claims, the inventive aspects lie in less than all the features of a single preceding disclosed embodiment. Therefore, the claims that follow the detailed description are hereby explicitly included in this detailed description, wherein each claim stands on its own as a separate embodiment of the present invention.
    In addition, since some embodiments described herein include some, but not other, features included in other embodiments, combinations of features of different embodiments are intended to fall within the scope of the invention and form different embodiments, such as will be understood by someone skilled in this field. For example, in the following claims, any of the claimed embodiments can be used in any combination.
    It should be noted that the use of particular terminology in describing certain aspects of the invention does not imply that the terminology herein is redefined to be limited to any specific features of the features or aspects of the invention with which that terminology is associated.
    Numerous specific details are set forth in the description given here. However, it is understood that embodiments of the invention can be worked out without these specific details. In other cases, well-known methods, structures and techniques were not shown in detail in order not to obstruct the understanding of this description.
    FIG. 1 shows a schematic representation of an embodiment of a DC-DC converter according to the invention with an inductive coupling. An asynchronous topology is used, which means that only one high voltage switch is used and the second switch as present in a synchronous topology is replaced by a diode. Two important components can be distinguished in the diagram: the high voltage switch with its setting circuits (first and second) and the control block. An on / off control arrangement is used: the converter switches to a fixed clock frequency of, for example, 1 MHz and with a fixed pulse width ratio of 87.5%. When the output voltage exceeds the desired output voltage (eg 10 V), the converter stops switching. The pulse width can be interrupted by two additional circuits in the control block: a soft start circuit and a current limiting circuit. The soft start circuit ensures that the converter starts with a very low operating cycle that is gradually increased over time to 87.5%. In this way the output voltage is gradually built up and the inrush current is lowered. The current limiting circuit can break the pulse width at any time. The current is measured by following the voltage across the switch. If this voltage becomes too high, the pulse width is interrupted.
    The DC-DC converter works in clock cycles. One clock cycle contains two phases. In one phase the switch is closed and one side of the inductor is connected to the ground. Energy is built up in the inductor. In the next phase, the switch is opened and the energy is transferred to the output connection. Due to the diode threshold and process variations in the control block, the voltage across the switch can reach a voltage level of up to 11 V.
    The switch (111) can tolerate the 11 V by using five stacked isolated 3.3 V. nMOS transistors (112). Transistor MNi is directly driven by the control block (110) via a conical buffer (118). ). The switch is closed by means of the 3.3 V power supply, which is applied to all ports via transistors MLB1, MLB2 and MLB3 in the local setting circuit (109). To open the switch, the gate of transistor MN1 is connected to ground. When the gate of MN2 is connected to the 3.3 V input voltage, node nl can rise to 3.3 V before MN2 is completely switched off. MN1 is therefore protected. To protect the other transistors MN2, MN3, MN4 and MN5, the medium voltages 5.0 V, 7.5 V and 10.0 V must be applied to the ports of MN3, MN4 and MN5 respectively. Multiples of 2.5 V are taken to provide sufficient clearance for process and temperature variations and to absorb transient voltage peaks over the MOS connections of 3.3 V. However, these voltages are not present at start-up. To open the switch without reliability problems, the medium voltages must follow the generated 10 V supply. This process is performed by the general setting circuit (108).
    FIG. 2 a detailed schematic overview of the general setting circuit (108) is given. Two resistive ladder networks (1) and (2) can be recognized. A first ladder network (1) is expanded with diode-configured nMOS transistors and the other ladder network (2) is expanded with diode-configured pMOS transistors By matching the resistors and adjusting the transistors in their sub-threshold area, proportionally distributed voltages are generated at nodes (3), (4), (5), (23), (24) and (25). Sinking or sourcing power from these nodes, however, is not possible. Consequently, the currents through the diode-configured transistors are mirrored to a push-pull output stage. In this way the threshold variation of the transistors is also compensated. The ports of the transistors (6) and (7) connected to the diode are connected to the ports of the push-pull transistors (8) and (9). Similarly, the ports of the diode-connected transistors (10) and (11) are connected to the push-pull transistors (12) and (13), respectively, and the ports of the diode-connected transistors (14) and (15) are connected to the push-pull transistors (16) and (17). In this way a series connection of three push-pull phases is obtained, which divides the 10 V supply into the medium voltages 7.5 V, 5.0 V and 2.5 V. These voltages only vary with the temperature dependence of the resistance network and relatively follow the voltages on the 10 V supply. Also, the transistors in the push-pull output structure are set in their sub-threshold area to achieve a low output impedance. In this way the medium voltages can source and sink flows. In addition, this limits the DC power consumption of the general setting circuit to only 60 μΑ.
    The 10 V power supply and the 7.5 V, 5.0 V and 2.5 V medium voltages are applied to the local setting circuit (109) of the high voltage switch. Fig. 3 shows a detailed overview of the high-voltage switch (111) with its local adjustment circuit. The switch has two positions: open and closed.
    The switch is closed by applying 3.3 V to the gate of MN1. Node n1 is discharged to the ground and transistor MN2 is guided since its gate is permanently connected to 3.3 V. Node n2 is in turn discharged to the ground so that transistor MLP1 can conduct. In this way node nl2 is discharged to 3.3 V and transistor MN3 starts to conduct. The same reasoning applies to transistors and MN4, and M, j> 3 and MN5.
    The switch is opened by applying 0 V to the gate of MNi. Node nl is charged to a maximum of 3.3 V since its gate is fixedly connected to 3.3 V. Consequently, transistor MN2 no longer conducts and the voltage on node n2 charges. To limit the voltage drop across the terminals of transistor MN2, the gate of transistor MN3 must not be set to a voltage higher than 6.6 V. To provide sufficient play in the voltage, voltage multiples of 2.5 V are chosen. Consequently, the gate of transistor MN3 must be set to 5.0 V. For the same reason, the gates of transistors MN4 and MN5 must be set to 7.5 V and 10 V respectively. This process takes place in the local setting circuit (109). When the gate of transistor MN1 in the switch is connected to ground, the gate of transistor MLP7 in the local bias circuit is pulled to 7.5 V. This means that node nl7 is charged to 10 V. Therefore, transistor MLP6 conducts since its gate is connected to the 7.5 V of the general setting circuit. Consequently, node nl6 is charged to 10 V and node nl9 to 7.5 V via transistor MNL3, which conducts. The same reasoning applies to MLps, MLN2 and MLp4 transistors. In this way, the gate of transistor MN5, node n4, is charged to 10 V and the gate of transistor MN4, node nl3, charged to 7.5 V. Consequently, transistor MLN1 conducts and the gate of transistor MN3, node nl2, is charged up to 5 V.
    In the event that the high voltage switch (111) is closed, the transistors MLP4 and MLp5 in the local setting circuit (109) must be protected against excessive voltages by applying 3.3 V and 5 V respectively to their gates. This is accomplished via the transistors and MLP2 for the gate of MLP4 and via transistor MLN1 for the gate of transistor MLP5.
    It should therefore be noted that the gate of transistor MN1 switches together with the gate of transistor MLP7. The gate of transistor MN1 switches between 0 V and 3.3 V and the gate of transistor MLP7 must be switched between 7.5 V and 10 V. This function is performed by a standard level shifter with capacitive coupling.
    The combination of the general (108) and local (109) setting circuits allows an implementation of a high voltage switch with standard low voltage devices and guarantees that the reliability of these devices is not compromised by excessive voltages on their connections.
    The 10 V output of the inductive converter circuit can serve as the power supply for a switched output stage. FIG. 4 is a schematic representation of the class D amplifier with its setting circuits. The 10.0 V rail is protected by a modified ESD terminal for high voltage. The class D amplifier includes five stacked, isolated pMOS and nMOS transistors in the pull-up and pull-down network, respectively, to handle process and temperature variations and fast switching transitions. The local setup is based on the paper "A 237mW aDSL2 + CO Line Driver in a Standard 1.2V 130nm CMOS technology" (B. Serneels et al., ISSCC Digest of Technical Papers, pages 524-525, February 2007) and requires the medium voltages 2.5 V, 5.0 V and 7.5 V for reliable operation. These voltages are generated from the 10 V supply, such as the general setting circuit in the inductive converter. During the start-up of the converter, the class D amplifier is set to tri-state via transistors MN1 and Mpi. The 10 V rail is built up gradually and the medium voltages follow relatively. Therefore, the reliability of the device in the class D amplifier is not compromised.
    The 10 V ESD terminal consists of four 3.3 V nMOS ESD terminals that are each responsible for a 2.5 V rail. The advantage of using an nMOS in the active area as an ESD terminal is the low holding voltage. During an electrostatic discharge, the medium voltages follow the ESD pulse. These voltages are connected to the 2.5 V, 5.0 V and 7.5 V rails of the general setting blocks on the test chip via p-type DNW diodes. In this way, an even distribution of the ESD pulse over the stacked devices is obtained, thereby improving the ESD robustness of the circuits.
    To illustrate the excellent performance of the DC-DC converter of the present invention, some numerical results are presented.
    Fig. 5 shows the efficiency of an inductive DC-DC converter according to an embodiment of the invention as a function of the output power for a variation of 10% on the 3.3 V input voltage and three temperatures. The peak efficiency is 81% at an output power of 732 mW for an input voltage of 3.3 V at 25 ° C. The maximum output power is 1.5 W. Fig. 6 shows the efficiency of the class D amplifier as a function of its switching frequency for a load of 66 Ω. An efficiency of 97% is obtained for the class D amplifier. The combined efficiency (class D and DC-DC) is equal to 74%. The efficiency starts to decline with a switching frequency of 1.0 MHz. Measured waveforms of the generated 10 V supply, the class D amplifier output and the inductor current are shown in FIG. 7. The average output voltage of the converter is 9.9 V. The class D amplifier achieves an output voltage swing of 9.6 V for a load of 66 Ω, resulting in an output power of 350 mW. The switching frequency is 20 kHz. The current waveform of the inductor consists of bursts of one full clock cycle of 1 ps and one cycle in which the pulse width is broken off, visualizing the on / off operation of the converter.
    It is important to note that in the configuration shown in FIG. 4, the class D amplifier serves as a high voltage output buffer, but the proposed high voltage topology is not limited to just output buffers. When the output buffer is set to tri-state, a voltage can be applied to the output. It is known that when the applied voltage exceeds its supply voltage, a leakage path exists from the output via the parasitic drain bulk diodes from the output phase to the supply voltage. Conventional I / O buffers lead under an undesired leakage current path (leakage at the pin) when the I / O voltage at the pin becomes greater than the operating voltage. Leakage at the pin can occur via the pMOS parasitic PN diode or via the pMOS channel when the I / O input voltage is greater than VDD + Vtp (see Fig. 8).
    A topology is now proposed that removes this leakage path. This is illustrated on an 1 / O buffer with Vdd output and 2Vdd input. The proposed solution is explained in detail with reference to Figs. 9. FIG. 9 is a circuit diagram showing the pre-driver 21 and the output buffer 22 of the mixed voltage input / output buffer. The example is given of an input / output buffer that can transmit at VDD levels and receive at 2VDD levels (twice the VDD level). The output buffer comprises two pMOS pull-up transistors 23 and 24, two nMOS pull-down transistors 28 and 29 and bias transistors 25, 26, 27 and 30. The output of the output buffer 22 is connected to the I / O PAD 210 of the mixed voltage input / output buffer. The pMOS pull-up transistors 23 and 24 share the same bulk source connection (node N2) and the same port connection (node N4). The corresponding drain bulk diodes of the pMOS pull-up transistors 23 and 24 are D2 and D1, respectively. Because of their common gate and source connection, the N sides of the diodes D1 and D2 are connected to node N2 and the P sides of the diodes D1 and D2 are connected to the I / O PAD 210 and the power supply VDD of output buffer 22, respectively The pre-driver 21 transmits the data signal DIN to the output buffer 22 and sets the output buffer 22 to tri-state mode via the OEN signal (Output Enable). When the output buffer 22 is set to tri-state mode, it can withstand 2V0D signals on the I / O PAD 210 without leakage to its VDD supply and without oxide stress on any device in the output buffer 22.
    When the output buffer 22 is turned on, the input / output buffer operates in transmission mode. The signal on the I / O PAD 210 will be high or low according to the data signal Durr. In transmission mode, a high output signal is a signal on VDD and a low output signal is a signal on GND.
    For a high output on 1 / O PAD 210, the pMOS pull-up transistors 23 and 24 are set in their linear range and the nMOS pull-down transistors are turned off. The pMOS pull-up transistors 23 and 24 are set in the linear region by discharging their ports to GND. This is performed by two stacked nMOS transistors 26 and 27. The gate of transistor 26 is fixedly connected to VDD. The gate of transistor 27 is driven to VDD. The connection between the ports, node N4 and the sources, node N2 of the pMOS pull-up transistors 23 and 24 established by transistor 25 is terminated. This is done by switching off transistor 25 by connecting its gate to GND. In FIG. 8, transistor 25 is implemented as a pMOS transistor. However, other solutions are possible such as a transmission port. The nMOS pull-down transistor 29 is turned off by connecting its gate to VDD. If the I / O PAD 210 is loaded to VDD, node NI is loaded to V0D - Vtn. The gate of the nMOS pull-down transistor 28 is fixedly connected to VDD. Consequently, the transistor 28 is turned off automatically.
    For a low output on 1 / O PAD 210, the pMOS pull-up transistors 23 and 24 are turned off and the nMOS pull-down transistors 28 and 29 are set in the linear region. The pMOS pull-up transistors 23 and 24 are turned off by connecting their ports to their sources or by connecting node N2 to node N4. This is done by setting transistor 25 in the linear region by connecting its gate to GND. In this way, the gate source voltages of the pMOS pull-up transistors 23 and 24 are 0 V. Transistor 27 is turned off by bringing its gate to 0 V. The nodes N2 and N4 are kept at a constant voltage VDD via transistor 30.
    If the buffer 22 is switched off or set to tri-state via the OEN signal, the input / output buffer operates in reception mode. The tri-state mode means that both pull-up and pull-down paths are cut off. For the nMOS pull-down transistors 28 and 29, this action is performed by leading the gate from transistor 29 to GND to turn off. For the pMOS pull-up path, this action is performed by shorting ports, node N4 and sources, node N2 of the pMOS pull-up transistors 23 and 24, and by setting transistor 27 so that the nodes N2 and N4 can float between the l / O PAD 210 and the power supply V0D of the output buffer 22. In reception mode the signal on the l / O PAD 210 can rise to 2V0D. In addition to the oxide stress that the transistors of the output buffer 22 can undergo, the leakage path from the I / O PAD 210 to the VDD supply of the output buffer 22 must be interrupted. This path is formed by the pull-up transistors 23 and 24. The leak via the drain bulk diode D1 of transistor 24 is stopped by the inversely connected drain bulk diode D2 of transistor 23. Moreover, no current is possible through the channel of the pMOS pull -up transistors 23 and 24 since in tri-state operation of the output buffer 22 the gates and sources of the pull-up transistors 23 and 24 are short-circuited by transistor 25 and these nodes float between the I / O PAD 210 and the power supply VDD of the output buffer , depending on which of the two is the highest. When the voltage at the I / O PAD 210 is 2VDD, the voltage at the nodes N2 and N4 rises to 2 VDD-V0 (where VD is equal to the voltage drop across the diode). The oxide of transistor 27 is protected against the voltage 2 VDD-VD by transistor 26. The gate of transistor 26 is fixedly connected to V00, which ensures that the voltage at node N3 does not rise higher than VDD. In the nMOS pull-down path, the oxide of transistor 29 is protected in the same way against the voltage 2VD0 by transistor 28 with a fixed gate connection to VDD. When the voltage at the I / O PAD 210 is 0 V, the voltage at the nodes N2 and N4 drops to VDD via transistor 30, which is located in the triode region.
    The solution is not limited to the prevention of leaks from the I / O pin to the power supply of the output buffer. In the same way, it can be implemented in the nMOS pull-down path to prevent leakage current to the grounding of the output buffer.
    Depending on the value of the OEN control signal (Output Enable), the 1/0 buffer can serve as an input buffer or as an output buffer.
    The proposed solution to the pin leakage problem uses the least number of devices to implement the desired function in comparison with existing solutions. The solution is fairly simple. Complexity through timing, transient stress and metal connections is greatly reduced. Moreover, the solution is not dependent on set-up nodes internally in the I / O buffer. Consequently, the presence of overlap currents (shoot through) and current leaks below the threshold value is minimized and a resistive load can be carried out without consequences.
    Although the invention has been illustrated and described in detail in the drawings and foregoing description, such illustrations and descriptions are to be considered as illustrative or exemplary and not restrictive. The foregoing description explains certain embodiments of the invention in detail. It should be noted, however, that no matter how detailed the foregoing is contained in the text, the invention can be made in many ways. The invention is not limited to the disclosed embodiments.
    Other variations on the disclosed embodiments may be understood and performed by persons skilled in the art and by practicing the claimed invention, through a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps and the indefinite article "a" does not exclude a plural. Any references in the claims should not be construed as limiting the scope.
    权利要求:
    Claims (14)
    [1]
    A DC-DC converter circuit for increasing a DC input voltage signal (103) to a DC output voltage signal (105), comprising - an input terminal (104) for applying a DC input voltage signal (103), - an output terminal for a Outputting a DC output voltage signal that is an elevated version of said DC input voltage signal, a multiple number of switching elements (112) arranged to be switched between an open state and a closed state, at least one of said switching elements not being capable of is to tolerate said DC output voltage signal, - a semiconductor switch (111) comprising said multiple number of switching elements (112), - a voltage passing element (107) connected to said semiconductor switch and adapted to receive a signal at a higher voltage level than said DC output voltage signal and to supply said DC output voltage signal (105) to said output terminal, - first adjusting means (108) adapted to be supplied with said DC output voltage signal and to derive from said DC output voltage signal at least one medium voltage signal (113) with a voltage level lower than said DC output voltage signal, - second adjusting means (109) adapted to be supplied with said DC input voltage signal and with said at least one medium voltage signal and to supply said DC input voltage signal and said at least one medium voltage signal to at least one switching element of said semiconductor switch, so that said semiconductor switch in said open state can tolerate said voltage higher than said DC output voltage signal, - a control block (110) arranged to receive said DC input voltage signal and said DC output voltage signal and comprising switching control logic (117) arranged to comparing said DC output voltage signal with a reference voltage signal (114) and to output a drive signal (116) according to the result of said comparison, - a buffer (118) adapted to receive the drive signal (116) and a voltage signal (120) to be supplied in accordance with the DC input voltage signal to a switching element of said semiconductor switch.
    [2]
    A DC-DC converter circuit according to claim 1, wherein said first setting means comprises at least one circuit with matched resistors.
    [3]
    A DC-DC converter circuit according to claim 1 or 2, wherein said first setting means comprises a push-pull output stage.
    [4]
    The DC-DC converter circuit according to any of claims 1 to 3, wherein said control block further comprises a start circuit adapted to control the pulse width of said drive signal during the start-up of the DC-DC converter circuit.
    [5]
    A DC-DC converter circuit according to any one of the preceding claims, wherein said control block further comprises circuits for limiting current through said semiconductor switch.
    [6]
    The DC-DC converter circuit according to any one of claims 1 to 5, wherein said voltage pass element is a diode element.
    [7]
    A DC-DC converter circuit according to any one of claims 1 to 5, wherein said voltage pass element is implemented as a second semiconductor switch comprising a second multiple number of switching elements
    [8]
    8. Circuit comprising a DC-DC converter circuit according to one of the preceding claims, comprising an inductor via which a DC battery voltage signal can be applied.
    [9]
    A circuit comprising a DC-DC converter circuit according to any one of claims 1 to 7, and a switched output stage adapted to be supplied with said DC output voltage signal from said DC-DC converter circuit.
    [10]
    The circuit according to claim 9, wherein said switched output stage is arranged as a class D amplifier.
    [11]
    The circuit according to claim 9 or 10, wherein said switched output stage further comprises switching elements to bring said DC output voltage signal to another voltage level
    [12]
    The circuit according to claim 11, wherein at least two of said further switching elements are provided with inversely connected diodes to prevent leaks.
    [13]
    The circuit of any one of claims 8 to 10, further comprising a clamping circuit for electrostatic discharge.
    [14]
    A circuit according to claim 11, wherein said electrostatic discharge clamping circuit comprises a plurality of electrostatic discharge terminals, wherein a clamping voltage signal can be generated at said at least one medium voltage signal level.
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    同族专利:
    公开号 | 公开日
    GB201122265D0|2012-02-01|
    WO2013034509A1|2013-03-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US4367421A|1980-04-21|1983-01-04|Reliance Electric Company|Biasing methods and circuits for series connected transistor switches|
    US4459498A|1980-07-09|1984-07-10|Siemens Aktiengesellschaft|Switch with series-connected MOS-FETs|
    US4900955A|1987-05-06|1990-02-13|Sanders Associates, Inc.|Voltage sharing circuit|
    US9793892B2|2016-03-10|2017-10-17|Peregrine Semiconductor Corporation|High speed and high voltage driver|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US201161532731P| true| 2011-09-09|2011-09-09|
    US201161532731|2011-09-09|
    GB201122265|2011-12-23|
    GB201122265A|GB201122265D0|2011-12-23|2011-12-23|DC-DC Converter circuit|
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