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    • 专利摘要:

    公开号:BE1020440A5
    申请号:E2012/0442
    申请日:2012-06-29
    公开日:2013-10-01
    发明作者:Guy Meynants
    申请人:Cmosis Nv；
    IPC主号:
    专利说明:

    PIXEL MATRIX WITH INDIVIDUAL CONTROL OF THE EXPOSURE TIME FOR A PIXEL OR A FIELD OF PIXELS
    DOMAIN OF THE INVENTION
    This invention relates to pixel structures and to matrices of pixel structures that can be used in applications such as image sensor.
    BACKGROUND OF THE INVENTION
    Image recorders can be designed with an array of active pixels that use a semiconductor process such as CMOS. A known type of active pixels is a 4-transistor (4-T) pixel-This-pixel-type-is shown in the figure. 1, ........
    and comprises a photosensitive element such as a photodiode PD, a buffer amplifier (source follower) sf, a reset switch res with a control line RES and a selection switch sel with a control line SEL. This pixel contains a voltage conversion element, also called a floating diffusion fd. A transfer gate tr forms a connection between the photosensitive element PD and the charge conversion element fd. The exposure time in a four transistor (4T) pixel is controlled by the transfer line. Before the start of the exposure time, the transfer line is pulsed when the floating diffusion is held in its reset state. Typically, the transfer line is a horizontal line of the pixel matrix that is connected to a row of pixels in the matrix. This means that the exposure time will start at the same time for all pixels connected to the same transfer line.
    In some applications, it is preferable to be able to use a different exposure time for different areas in the image. An exemplary application in the field of automotive applications is described. in US 2009 / 0225189A1 and an example of a star follower used for navigation in spacecraft. is described in O. Yadid-Pecht, et al, "CMOS Active Pixel Sensor Star Tracker with Regional Electronic Shutter," IEEE Journal of Solid State
    Circuits, full. 32, no. 2, Feb. 1997, p. 285-288.
    The article by O. Yadid-Pecht describes a technique for individually controlling the exposure time per pixel. This is applied to a classic three transistor (3T) active pixel. A series switch is connected between the reset control line and the gate of the reset transistor in the pixel.
    SUMMARY OF THE INVENTION
    The invention seeks to control the exposure time of a pixel structure in an alternative manner, and also relates to the pixel structure with provisions for controlling exposure time.
    An implementation of the invention provides a pixel matrix comprising a plurality of pixel structures. Each pixel structure comprises a photosensitive element to generate a generic response to incident light and a charge conversion. ... - element; a first transfer port and a second transfer port connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a feed line; and an output stage. A first transfer port control line is connected to the first transfer ports of a first sub-set of pixel structures in the matrix; and a second transfer port control line is connected to the second transfer ports of a second sub-set of pixel structures in the matrix. The first sub-set of pixel structures and the second sub-set of pixel structures partially overlap, and have at least one pixel structure in common.
    In another implementation, a matrix of pixel structures is provided, each pixel structure consisting of a photosensitive element to generate charge in response to incident light, a charge conversion element, a first transfer port and a second transfer port connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a supply line and an output stage, this matrix comprising: operating features such as control logic for the first gates of a first sub-set of the pixel structures in the matrix; and operating features such as control logic for the second gates of a second sub-set of the pixel structures in the matrix for a period at least partially overlapping with the operation of the first transfer ports, the first sub-set of pixel structures and the second sub-set set of pixel structures partially overlapping, and having at least one pixel structure in common.
    All the pixel matrices described above can be combined with the elements of any of claims 2 to 15.
    An advantage of the pixel matrix is that the pixel structures in the matrix can have different exposure times.
    A pixel structure can be reset when both control lines for the transfer ports, and therefore both the first and the second transfer port, are activated at the same time as when the reset stage is activated.
    This determines the start of the exposure time. Preferably, a reset control line is associated with the reset stage, for example, in a first sub-set of pixel structures and a second sub-set of pixel structures.
    Since the transfer port control lines are connected to different sub-sets of pixel structures, these different sub-sets can be controlled differently.
    The exposure time can be controlled separately for a sub-set (for example, an area) of pixels or individually for each pixel, if required, by appropriate configuration of the transfer port control lines and the control logic that controls the transfer port control lines.
    Advantageously, the first sub-set of pixel structures and the second sub-set of pixel structures have only one pixel structure in common. This makes it possible to check the exposure time of each pixel individually.
    Advantageously, the first sub-set of pixel structures and the second sub-set of pixel structures are perpendicular to the matrix. The first sub-set of pixel structures can be a row or a column of the matrix, and the second suh-set of the pixel structures can then be the column or the row of the matrix. A transfer port control line runs along a row of the matrix, and another transfer port control line runs along a column of the matrix.
    In at least one implementation, the first and the second transfer port are connected in series between the photosensitive element and the charge conversion node. A pixel structure can be reset when both transfer port control lines, and therefore both transfer ports, are turned on at the same time when the charge conversion node is held in reset.
    This determines the start of the exposure time. Charge is transferred from it. - * photosensitive element to the charge conversion node when both transferperort. control lines, and therefore both transfer ports, are switched on. {"This defines the end of the exposure time. Preferably: the charge conversion node is not kept reset at this time.
    In at least one implementation, the first and the second transfer port are connected in series between the photosensitive element and a power supply line. When both the first and the second transfer rate are - switched on, - the pixel structure is reset. -This defines. the start of the ------ exposure time of the pixel. An additional transfer port can be provided at the conventional position between the photosensitive element and the charge conversion node.
    The pixel matrix comprises a plurality of first transfer port control lines, each connected to a respective first sub-set of pixel structures, and a plurality of second transfer port control lines, each connected to a respective second sub-set of pixel structures.
    Advantageously, the output stage of each pixel structure comprises a selection switch. One of the transfer port control lines can be connected to the selection switches in the same sub-set of pixels as the transfer port control line. This has the advantage that the number of control lines in the pixel matrix is not increased.
    Advantageously, the second transfer port is connected to the charge conversion element. The pixel matrix further provides control logic provided for checking the pixel structures in a mode where charges transferred from the photosensitive element are stored on a combination of the second transfer port and the charge conversion element. This provides an operating mode with a high capacity, or an In-conversion converter.
    Advantageously, the voltage on the second transfer port is higher than.
    on the first transfer port. This makes it easier to transfer charge from the photo diode to the charge conversion node, and prevents charge from flowing back to the photo diode when the gates are turned off.
    Implementations of the present invention provide a method to control an exposure time of a first pixel structure in a matrix of pixel structures, wherein each pixel structure has a photosensitive element to generate charge in response to incident light, a charge conversion element, a first transfer port and a second transfer port transfer port connected in series between the photosensitive element and the charge conversion element, or between the photosensitive element and a power line, and includes an output stage. The method may include: driving a first transfer port control line connected to the first ports of a first sub-set of pixels in the matrix; and .
    ------- driving-from-a-second-transfer-port-control--connected-to the second --------------- ports of a second sub-set of pixel structures in the matrix for a period that at least partially overlaps with driving the first transfer port control line, the first sub-set of pixel structures and the second sub-set of; pixel structures partially overlap, and at least one pixel structure. have in common. : "
    In each of the implementations, the pixel structure may be a semiconductor pixel structure formed by a process such as CMOS.
    BRIEF DESCRIPTION OF THE DRAWINGS
    Implementations of the invention will be described by way of example only, with reference to the accompanying drawings, in which:
    Figure 1 shows a four transistor (4T) active pixel; · ".
    Figure 2 shows a pixel structure according to an implementation of the present invention with two transfer ports connected in series;
    Figure 3 shows a timing diagram illustrating the operation of the pixel structure of Figure 2;
    Figure 4 shows the architecture of an image sensor according to an implementation of the present invention with pixels of the type shown in Figure 2;
    Figure 5 shows routing of control, power, and output lines of the pixel of Figure 2;
    Figures 6 and 7 show alternative routing for the control, power, and output lines, with the selection control line shared with one of the transfer port control lines;
    Figure 8 shows a cross-section of the pixel structure of Figure 2;
    Figures 9 and 10 show potential diagrams during the operation of the pixel structure of Figure 2;
    Figure 11 shows a timing diagram for the operation of the pixel structure - -vaa-figttttf-2 ·; ----------------------------- --------------------------------—----------------- -------------------------
    Figure 12 shows the operation of the transfer gates to improve charge transfer;
    Figure 13 shows two possible read modes for the pixel structure of Figure 5;
    Figure 14 shows the use of a readout mode with low conversion factor to read out a large load packet;
    Figure 15 shows a variable control of the potential of the transfer port;
    Figures 16 to 18 show timing diagrams for reading the. pixel structure;
    Figures 19 to 23 show pixel structures capable of global shutter operation;
    Fig. 24 shows a pixel matrix and a controller;
    Figure 25 shows exposure control of areas from a pixel matrix;
    Figures 26 and 27 show another 4T pixel structure with exposure time control provided by an additional switch connected between the transfer port control line and the transfer port.
    DESCRIPTION OF PREFERENTIAL IMPLEMENTATIONS
    The present invention will be described by means of specific implementations and with reference to certain drawings, but the invention is not limited thereto, but only by the claims. The described drawings are only schematic and not restrictive. In the drawings, the size of some elements may be exaggerated and not drawn to scale for illustrative purposes. When the term "comprising" is used in this description and in the claims, it does not exclude other elements or steps. In addition, the terms first, second, third, and the like are used in the description, and the claims to distinguish between similar elements and not.
    *. *. f 'necessary to describe a sequence or a chronological order. It is to be understood that the terms so used are interchangeable under suitable conditions and that the implementations of the inventions described herein are capable of operating in sequences other than those described or illustrated herein.
    Figure 2 shows a pixel structure according to an implementation of the present invention. The pixel structure is a modified 4T (four transistor) pixel comprising a photosensitive element PD such as a pinned diode, a reset switch res with a control line RES, a buffer amplifier (source follower) sf and a selection switch sel with a control line SEL. The pixel includes, a charge conversion element, also called a floating diffusion fd. Two transfer ports TRX and TRY are connected in series between the photosensitive element PD and the charge conversion element fd. The first transfer port TR1 is connected on one side to the photo diode PD and on the other side to the second transfer port TR2.
    The second transfer port TR2 is adjacent to the first transfer port TR1 and the charge conversion element fd. An output stage of the pixel comprises the buffer amplifier sf and the selection switch sei. Each of the transfer ports TR1, TR2 is connected to a control line TRX, TRY which controls the operation of the port. Control lines TRX, TRY are connected to a plurality of pixels in the matrix, in an advantageous implementation, control line TRX is connected to the; transfer ports TRI in a row of pixels of the matrix and is control line TRY
    connected to the transfer gates TR2 in a column of the pixel matrix. Each of the individual pixels of the matrix can be checked individually by ‘a combination of the TRX and TRY control lines. There is a control line TRX for each row of pixels in the matrix, and a control line TRY for each column of pixels in the matrix. Control logic checks the operation of the control lines TRX, TRY and other lines RES, SEL of the pixel matrix. Logic can control an individual pixel, or can control multiple pixels (or an area of interest). This makes it possible to reset photo diodes only on specific pixels or for specific areas in the pixel matrix, and thus to control the exposure time for each pixel or area separately. In addition, it is possible to control the end time of an exposure of a pixel by turning on TR1 and TR2 at a specific time, by using transfer gates TR1 and TR2 between the photodiode PD and the wobble-diffusion fd.-This however, the last effect is not - -. possibly when the two ports connected in series are connected to the power supply line.
    Figure 3 shows a timing diagram for the operation of pixels of the type shown in Figure 2. At the start of the exposure time of a specific pixel, the photodiode is completely depleted by switching on TR1 (via the control line TRX) and TR2- ( via the TRY control line) at the same time as switching on the reset switch res. This also resets the floating diffusion fd. This operation can be checked individually, per pixel. Figure 3 shows how different pixels in the matrix are checked. A first pixel (row y, column 1) is checked so that the pixel is reset and its exposure time begins. A second pixel (row y, col2) of the matrix is then checked so that the pixel is reset and its exposure time begins. In practice, the vertical transfer port control line TRX is set high on a pixel of a row to be reset. Then the horizontal transfer line TRY is pulsed together with the reset line RES to deplete the photo diode and start the exposure for the selected pixels. This can be done at different times for different pixels of the same row.
    The readout will now be described. The floating diffusion becomes fd first. - reset by a pause on the RES line. The reset level is sampled in a column around the image sensor's amplifier. Then the charge is transferred to the floating diffusion for the pixels whereby both transfer gate control lines are pulsed high. All pixels in a given row can be read out at the same time, each via a respective column read line, as shown in Figure 3. Pixel (row y, coll) has a longer exposure time than pixel (row y, col 2).
    Alternatively, pixel in different columns of a given line can be read out at different times if necessary. It is also possible to read different columns at different moments in time and thus generate a high-speed readout with a short exposure time for an area of pixels, and at the same time do a slow readout of an area of pixels with a longer exposure time.
    - Figure 4 - shows - an - architecture - - of - an - image sensor, where - the .......
    the image sensor comprises a pixel matrix 40, which is read out at a regular image frequency (for example, 30 images per second). The pixels can be of the type shown in Figure 2 or another pixel type described in this text.
    In an implementation of the invention illustrated in Figure 4, 4 areas of pixels 42 can be read out at much higher speed (e.g. 300 or 3000 times per second). This can be used, for example, to measure the average exposure signal during the exposure of the injured pixels in the matrix. This readout can be destructive, thereby destroying the load that is. integrated in the pixels. This will be the case with buried photodiodes ("pinried. Photodiodes"). The pixels in the area 42 are reset during each read-out.
    To read out the pixels are, by way of advantage, two driving logic control circuits. provided, a 222.223 on the left, and a 220, 221 on the right of the pixel matrix. The two row control logic circuits control which rows were read and / or reset during the reading of an image. The row logic on the right side of the pixel matrix can be composed of a row of address register 220 and a shift register 221. The row of address register 220 indicates which rows are read out for the full resolution, low speed, readout. If a log 1 is written in the register of the row, this row is read out. If a logical "O" is written in the register of the row, the shift register 221 will skip this row. For a full resolution readout, a logical "" is written in each line in the full register 220. The shift register 221 will then, advantageously, scan through the entire pixel matrix. The shift register 221 controls horizontal control signals in the pixel matrix 40 via control lines 26. These may include signals to reset the row of pixels and one of the two transfer gate signals TR1. The other transfer gate signal TR2 'is driven by control lines 25. These are advantageously driven vertically from a column address register 210 or 211. These column address registers control which columns are read (and / or reset) when the. ·.
    image is read (and / or reset). Column address register 221 can. are used for reading the full image in the preview. When TR1 is driven via register-220, then TR2 is controlled via register-21-1. For a -------- fast image readout, the horizontal control lines 26 of the row address register 222 and the row address are controlled. shift register 223. In this example, only four rows # have a logical '1' in their left-hand row address register 222. Only these four rows will be read out in the fast readout cycle. Column address register 210 can be used in connection with the row shift register and row logic 223 and row address register 222. The column address register 210 checks which columns are read and reset during the fast read cycle. In this example, only four columns contain a logical "" in their column register. Only these four columns. . used in reading the fast image. This results in four areas of veto pixels · 42, each containing 2x2 pixels, which are read out. The pixels can also be reset during the readout. The exposure time of these 16 pixels can therefore be very short. The exposure time of the other pixels of the pixel matrix 40 can be much longer. During reading of the entire image, the pixels in regions 42 can also be read again. They will have a much smaller signal in this case. Figure 4 further shows output circuits 30 comprising a multiplexer 33 and an output amplifier 34 which can be used to read and multiplex the signals from the column of output lines. Multiplexer 33 can be assembled from a column amplifier, a shift register and an analog multiplexer to an output bus. The shift register in multiplexer 33 can preferably address only the columns that have a logic in column registers 210 and 211. It is also possible to replace the analog multiplexer with a column AD converter and a digital multiplexer.
    When multiple pixels are read out at the same time, the transfer pulses need not necessarily be the same in shape. Instead, the transfer pulses should only overlap for a portion of the time. For reading it is advantageous to keep TR2 at (high), because this increases the capacity of the floating diffusion fd. This is useful for reading out large load packages.
    It is possible to keep TRI on (high) during the exposure time.
    • This increases the capacity of the photodiode, but has the disadvantage that it. dark current is considerably higher. This is because the transfer port is typically a surface channel transistor and the charge packet in the photodiode is then not shielded from the surface.
    Preferably, when TRI. is switched on (high), it is no longer switched off before TR2 is switched on. - This prevents charge from flowing back to the photo diode.
    If the addressing logic and readout logic for TRX and TRY support it, more than two exposure times can be implemented for different pixels in the matrix.
    Figure 5 shows a possible routing of the transfer port control lines. TRX, TRY together with the select control line SEL, reset control line RES, output line OUTPUT and supply line VDD.
    Figures 6 and 7 show two alternative configurations in which one of the two transfer gate control lines TRX / TRY is shared with the selection control line SEL. This has the advantage that the number of check lines required for routing across the pixels is reduced.
    Figure 6 shows a control line TRY / SEL, which is connected to the first. transfer gate TR1, adjacent to the buried photodiode PD, and the selector switch SEL. This configuration provides the charge conversion node fd with the lowest possible capacity and the highest possible conversion factor, which is advantageous for a lower noise readout.
    Figure 7 shows a control line TRY / SEL which is connected to the second transfer gate TR2 and the selection switch. Hereby, the capacity of the charge conversion node fd is larger during the readout (when SEL is on). This is advantageous in the case when a large load packet has to be read out.
    Fig. 8 shows a cross-section of the layers in the semiconductor which form the photodiode PD, the transfer gates TR1, TR2 and the charge conversion node fd.
    Figures 9 and 10 show potential diagrams during a first (standard) operating mode of the pixel of Figure 8. Figure 11 shows the timing of the - pi-xel-in-standard operating mode. - Figure 9 (a) - shows - the - start of ~, a - exposure period. Transfer ports TR1 and TR2 are switched off (low potential). Charges are accumulated on the photodiode PD during an exposure period. The amount of accumulated charge is proportional to the light intensity of the light incident on the pixel.
    Figure 9 (b) shows the end of the exposure period with TR1 and TR2 still switched off (low potential). An amount of charges has been accumulated on the photo diode PD. The reset level of the floating diffusion can be read. This is the reference level of the pixel.
    Transfer port TRI is now switched on (high potential). Figure 9C shows the end of the exposure time with TR1 on and TR2 off. Charge is at least partially transferred from the photodiode to TRI.
    Both transfer ports TR1, TR2 are switched on (high potential). Figure 10 (a) shows TR1 and TR2. Charge has been transferred to the charge conversion node fd.
    Figure 10 (b) shows the readout of the signal. Transfer ports TR1 and TR2 are now off (low potential) to prevent further charge from reaching the charge conversion node.
    An additional reset can be performed (if required) before the start of the next exposure period. This is shown in Figure 10 ©. TR1, TR2 and RES are switched on (high potential). This extra reset may be required. to remove remaining charge on the photo diode. It may also be necessary to define the start of the next exposure period.
    Preferably, for a better charge transfer, the high level on the second transfer port TR2 is higher than on the first transfer port TR1. This makes it easier for the charges to move to the floating diffusion fd, due to the lateral electric field. This is shown in Figure 12.
    Modulation of the load conversion node capacity
    Figure 13 shows an advantageous feature. The transfer port TR2 adjacent to the charge conversion element fd can be controlled to modulate the capacity of the charge conversion node fd, - this - provides a - pixel - with - two charge conversion factors in standard 4T mode: low gain (high capacity) -) mode in which the transfer port TR2 is switched on (at high potential); and a high gain (low capacity) mode in which the transfer port TR2 is turned off (low potential).
    Figure 13 (a) shows the high gain mode. This is useful in low-light situations. Figure 13 (b) shows the low gain mode. This is optimized for the full charge of the photo diode. A larger load package can be read. Figure 14 illustrates this. In Figure 14, a large charge packet cannot be stored on the floating diffusion when TR1 and TR2 are off. However, the same charge package can be stored on the floating diffusion when TR2 is switched on.
    The gain in low gain mode is determined by the size of the transfer port. The size of the TR2 port can be selected to store a foreseen amount of loads. It is also possible to change the voltage on TR2 to adjust the relative depth of the charge package. This is shown in Figure 15.
    Each of the above logs can be combined with a variable exposure time for the pixels. It is possible to take two readings from the pixel: a reading with low gain and a reading with high gain.
    Figures 16 to 18 show possible readout schemes. Figure 17 shows a timing diagram for a case with two samples. The floating diffusion is first reset, and this reset level is read. Then charge is transferred via TR1 and TR2 to the floating diffusion and TR1 and TR2 are both switched off again. The signal on the floating diffusion is then read. The TR1 'and TR2 ports are then again high pulsed to perform a second charge transfer. The remaining charge from the photodiode will transfer to the floating diffusion and the TR2 port. TR1 is then switched off again, and the signal is then sampled with a low conversion factor, determined by the capacity of the TR2 port and the floating diffusion. Both samples can be referenced to the reset level of the drifting diffusion for the first charge transfer. Correlated double sampling can be applied to both samples by subtracting this reset level from both sampling levels. This eliminates the reset (kTC) noise of the signals.
    Optionally, there may be an additional reset pulse between the first and second charge transfer period. In that case, the intermediate reset level must be read out to do correlated double sampling on the second sampling (with the low conversion factor). This is shown in Figure 18.
    The pixel can also be used only with low gain. The timing for this mode is shown in Figure 16.
    Combination with a global shutter
    The pixel can also be combined with a global shutter. A number of possible ways are shown in Figures 19 to 23.
    Figure 19 shows a pixel with four transfer ports: TRX, TRY, TRS, TRR, placed in series between photo diode PD and charge conversion node fd. A further gate VAB is connected between the photo diode PD and the power line VDD. Start of the exposure is controlled by pulsing VAB. Alternatively, the start of the exposure can be controlled by raising the four adjacent transfer ports and resetting the charge conversion node (fd). At the end of the exposure period of a pixel at location (x, y), the horizontal and vertical transfer control lines controlling TRY and TRX respectively are set high. TRS is also set high, at a higher voltage. Electrons accumulated on the photo diode PD will transfer from the photo diode to the TRS port. During readout, first, the charge conversion node FD is reset and the reset level is sampled in the readout circuit. Then it becomes. TRR is pulsed to cause the electrons to move to the charge conversion node, and the charge conversion node fd is resampled. This pixel allows a combination of correlated double sampling (CDS) and an individual check of the pixel exposure time. Except control over ......
    at the start of the exposure time, VAB is also used as a horizontal anti-overexposure drain to drain charge from the photodiode in the event of overexposure. Advantageously, the low level of VAB is chosen so that this port is an effective anti-overexposure drain. works. The low level of VAB will then be higher than the low level of TRX or TRY .---------
    Figure 20 shows an alternative implementation. It provides a global shutter functionality with correlated double sampling. The pixel has three transfer ports: TX, TS, TR, placed in series between photo diode PD and charge conversion node fd. Ports VABX and VABY are connected in series between the photo diode PD and the supply line VDD. To control the start of the exposure, the adjacent ports VABX and VABY are pulsed together. VABX is controlled by a vertical control line and VABY is controlled by a horizontal control line. The photo diode is only reset when both lines are high. The low level of VABX and VABY is chosen so that both gates act as an anti-overexposure drain.
    Figure 21 shows an implementation of the same regional shutter control, using two adjacent transfer ports, but now as an addition to a 5-transistor global shutter pixel as described in U.S. Patent 7,045,753. The two series-connected ports VABX, VABY. are used in the same way as in Figure 19.
    Figures 22 and 23 show other implementations of global shutter pixels that are adapted to have two serially connected transfer ports. use. In Figure 22, the added ports are TRX, TRY. In Figure 23, the added ports are VABX, VABY. The pixels are described in detail in United States Patent Application US 2009 / 256060A1, the contents of which are incorporated herein by reference.
    Fig. 24 shows an apparatus 10 for a pixel matrix 40. A pixel matrix 40 comprises a plurality of pixels 41 of each of the types described above.
    - Controller-20- controls, de-operation-pixel-matrix-40-and the output pixels -...
    30. Controller 20 includes column selection / line control circuits 21 to generate control signals on control lines 25 aligned with columns of the matrix, and row selection / line control circuits 22 to generate control signals on control lines 26 aligned with rows of the pixel matrix . The signals 25, 26 drive pixels 41 in the matrix 40. Controller 20 checks: resetting the pixels to control the start of an exposure time (including operation of the transfer gates TR1, TR2); operation of the transfer gates TR1, TR2 to transfer charge to the floating diffusion fd; operation of the switches res, sei to control the reading of a pixel. ; ;
    Example timing schedules for the control signals are shown. The pixel matrix can be read out in a conventional manner, with pixels being scanned on a row-by-row basis. Alternatively, controller 20 may perform a global shutter function by synchronous operation of the control signals which respectively control the exposure times of each of the pixels in the matrix. Controller 20 also has control logic 23 to control the operation of output circuits 30. The control logic of controller 20 can be stored in hard coded form, such as in an Application Specific Integrated Circuit (ASIC), or it can be stored in some form of reconfigurable processor, such as a logic array (programmable array, reconfigurable array) or a processor that executes software. All elements shown in Figure 24 can be provided on a single semiconductor substrate or the elements can be distributed on several separate substrates. Output circuit 30 may provide column processing circuits 32 assigned to each column, such as: an analog-to-digital converter (ADC), one or more amplifiers, storage to store values, to perform functions such as correlated double sampling (CDS). . Output circuit 30 outputs a signal 35.
    Figure 25 shows an implementation of the row and column logic 21, 22 that permits a regional shutter function. Different shift registers are implemented in the row logic (left / right of the pixel matrix) and the column logic (top / bottom - of the pixel matrix) - The SG shift registers are loaded with a pattern-that-the-rows and identifies columns to be read for exposure. In a global shutter operation, the pixels are reset by driving the TRY lines directly by the contents of one of the shift registers in the row logic, and driving the TRX lines directly by the contents of one of the shift registers in the column logic. At different moments in time, areas of pixels are reset by driving the TRX and TRY lines through the corresponding shift registers. For a rolling shutter operation, the driving logic includes additional logic to combine the contents of the shift registers with the reset pulse, which is generated by a single pulse.
    Another implementation of an exposure control for a 4T pixel will now be described with reference to Figures 26 and 27. A switch is added between the transfer control line TR and the transfer port. A switch between the transfer control line TR and the transfer port is used to select the pixels that are controlled by the transfer control line. In the event that a pixel does not require a charge transfer, the transfer pulse will be suppressed by opening the switch between the transfer control line and the transfer port. Figure 26 shows the timing of this pixel. The transter gate will remain floating during this time. Since the transfer time is only switched on for a short time (less than 10 microseconds), it won't hurt to keep the port floating for a short time. If this is nevertheless a concern, or if the transfer port must be switched on for a longer period of time, an additional switch can be provided which pulls the port to a low voltage (for example GND). However, this is typically not necessary.
    This implementation has a disadvantage because the transfer port must be placed at a high voltage to guarantee a good charge transfer. The high level of the transfer port must be at least as high as the sum of the depletion voltage of the photodiode and the threshold voltage of the transfer port.
    Only NMOS transistors can be used in the pixel. The switch between the transfer control line and the transfer port is an NMOS transistor. The gate of this transistor must be driven to a voltage that is considerably higher than the transfer port - in order to stand up to the high level of the 4th transfer port control line at ------- the transfer port ends up. Because the maximum voltage that can be applied to the switching transistor is practically limited, the highest voltage that can be applied to the transfer port is also reduced. The other implementations described in this document do not have this limitation.
    The invention is not limited to the implementations described herein, which can be changed or varied without departing from the scope of the invention.
    权利要求:
    Claims (18)
    [1]
    A pixel matrix comprising: a plurality of pixel structures, each pixel structure comprising: a photosensitive element to generate charge in response to incident light; a charge conversion element; a first transfer port and a second transfer port connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a feed line; an output stage; a first transfer port control line connected to the first transfer ports of a first sub-set of pixel structures in the matrix; a second transfer port control line connected to the second transfer ports of a second sub-set of pixel structures in the matrix, the first sub-set of pixel structures and the second sub-set of pixel structures partially overlapping, and having at least one pixel structure in common, and wherein the photosensitive element comprises a buried photodiode (ENG: "pinned photodiode").
    [2]
    A pixel structure according to claim 1, wherein the first sub-set of pixel structures and the second sub-set of pixel structures have only one pixel structure in common.
    [3]
    A pixel structure according to claim 1, wherein the first sub-set of pixel structures and the second sub-set of pixel structures are arranged perpendicularly in the matrix.
    [4]
    A pixel structure according to claim 2, wherein the first sub-set of pixel structures is a row or a column of the matrix, and the second sub-set of pixel structures is a column or a row of the matrix.
    [5]
    A pixel structure according to claim 1, wherein there is a plurality of first transfer port control lines, each connected to a respective first sub-set of pixel structures and a plurality of second transfer port control lines, each connected to a respective second sub-set of pixel structures.
    [6]
    A pixel structure according to claim 1, wherein the output stage of each pixel structure comprises a selection switch and wherein one of the transfer port control signals is connected to the selection switches in the same sub-set of pixel structures as the transfer port control line.
    [7]
    A pixel structure according to claim 1, wherein the second transfer port is connected to the charge conversion element and the pixel matrix further provides control logic configured to read one of the pixel structures in a mode where charge transferred from the photosensitive element is stored on a combination of the second transfer port and the charge conversion element.
    [8]
    A pixel structure according to claim 1, further comprising control logic which is configured to read out one or more pixel structures in a mode in which charge transferred from the photosensitive element is only stored on the charge conversion element.
    [9]
    A pixel structure according to claim 1, wherein the second transfer port is connected to a charge conversion element, and wherein the second transfer port has a higher potential level than the first transfer port when the transfer ports are used.
    [10]
    A pixel structure according to claim 1, wherein each pixel provides a reset stage to reset the charge conversion node and wherein the pixel matrix further provides control logic configured to control the start of an exposure period by turning on the first transfer port and the second transfer port at the same time as using the reset trap.
    [11]
    A pixel structure according to claim 1, wherein a reset control line is connected to the reset stage in one of the first sub-set of pixel structures or the second sub-set of pixel structures.
    [12]
    A pixel structure according to claim 1, further comprising control logic configured to control the end of an exposure period of one of the pixel structures by using the first transfer port control line and the second transfer port control line to transfer charge from the photosensitive element to the load conversion element.
    [13]
    A pixel structure according to claim 1, wherein the first transfer port and the second transfer port are connected in series between the photosensitive element and a feed line, and wherein each pixel structure has at least one additional transfer port connected between the photosensitive element and the charge conversion element.
    [14]
    A pixel structure according to claim 1, further comprising control logic which is configured to control the first transfer port control line and the second transfer gate control line.
    [15]
    A pixel structure according to claim 14, wherein the control logic is configured to activate both the first transfer port control line and the second transfer port control line for a period that at least partially overlaps.
    [16]
    A pixel matrix comprising: a plurality of pixel structures, each pixel structure comprising a photosensitive element to generate charge in response to incident light, the photosensitive element comprising a buried photodiode (a pinned photodiode), a charge conversion element, a first transfer port and a second transfer port connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a power line, and an output stage, the matrix comprising: a first control logic for controlling first ports of a first sub-set of the pixel structures in the matrix; and a second control logic for controlling second ports of a second sub-set of the pixel structures in the matrix for a period at least partially overlapping with the control of the first transfer port control line, wherein the first sub-set of pixel structures and partially overlap the second sub-set of pixel structures, and have at least one pixel structure in common.
    [17]
    A method of checking an exposure period of a first pixel structure in a matrix of pixel structures, each pixel structure comprising a photosensitive element for generating charge in response to incident light, the photosensitive element having a buried photodiode (ENG: "pinned photodiode") ), a charge conversion element, a first transfer port and a second transfer port connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a power line, and an output stage, the method comprising: driving a first transfer port control line connected to the first gates of a first sub-set of pixel structures in the matrix; and driving a second transfer port control line connected to the second ports of a second sub-set of pixel structures in the matrix for a period at least partially overlapping with the driving of the first transfer port control line, wherein the first sub-set of pixel structures and the second sub-set of pixel structures partially overlap, and have at least one pixel structure in common.
    [18]
    A method according to claim 17, wherein the steps of driving the first transfer port control line and driving the second transfer port control line define the start of an exposure period for the first pixel structure, and wherein a second pixel structure in the matrix has a different exposure period.
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    GB1111158.0A|GB2492387B|2011-06-30|2011-06-30|Pixel array with individual exposure control for a pixel or pixel region|
    GB201111158|2011-06-30|
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