• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a system for testing an input signal (100). The system comprises - a test signal generation block (103) which produces a test signal (25) based on test parameters obtained from input signal analysis, - an input circuit (101) comprising means for superimposing said test signal (25) on said input signal (100), - a test interface (102) in connection with said input circuit and adapted to analyze characteristics of the input signal and test signal, - a test control unit (105) in connection with said test interface (102) and said test signal generation block (103) and arranged for the define updated test parameters.
    公开号:BE1020310A5
    申请号:E2012/0097
    申请日:2012-02-16
    公开日:2013-07-02
    发明作者:Carl Eeckhout；Bram Baert
    申请人:Televic Rail Nv；
    IPC主号:
    专利说明:

    SIGNAL TEST CIRCUIT AND METHOD Field of the invention
    The present invention relates to the field of circuits for testing input signals and methods for performing testing of such input signals.
    BACKGROUND OF THE INVENTION
    In numerous applications, and in particular in safety applications, it is essential to test input signals before using them in their application, or to test the circuit during the application. The testing of these interfaces often takes place by applying a reference signal to the input by changing the circuit input path. By doing this, a disconnection from the original input path is made.
    In some cases, however, the condition of the original entry path is unknown; therefore, it is considered a risk to switch the input path to another source, since it cannot be guaranteed that switching back to the original source will occur correctly, or that conclusions regarding the disconnected part are relevant.
    Furthermore, it is desirable to be able to verify the input switching system also during online operation. By using route-disrupting verification techniques, the signal of interest can no longer be checked and functionality as such ceases.
    Known solutions rely on a hard switch from the input connection to a reference signal. In these cases, when the input path is opened, a correct switch back to the original input path after the test is not guaranteed can be guaranteed. Furthermore, the prior art solutions do not allow continuous monitoring of the input circuit with regard to signal continuity, signal level and, for example, digitizer interface accuracy.
    Moreover, there is no methodology to implement testing of specific parameters in an intelligent and structured way to allow a reduction of the test components, which provides for certain compensations on the output stages as a function of test operations delivered on the input stage.
    Accordingly, there is a need to overcome the drawback of having to disrupt the original input path while input signal measurement is being performed. There is also a need for one! intelligent solution to determine the correct behavior of the input circuits and the input signal itself. Closely related to this, there is a need for reporting problems (error, warning) and acting on the output signal.
    Summary of the invention
    It is an object of the embodiments of the present invention to provide a solution for interface testing that leaves room for testing in a non-disruptive manner, avoiding the need to change the input path. It is a further goal to present a solution for the intelligent testing of signal parameters.
    The above object is achieved by an apparatus and method according to the present invention.
    Embodiments of the present invention obviate the drawback of having to disconnect the original input path while. input signal testing is performed. With the solution according to the invention it is clearly measurable whether the test circuit is still installed or not. If the test system is not installed, it can be guaranteed that the correct normal entry conditions apply. However, the invention also ensures that in the event the test signal is still present, the signal of interest can still be isolated from the test signal, which allows control of the analog input circuit even during normal operation.
    More specifically, the invention relates in a first aspect to a system for testing an input signal. The system comprises - a test signal generation block adapted to produce a test signal, - an input circuit comprising means for superimposing said test signal on said input signal, - a test interface in connection with said input circuit and adapted for analyzing characteristics of said input signal and said test signal - a test control unit in connection with said test interface and said test signal generation block and adapted to select additional characteristics of said test signal that are absent in said input signal.
    In the input circuit it is guaranteed that no disconnection is required to take measurements with the test signal: the test signal is superimposed on the input signal applied. In the test interface block, the superimposed test signal and input signal can be analyzed. The test control unit receives information from the test interfaces and determines specifications for the test signal to be generated. These specifications are passed to the test signal generation block, where the actual test signal is produced and output.
    In a preferred embodiment, the input circuit is a sum amplifier. Such a sum amplifier input circuit guarantees an exact compensation in the event of an error due to incorrect switching of the test signal on the input signal multiplexer. In the event that the compensation is performed digitally, in some configurations (e.g., a sum amplifier with gain factor 2), only a one-bit shift is needed to implement the appropriate gain.
    In another preferred embodiment, the input circuit is a galvanically isolated coupling.
    Preferably, the system further comprises an output stage.
    By also checking and controlling the output stage, the output stage can be brought into a "safe" state by using this generic method in case input signal problems would be detected. As such, the method not only provides clear reporting regarding a problem on the input circuit, but also provides for an adjustment of the output signal that causes an implicit superfluous effect on the evaluation of a particular signal. This excess effect can be of great importance for safety-related devices. The output stage is preferably adapted to compensate for test parameters.
    In another preferred embodiment, the test control unit is adapted to output to the output stage an indication of safe state.
    In a preferred embodiment, the system further comprises multiplexing means for multiplexing a large number of signals output by a large number of input circuits. Different input signals can thus be tested simultaneously using the same test signal. In that case, the test interface is preferably adapted to receive signals in a time division multiplexing style (or a combination of permanent, temporary or time division multiplexing). However, other multiplex solutions can also be envisaged. Preferably, the signals fed to the test interface come from the output stage or from the input circuits.
    The control block preferably comprises a test arranger for determining the order of parameters to be used.
    In a preferred embodiment, the control block is adapted to perform an algorithm for determining test parameters for the test signal. .
    The invention also presents a method for performance analysis of a signal carried across the input circuit and signal manipulation as a function of its condition, or of the tests performed to provide a reliable and interrupted signal to higher level systems. More in particular, the method for testing an input signal comprises the steps of - applying an input signal, - superimposing a test signal on the input signal, - performing an analysis on the superposition of said test signal and said input signal,
    ; I
    - determining settings for performing said testing from said analysis and deriving modifications for said test signal from said settings, - producing an updated test signal reflecting said modifications for continuing testing.
    When an assessment is started, of course only the input signal is available. The input signal is analyzed and based on that analysis, test settings and specifications for the test signal are determined. This information is supplied to the test signal generation block where the actual test signal is made. The test signal is then applied to the input circuit, where it is superimposed on the input signal. From that moment the superposition of test signal and input signal is analyzed and the test signal is further updated based on analysis of the superposition, as explained above.
    For purposes of summarizing the invention and the advantages achieved above the prior art, certain objects and advantages of the invention have been described above. It is, of course, obvious that not all such objects or advantages can be achieved in accordance with a specific embodiment of the invention.
    The above and other aspects of the invention will be apparent from, and will be explained with reference to, the embodiment (s) described below.
    Brief description of the figures
    The invention will now be described, by way of example, with reference to the accompanying figures, in which:
    FIG. 1 represents a high-level block diagram of the system according to the invention.
    FIG. 2 represents a detailed block diagram of an embodiment of the system of the invention.
    FIG. 3 represents the data connections used by the test algorithm.
    FIG. 4 represents a block diagram of an embodiment based on direct parallel sum gain.
    FIG. 5 represents a block diagram of an embodiment based on a galvanic test signal insert.
    FIG. 6 represents an example of test signal adjustment as a function of the examined input circuit parameter that allows validation of quantitative aspects of the input circuits.
    FIG. 7 represents a block diagram of an embodiment based on both a galvanic test signal insert and the parallel sum gain.
    FIG. 8 represents an actual implementation example.
    The figures are only schematic and are non-limiting. In the figures, for illustrative purposes, the format of some of the elements may be exaggerated and not drawn to scale.
    Reference characters in the claims should not be interpreted as limiting the scope.
    In the various figures, the same reference characters refer to the same or analogous elements.
    Detailed description of illustrative embodiments
    The present invention will be described with reference to specific embodiments and with reference to certain figures, but the invention is not limited thereto but solely by the claims.

    The solution presented in this invention overcomes the limitation of having to disconnect from the original input path while input signal testing is being performed. It will clearly determine whether the test circuit is still installed or not. If the test system is not installed, it can be guaranteed that the correct normal input condition applies. However, even if the test signal is still present, the signal of interest, ie the input signal, can still be isolated from the test signal, allowing control of the input signal even during normal operation: A single test signal generator and analyzer can be used. for multiple inputs. This means an optimization with regard to volume, costs and reliability. However, more than one test signal generator and analyzer can also be used.
    In FIG. 1 a general overview of the system according to the invention is provided. An input signal (100) is applied to an input circuit (101) whereby a test signal can be multiplexed on the input signal. The input signal forms the waveform under investigation. That waveform can be internal (e.g., a sine wave signal that makes it possible to verify the input circuit filter characteristics) or external (e.g., a correct external sensor signal that produces a signal level higher than 4 mA). The applied signals are processed in the input circuit. The input circuit (101) preferably includes one or more sub-circuits to adjust the signal to the requirements of the system that handles it. The signal coming from the input circuit (101) is fed to one or more test interfaces (102), with various functions being implemented for analyzing certain signal aspects. The test interface circuits are adapted to operate on the test parameters of interest and to set certain characteristics in accordance with the aforementioned (e.g. associated with filtering). The resulting signals from the test interfaces are passed on to a test control unit (105). The latter includes one or more logical units that provide a correlated test application, test analysis, test reporting, and output signal control. A test signal generation block (103) connected to the test control unit is adapted to generate an actual test signal that meets certain specifications received from the test control unit. One or more output stages (104) provide an output signal representative of the corresponding input signal or the state in which the input signal is located.
    In the test control unit (105), the settings for performing the test are prepared on the basis of a test algorithm that includes knowledge of the physical parameters of the signal, the input circuit (101) and the output stage (104). Once the test check has established the actual test parameters, the characteristics of the test signals (such as missing frequency components, or signal levels) are determined and passed to the test signal generation block (103), where the actual physical test signal to be superimposed on the input signal is generated.
    Depending on the test signal and the way in which. the test signal is modulated to the signal of interest, the output stage is regulated in such a way that the generated output signal is representative of the state of the input signal or the state in which the input circuit is located.
    The state of the output signal leaving the output stage is checked by a similar test interface as the one applied to the input signal to validate correct behavior of the output stage. In this way it can be guaranteed that the compensation of the output signal is performed correctly.
    The test control unit (105) may also include an interface to a higher level system that communicates the internal status of the test system. The test control unit can be controlled in one embodiment to start or stop certain tests.
    In some applications, the input circuit block (101) comprises only means for achieving a superposition of the input signal and the test signal, such as, for example, a multiplexer or a relay, and it is arranged to connect the resulting superimposed signal directly to the test interface. In other applications, the input circuit furthermore comprises one or more components such as a signal amplifier, an offset shifter, filters, protection devices and so on. The same can be said with regard to the output stage. In certain embodiments, the input circuit and the output stage are even controlled by the test control unit.
    In FIG. 2, a detailed block diagram of an embodiment of the system according to the invention is provided. The examined input signal (100) can come from a signal generator that can operate as an input signal source. In practice, it can be implemented as a sensor or any other type of signal generating device. The input signal can be analog or digital. Optionally, a test signal isolator (2) can be provided to establish a galvanic isolation between the test signal and the input signal. The test signal can be connected to the input signal via a multiplexer (3) under the control of the physical layer of the test signal control block (103). The input signal multiplexer block can be implemented as a multiplexer, but it can also be a modulator. Further down the signal path, the input gain of the input signal can be adjusted by an input signal gain adjustment block (4). A filter control block (5) leaves room for changing the input signal filter characteristics. In a signal quantizer (6) the analog signal is converted to a different representation. This can be an analog-to-digital conversion or even a simple threshold detection that can be important for a digital signal.
    A test signal is generated in the physical layer of the test signal control block (103), possibly together with control signals from the input switching system, based on the received input parameter (s) of the test signal. This may include - among other things - controlling the setting of the test signal multiplexer (3), the setting of the gain of the input amplifier (4) and the settings of the input filter (5). The actual test signal is generated in the test signal generator (8). The input gain control block (9) comprises input signal gain controller means for controlling the input signal gain (4) based on the input parameters (P1, P2, P3) of the test signal generator. From here, the input signal gain control outputs a signal to be applied to the gain adjustment block (4). Exactly the same can be said for the input filter control block (10). Control block (103) comprises the input signal filter control means (10) to control the filter settings of the input signal filter (5) on the basis of the input parameters (P1, P2, P3) and to output a corresponding signal to the input signal filter (5) . Controller (103) further comprises a test generator parameter check block (11) which determines the waveform of the test signal. There may be a large number of such elements that are controlled in a consistent manner by the test generator block (19) itself. The following test signal parameters can be controlled, for example: amplitude, frequency, waveform, sample table (complex signal shape), ...
    In the test interface (102), the test parameter input filter block (12) is controlled by a test parameter verification unit (.16). The filter characteristics of this test parameter input filter block (12) are set as a function of the test parameter to be checked. The main task of the test parameter input filter block (12) is to pass on the relevant input signal data in order to perform optimum verification of the test parameter (s) of interest modulated by the test generator or present in the natural behavior of the input signal. In the test parameter extractor (13), based on the input signal with respect to the test parameter of interest, a specific analysis is performed on the input signal applied. This element can, for example, determine the level of a certain frequency component, the peak value of the input circuit, ... The output of the extractor (13) is applied to a test parameter comparator (14), the extracted test parameter being verified against a predefined controlled by a test parameter estimator (17). This state is dependent on the test to be performed and can, for example, express whether a certain frequency component is present in the applied signal, whether this frequency has a certain level (<,>, =), whether a top value is met, satisfies a certain spectrum, exceeds a certain level, ... This can all be defined against specific tolerances. The test parameter analyzer (15) records the result of the test parameter comparator (14). -
    The test verification block (16) is responsible for controlling the test parameter extractor (13) and the test parameter input filter (12). It also produces the state for parameter evaluation and produces the conclusion regarding the analysis of the parameter of interest.
    The parameter estimator (17) contains the expected context to measure against the extracted parameter. The Context is applied to this element by the test verification block (16). The estimator may contain a single value, such as a threshold, but may just as well be a full spectrum, or a top value, ...
    The test control block (105) comprises a test analyzer (18), a test generator (19), a test arranger (21) and a generic test control unit (20).
    The test analyzer (18) combines the results of individual test parameter analyzers (15) in the test interfaces (102) and evaluates, depending on the condition of the test arranger (21), whether the input or the different inputs is / are in a good shape, ie whether the input circuits behave as expected. If this is not the case, an alarm will be generated. The result of this overall test analysis is reported to the generic test control block (20). The test analyzer can also verify the state of the output signal in different positions in its output stage.
    An important role in the operation of the system and more particularly of the test control block (105) is played by the test generator (19). It transmits the test parameter states to the test signal generation block (103), taking into account the information already available in the input signal and imposing additional characteristics on the test signal in order to increase the overall input signal path test coverage. He also applies test parameters based on the status of the test arranger (21) to the individual test verification blocks (16). The test generator (19) also determines the conditions to be applied to the output signal components.
    The generic test control block (20) provides an interface to a higher-order system and allows starting testing or a specific part thereof on one or more input signals. The status of the testing is reported by this block (20). This includes the state of the test items as well as the state of the selected input signals. The reporting relates to the exact type of problems detected with regard to the tested signals (eg input signal level too high) and / or the reporting with regard to the test components themselves, eg that the test signal was not visible in the analyzed signal, possibly due to an input multiplexer error. It should be noted that in certain embodiments, a higher level system can access the control block to force a test or to change test system parameters or to provide certain information (status, internal condition, alarms, warnings, parameter settings, etc.). ...). In the test arranger (21), the required input for the test analyzer (18) and the test generator (19) is produced in order to schedule a correlated execution of all individual tests on the input signals that are performed one after the other and / or in parallel. This generator also controls the output signal path to perform compensation for the tests performed or to bring the output to a "safe" state. The test arranger (21) starts a certain activity under the control of the generic test control block (20).
    The output signal filter (22) in the output stage (104) ensures that no intrusive test signal, potentially modulated on the natural input signal, remains mixed in this usable signal. The filter settings can be adjusted by the test generator (19) in view of the applied test parameters.
    The settings of the output signal amplification stage (23) can be adjusted by the test generator (19) as a function of the applied test parameters. This can be useful if the input signal level is modified by making certain input circuit settings. This can also be used to implement a certain safe state in the output signal, e.g. by increasing or decreasing the gain or applying a certain offset so that a certain effect of a higher order application can occur.
    The in FIG. 2 shows system architecture - only one embodiment of the invention. In alternative embodiments, some of the functional blocks of FIG. 2 are grouped. A scalable solution can be provided, with a repetition of blocks whether or not combined with multiplexers. Certain blocks can be repeated, in their largest or reduced form, to obtain a large number of input and output channels with only limited test items. In some embodiments, only a subset of the ones shown in FIG. 2 presented components. As already mentioned, various blocks in FIG. 2 optional.
    In a further embodiment, the test interface (102) can also be used to verify the natural behavior of the signal. This means that, given the knowledge of the typical behavior of the input signal, conditions can be defined with respect to this signal that can be checked by the test interface (102). By way of example, this is typically applicable to industry standard analogue interfaces of 4-20 mA. It is a fact for these signals that the current should not be below 4 mA and not above 20 mA. This can be checked and tested by the method described above.
    In another optional embodiment, the test interface (102) is adapted to verify the output signal in the various output stages (104).
    Another preferred system feature relates to the application of a multiplexer (24) to the test parameter input filter (12) in the test interface (102). The test interface can thus be reused for, for example, time-division multiplex analysis of several entries, thus reducing the need for resources.
    FIG. 3 illustrates the behavior of a possible implementation of the test algorithm that is executed in the test control block (105). The test algorithm can be considered as distributed logic across the test control block (105) (i.e., the test analyzer (18), test generator (19), test arranger (21) and generic test control (20)). Based on the check applied to the test generator (19), the test arranger plans a number of test segments. The test segments are a set of test conditions that affect one or more input channels. The test conditions are based on the physical characteristics of the input signal and / or of the input circuits. The main objective of the test algorithm is to determine a test pattern that aims to achieve maximum test coverage of the input path, as well as to prevent intrusion to the input signal. This is achieved by defining a number of test parameters and related test patterns to verify certain physical aspects of the input signal and the input circuit without affecting functional behavior.
    These parameters are configured by the algorithm in the test generator (19), which applies the effective test pattern to the input signal and the test analyzer (18), which detects the effects of the test signal on the input circuits. Because of the knowledge of the test rigorhythm about the output stage (104), the test rigorithm may decide to apply certain filter characteristics or gain settings to the output stage in function of the applied test parameters to compensate for the applied test conditions. Moreover, the algorithm may even decide to change the output signal of the output stage in a way that it implements safe behavior depending on the test result.
    The following examples describe some preferred possible implementations of a portion of the input circuit (101) and provide an illustration of the generic approach previously presented. Reference is made to FIG. 4..
    In the embodiment shown in FIG. 4, the parallel parallel sum amplification method, the intrusion of the test signal is effected by modifying the insertion path of a sum amplification. In a "normal" operational condition (Fig. 4A), the input circuit is formed by applying an analog input signal to a standard inverting amplifier that is formed by connecting two sum amplifier branches via double rated resistors (R1, R2) from the normal amplification series. The input gain resistance is formed by the constellation of the parallel resistors. The second resistor (R2) is in the path because of the default position of the two-pole switch (3). Since the input switching system is also there without a test circuit or signal present, it can be verified whether or not the input works correctly / naturally by analyzing the data from the standard input. During the 'test' operation (Fig. 4B) the switch is changed so that in this case a test signal generated by the test signal generation block (103) and the control logic in test control block (105) is applied to the sum amplifier. The standard path is not disturbed and verification of the test signal is possible. At the time of testing, the analog input signal and the test signal are separated from each other by suitable filters. Also, the test check block (105) on the functional input signal at the level of the output stage (104) activates a double gain that compensates for the change in input gain. Even if one is unable to switch back to the normal state of affairs (which is detectable since the test signal is still coming through), the signal can still be evaluated correctly.
    Another possible approach is illustrated in FIG. 5, where an intrusion of a galvanic test signal is used. More in detail, a galvanic coupling (inductive, optical, ...) is made between a test signal and the analog input itself. By applying a test signal to the component establishing the galvanic coupling, a signal is imposed on the standard test interface. In contrast to the parallel sum gain of FIG. 4, no modifications are made to the input circuit. Thus, no interruption is made to the standard path or to the amplification of the "normal" operation signal. At the time of testing, the analog input signal and the test signal are separated from each other by suitable filters.
    Both in the case of galvanic or direct test signal intrusion and in parallel sum gain, the test signal can be applied continuously by providing an intelligent test signal generator and input signal analyzer. The signal generator then outputs a test signal to the coupling device based on the actual measured input circuit. It produces a test signal from the usable frequency range of the analog input signal. The test signal level can also be adjusted. This mechanism allows the verification of the entire analog input path with regard to signal continuity and signal level. This latter feature even allows continuous evaluation of the operational range of the analog circuit and / or of the digital interface of, for example, the digitizer.
    By making the test signal generator intelligent so that the actual analog input signal is used to determine the characteristics regarding, among other things, frequency and level of the test signal, input path verification can take place continuously. FIG. 6 provides an illustration about inserting test signal outside the input signal frequency band with modulated signal level. By providing a test signal as an example outside the band of the input signal, it is possible to validate the correct operation of an analog-to-digital conversion device or to verify whether or not the signal passes through input circuits is filtered out. FIG. 6 shows how the test signal is produced outside the band of the input signal. This can be from higher frequencies or from lower frequencies.
    The above examples are to be seen as such and therefore not as limiting of the invention. To illustrate this, in a subsequent embodiment, a combination of the examples shown above, as shown in FIG. 7, possible. In FIG. 7, both a galvanic test signal insert and the parallel sum gain are applied.
    A typical operational exemplary situation is described based on the situation provided in FIG. 8. It relates to a rotating machine with a linear distance encoder with analogue current output. The linear encoder records the rotary motion of a take-up machine that operates between two diameters defined by P1 and P2. During the winding process, the crankshaft connected to the linear encoder moves from P1 to P2. The take-up rotation speed is variable between 10 Hz and 20 Hz. It is now described how to determine the natural behavior of the sensor signal. This signal is supposed to have (only the operational behavior of the machine) a frequency between 10 Hz and 20 Hz.ë and the measured level should be between 5 mA and 15 mA. If these conditions are not met, there is a machine problem (crankshaft, sensor mounting, winding machine). In the case that the sensor signal is lower than 4 mA or higher than 20 mA, there is clearly a sensor problem. However, there could also be a problem with either the sensor, the input circuit, or their interconnection. In order to verify this, the test control unit can apply a frequency sweep of certain levels (the test algorithm can verify this by dynamically using the information already present in the natural signal in order not to disturb the natural behavior of the sensor signal) and to insert the sensor signal by changing the test switch. At this time, the output gain is also adjusted to compensate for the input change.
    In order to verify that the system indeed provides the correct output, the output itself is also checked.
    In the event that the test algorithm detects an error, an error is reported and the output signal is set to the safe alarm condition. These can, for example, all be zeros.
    By changing the sweep level and frequency, the test algorithm is able to test the gain of the input circuit, the bandwidth of the input filter, and the proper functioning of the ADC.
    All of these tests are planned by the test arranger, who performs the test segments in parallel or sequentially based on interdependent parameters of the test segments and test circuits.
    The proposed solution offers a wide variety of benefits. One signal generator is required for testing multiple inputs. This clearly forms an optimization in terms of volume, costs and reliability. The test signal can be used for multiple inputs with similar characteristics. An important advantage is - as already mentioned - that inputs which could be influenced by said test signal can be disconnected from the test signal. Furthermore, multiple parameters of the input circuit can be verified. The proposed approach also allows verification of the state of the output signal. The input signal connectivity remains guaranteed at all times.
    Another important feature of the proposed system is its ability to enable measurement and verification of the online input circuit. A status indication can be obtained. The system is scalable and can be multiplexed over time. The output signal can be modulated to a safe state. Specific behavior of the input and output signals can be verified.
    Further advantages offered by the invention can be summarized as follows. The connectivity of the input signal can be guaranteed at all times. It makes it possible to apply the test signal to several inputs with similar characteristics. Inputs that can be influenced by the test signal can be disconnected from the test signal. At any time you can detect whether the test signal is still connected to the input.
    In addition to dealing with the test input connectivity, the present disclosure also presents a method for modifying the input switching system for specific test signal verification, a solution for specific test parameter verification, for the test pattern production and for overall test para mete rif icification.
    Through the invention, a test signal can be inserted into an interface circuit by a galvanic method or by a method based on a sum amplifier. It also provides a way to generate a specific test signal to enable online measurement, and a method to use the data from the available switching system to analyze the test data and extract the signal of interest.
    权利要求:
    Claims (7)
    [1]
    The testing system of claim 1, wherein said input circuit (101) is a galvanically isolated coupling.
    [2]
    The testing system of any of claims 1 to 3, further comprising an output stage (104).
    [3]
    The testing system of claim 4, wherein said output stage is adapted to compensate for said test parameters.
    [4]
    The testing system according to claim 4 or 5, wherein said test control unit (105) is adapted to perform a safe state indication to said output stage. The testing system according to any of the preceding claims, further comprising multiplexing means (24) for multiplexing a plurality of signals output through a plurality of input circuits (101).
    [5]
    The testing system of claim 7, wherein said test interface (102) is adapted to be fed with signals in a time division multiplexing style. The testing system of claim 8, wherein said signals fed to said test interface (102) come from said output stage or from said input circuits.
    [6]
    The testing system according to any of the preceding claims, wherein said control block (105) comprises a test arranger (21) for determining the order of parameters to be used. The testing system according to any of the preceding claims, wherein said control block (105) is adapted to perform an algorithm for determining said test parameters for said test signal.
    [7]
    A method for testing an input signal (100), comprising the steps of - applying an input signal (100), - generating a test signal (25) based on test parameters obtained from analysis of said input signal, - superposing catching said test signal (25) on said input signal (100), - performing an analysis on said superposition of said test signal and said input signal, - defining updated test parameters for performing said tests from said analysis of said superposition and making modifications for deriving said test signal from said updated test parameters, - producing an updated test signal reflecting said modifications for continuing testing.
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    同族专利:
    公开号 | 公开日
    WO2013092082A1|2013-06-27|
    EP2795352B1|2015-11-18|
    GB201122294D0|2012-02-01|
    EP2795352A1|2014-10-29|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US4724380A|1984-12-21|1988-02-09|Plessey Overseas Limited|Integrated circuit having a built-in self test design|
    EP0572204A1|1992-05-27|1993-12-01|Kaye Instruments, Inc.|Method and apparatus for automated sensor diagnosis|
    US20070219739A1|2006-03-15|2007-09-20|Spears Brian K|Mixer measurement system and method using a chaotic signal|
    US20090284263A1|2008-05-13|2009-11-19|Kirkelund Morten|Full function test for in situ test of sensors and amplifiers|
    TWI696914B|2019-05-17|2020-06-21|和碩聯合科技股份有限公司|Electronic device, signal verification device, and method for verifying signals|
    法律状态:
    2018-11-29| MM| Lapsed because of non-payment of the annual fee|Effective date: 20180228 |
    优先权:
    申请号 | 申请日 | 专利标题
    GB201122294|2011-12-23|
    GB201122294A|GB201122294D0|2011-12-23|2011-12-23|Signal test circuit and method|PCT/EP2012/073198| WO2013092082A1|2011-12-23|2012-11-21|Signal test circuit and method|
    EP12790545.3A| EP2795352B1|2011-12-23|2012-11-21|Signal test circuit and method|
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