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    • 专利摘要:
    A multiphase synchronous converter, consisting of a plurality of half bridges, in turn consisting of one upper circuit breaker and one lower circuit breaker, is controlled by a pulse width modulation depending on a predetermined duty cycle in the range of zero to one hundred percent. The multiphase synchronous converter generates an output current and is operated in a normal mode in which the circuit breakers switch with a normal switching period defined by a predetermined normal switching frequency and a normal plus duration dependent on the current duty cycle. As soon as the duty cycle exceeds an upper duty cycle threshold or falls below a lower duty cycle threshold, the multiphase synchronous converter is switched from the normal mode to an operating mode in which at least one of the power switches of at least one half-bridge is permanently deactivated over a period which is greater than the normal switching period.
    公开号:AT517686A4
    申请号:T50829/2015
    申请日:2015-10-01
    公开日:2017-04-15
    发明作者:
    申请人:Avl List Gmbh；
    IPC主号:
    专利说明:

    Method for driving a multiphase synchronous converter
    The subject invention deals with a method for driving a multiphase synchronous converter, consisting of a plurality of half bridges in turn each consisting of an upper circuit breaker and a lower power switch, by a pulse width modulation depending on a predetermined duty cycle in the range of zero to one hundred percent, wherein the synchronous converter is an output current is generated and the Mul-tiphasige synchronous converter is operated in a normal mode in which the circuit breaker with a defined by a predetermined normal switching frequency normal switching period and a current duty cycle dependent normal plus duration switch.
    In order to transform DC voltages into other DC voltage ranges, various DC-DC converters, sometimes also called DC-DC transformers, are known. For certain applications, such as battery chargers or battery testers, powerful DC converters are required, which can also be operated bidirectionally. One possible implementation of a bidirectional DC-DC converter is a synchronous converter, which is a buck converter, i. which input voltages convert into output voltages smaller or at most equal to the input voltages, or vice versa. For this purpose, a half-bridge is used, wherein the two power switches of the half-bridge are controlled by a controller with pulse width modulation (PWM control) such that they are driven within a switching period, which is determined by the predetermined switching frequency, alternately driven with inverted switching pulses. Thus, basically a circuit breaker of a half bridge is conductive, the other blocks. The level of the output voltage of the synchronous converter is set by the specification of the duty cycle of the PWM control. The duty cycle denotes the ratio of the pulse duration of the upper power switch of a half-bridge to the switching period. These synchronous converters can also be designed as multiphase converters. In this embodiment, as is known, a plurality of half bridges, each with two circuit breakers, are connected in parallel via the output chokes of the half bridges and are controlled in series by the PWM control. Thus, the circuit breakers are usually clocked offset by a fraction of the switching period, primarily to reduce Ausgangsstromrippei. The output current is determined in multiphase synchronous converters with a fixed sampling rate. In order to ensure that the sampling points each fall on the average currents, the timing of the power switches take place offset by the switching period duration divided by the number of half bridges. With the multiphase control, larger output currents can be generated with a smaller current ripple, or the switching frequency of the sum output current of such a multiphase converter can be reduced, which enables simpler filter sizing. Last but not least, smaller capacitors can be used in a multiphase converter for the same power range.
    As is known, however, the upper and lower power switches of a half-bridge may not be switched on simultaneously, since otherwise the voltage input of the synchronous converter is short-circuited. For this reason, it is not possible to switch the two circuit breakers of a half-bridge simultaneously or directly behind one another, since otherwise it would be risked that, for example, due to switching delays in the nanosecond / microsecond range, both switches will be turned on for a short time and thus the input shorted. Remedy is the insertion of dead times between the switching of the upper and lower circuit breaker of a half-bridge. This will ensure that one switch is off before the other switch is turned on. By inserting dead times, however, a reduction of the achievable duty cycle always occurs because the achievable minimum and maximum duty cycle and thus the minimum and maximum output voltage are limited. Thus, the covered voltage range of the synchronous converter is reduced when driven with inverting PWM signals and it is not possible to output very small or very high voltages. The driving of the half-bridge with inverting PWM signals basically has the meaning that the current can continuously change between positive and negative values within a pulse period. Since both circuit breakers always alternate in normal operation, a high or low output voltage can not be accurately set because the voltage is affected by the required pulses of the other circuit breaker and the dead time generated thereby. Thus, no theoretically maximum or minimum possible voltage can be output on the output side, without obtaining a certain error. Although PWM controllers are known that at least allow a duty cycle of 100 percent, but there is a gap at values just below 100 percent.
    It is thus an object of the present invention to expand the achievable voltage range of a DC-DC converter.
    This goal is achieved by switching the switch from normal mode to an operating mode when at least one of the circuit breakers of at least one half-bridge is permanent for a period of time greater than the normal switching period when the duty cycle exceeds a first upper duty cycle threshold or below a first lower duty cycle threshold is deactivated. This eliminates the otherwise required dead time, which would lead to a reduction of the duty cycle and thus the voltage range.
    If the output current is greater than a first positive output current threshold or smaller than a first negative output current threshold, the synchronous converter can additionally be switched to a blocking mode by all lower circuit breakers or all upper circuit breakers, ie the respective circuit breaker, the normal operation still short pulses per period contribute and thus additionally cause a dead time to be permanently disabled. "Disable" means that the respective circuit breaker is permanently open and no drive pulses are applied to it. As a result, only the pulse width of the opposing circuit breaker of the half-bridge determines the output voltage, and no dead time must be taken into account between switching the circuit breaker of a half-bridge. Since the normal switching period does not change in the blocking mode, the sampling period of the output current can be maintained.
    In extreme cases, thus, for example, with positive output current, the upper circuit breaker (driven offset in multi-phase synchronous converters) permanently switch, whereas all lower circuit breaker are permanently disabled during the lock mode and a duty cycle of one hundred percent is achieved. In extreme contrast, all upper circuit breakers can be permanently disabled, whereas all lower circuit breakers switch permanently (again offset in multiphase synchronous converters), giving a duty cycle of zero percent. If the output current is negative, the roles of the upper and lower circuit breakers are reversed. If at low output currents all upper or all lower circuit breakers are blocked, then a zero crossing of the output current is not possible. If, for example, a positive output current flows, only the upper circuit breakers are switched in blocking mode. However, if the lower power switches are disabled, there can be no current change from positive to negative because the energy in the inductor is zero at the zero output current and the current reversal to negative output currents only pass when the lower power switch turns on and the output voltage through the current lower circuit breaker would drift in the negative direction. The input voltage is greater than the output voltage in a synchronous converter. For example, output current gaps will occur at around zero amps and, for example, oscillations may occur between the positive current blocking mode (disabling all bottom circuit breakers) and the negative current blocking mode (disabling all top circuit breakers). With low or no high duty cycles, the normal mode must be used instead of the lock mode to produce a zero crossing of the output current. At low or high duty cycles, the normal mode again gives the above-mentioned dead time problem and the desired duty cycles and thus output voltages can not be achieved.
    The remedy here is a low-current mode which is activated when a specified second positive output current threshold is undershot and at the same time a second negative output current threshold is exceeded, ie if the output current is in a range around the zero crossing. In this low current mode, the power switches are alternately switched with a switching period increased by a factor z by the sampling period.
    This reduces the influence of the dead times by the same factor z, since Z times seldom switched. Exceeding the upper or lower first duty threshold is assumed, otherwise the normal mode would be sufficient.
    In addition, the pulse durations of at least the upper or the lower power switches of a half bridge can be increased by the factor m by the pulse duration. The pulse duration increased by the factor m makes it possible to take into account the required dead time in the case of inverting switching of the half-bridge. It is achieved that the pulse widths for the very small output voltages become greater than the dead time, and thus can be output. Overall, this results in a higher accumulated total pulse duration over the individual pulses, which occur z times less often, but m times wider.
    Advantageously, it is provided in the low-current mode, for example, by increasing the switching period, that within a sampling period only a half-bridge switches, the multi-phase synchronous converter is operated as a single-phase synchronous converter, with each sampling period, the switching half-bridge changes. The current ripple is already low at low output currents, so that the omission of a nested switching of the half bridges with increased switching period brings no disadvantages for the filtering of the Ausgangsstromrippeis with it. Thus, one half-bridge can be switched alternately per sampling period.
    Advantageously, the factor z corresponds to the factor m, whereby on the one hand the same duty cycle as in normal mode can be achieved, but with z = m less occurring dead times. In addition, it is ensured that the sampling period of the output current always hits the mean value of the currently active circuit breaker and to adjust the desired duty cycle.
    In order to avoid oscillations between low current mode and the blocking mode, it is possible to generate hystereses between first positive and second positive output current thresholds and between first negative and second negative output current thresholds, respectively.
    When the synchronous converter is in lock-up mode, it may remain in lock-up mode if the output current remains greater than a second positive output current threshold or less than a second negative output current threshold, depending on the polarity of the output current.
    When the synchronous converter is in low current mode, the synchronous converter may remain in low current mode if the output current remains less than the first positive output current threshold and greater than the first negative output current threshold remains.
    If no hysteresis is desired, first and second negative output current thresholds, respectively first and second positive output current thresholds can be equated respectively.
    To avoid oscillations between normal mode and lock mode, or low current mode, another hysteresis may be generated by setting at least one more duty cycle threshold closer to a 50% duty cycle than the upper and lower duty cycle thresholds. Exceeding the second duty cycle threshold causes in each case a switch to normal operation. This effectively gives a hysteresis between the at least one further duty cycle threshold and the upper duty cycle threshold and the lower duty cycle threshold, respectively.
    The subject invention will be explained in more detail below with reference to Figures 1 to 5, which show by way of example, schematically and not by way of limitation advantageous embodiments of the invention. It shows
    1 shows the circuit structure of a four-phase synchronous converter,
    2 shows a circuit diagram of a polyphase synchronous converter in normal mode M0
    3 shows a circuit diagram of a multiphase synchronous converter in the low-current mode M3
    4 shows a representation of the possible operating modes M0, M-ι, M2, and M3
    Fig.5 shows circuit diagrams of the transition from normal mode and operating modes M0, M-i, M3, M2 and an associated output current characteristic with zero crossing.
    In Fig. 1, a known multi-phase, here a four-phase, synchronous converter 1 is shown according to the prior art. As is known, synchronous converters are bi-directional, but the left-hand side is referred to, for example, as input side with the input voltage Ui at the input capacitance Ci and the right-hand side as output side with the output voltage U2 at the output capacitance C2. Likewise, as is known, inductances X2, X3, X4 (throttling) are provided at the individual phases, the inductances Xi, X2, X3, X4 on the one hand between the upper and lower power switches, each having a half bridge HB1, HB2, HB3, HB4 are connected and on the other hand connected to each other. The inductors X 1, X 2, X 3, X 4 together with the output capacitance C 2 form an output filter of the synchronous converter 1.
    The half-bridges HB-i, HB2, HB3, HB4 each consist of an upper power switch Lo1, Lo2, Lo3, Lo4 and in each case a lower power switch Lu1, Lu2, Lu3, Lu4 and optionally associated diodes Do1, Du1, Do2, Du2, Do3, Du3, Do4, Du4. A PWM control 2 (indicated in FIG. 1 only for the power switch Lu1) controls the half-bridges HB-i, HB2, HB3, HB4, or the power switches Lo1, Lo2, Lo3, Lo4, Lu1, Lu2, Lu3, Lu4 of FIG Half bridges HB ^ HB2, HB3, HB4, in the normal mode M0 such that within a defined by a predetermined normal switching frequency normal switching period T0, the half-bridges HB-i, HB2, HB3, HB4 with the normal switching period T0, but by the normal switching period T0 / by the number the half-bridges x offset, clocked. Thus, the upper circuit breaker Lo1, Lo2, Lo3, Lo4 are switched off and switched while the respective associated lower circuit breaker Lu1, Lu2, Lu3, Lu4 of the respective half-bridge HB ^ HB2, HB3, HB4 locked. After a pulse duration t0 of the upper power switches Lo1, Lo2, Lo3, Lo4, the previously turned on upper power switches Lo1, Lo2, Lo3, Lo4 are turned off and the previously disabled switched lower power switches Lu1, Lu2, Lu3, Lu4 are turned on. After a pulse duration tu of the lower circuit breaker Lu1, Lu2, Lu3, Lu4 these are disabled again and the upper circuit breaker Lo1, Lo2, Lo3, Lo4 connected. Of course, the roles of the upper and lower power switches Lo1, Lu1, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4 of the half-bridges HB-i, HB2, HB3, HB4 can also be reversed, for example when the output current direction is changed.
    In order to prevent the upper power switches Lo1, Lo2, Lo3, Lo4 and lower power switches Lu1, Lu2, Lu3, Lu4 of the half bridges HB ^ HB2, HB3, HB4 being simultaneously turned on and thereby short-circuiting the voltage input, after each normal plus duration t0, tu a dead time Tt between the on / off of the upper power switch Lo1, Lo2, Lo3, Lo4 and the off / on of the associated lower power switch Lu1, Lu2, LU3, Lu4 the half-bridge HB1, HB2, HB3, HB4 realized and vice versa. This results in a comprehensible relationship: the sum of the pulse durations t0 of the upper power switches Lo1, Lo2, Lo3, Lo4 and the pulse durations tu of the lower power switches Lu1, Lu2, Lu3, Lu4 plus twice the dead time Tt gives the normal switching period T0. The duty cycle S describes the ratio between the pulse duration t0 of the upper power switches Lu, L21, L31, L41 to the normal switching period T0. The ratio of the pulse durations t0, the upper power switches Lo1, Ι_ο2, l_o3, Lo4 and the pulse durations tu of the lower power switches Lu1, Lu2, Lu3, Lu4 is thus determined by the PWM control 2 via the duty cycle S and the normal load period T0.
    From, for example, duty cycles of 25% arise at n = 4 existing half bridges HBi, HB2, HB3, HB4 overlaps of the pulse durations t0, tu of the upper power switch Lo1,
    Lo2, Lo3, Lo4 and the lower circuit breaker Lu1, Lu2, Lu3, Lu4, depending on the current direction.
    The setting of the output voltage U2 occurs in the case of synchronous converters via the duty cycle S. A duty cycle S of one hundred percent would therefore mean (with positive output current Ia) that the upper power switches Lo1, Lo2, Lo3, Lo4 are permanently switched and the lower power switches Lu1, Lu2, Lu3, Lu4 of all half bridges HB ^ HB2, HB3, HB4 is permanently blocked. This would cause a switching of the input voltage Ui to the output voltage U2. In turn, a duty cycle S of zero percent would mean that all lower power switches Lu1, Lu2, Lu3, Lu4 are permanently switched and the upper power switches Lo1, Lo2, Lo3, Lo4 of all half bridges HB ^ HB2, HB3, HB4 are permanently blocked are disabled. This causes an output voltage U2 of zero. Since within a normal switching period T0 due to the offset circuit of the upper power switch L0i, Lo2, Lo3, Lo4 and the necessary pulses of the associated lower power switch Lu1, Lu2, Lu3, Lu4 and the twice required dead time Tt now the duty cycle S is not arbitrarily reduced or increased Usually, these extreme duty cycles S are not achievable. In normal mode M0, the possible range of the output voltage U2 is therefore limited.
    In Fig. 2, the circuit diagram of the circuit breaker Lo1, Lu1, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4 is shown, wherein each of the four half-bridges HBi, HB2, HB3, HB4 offset with the normal switching period T0 by the number x of the half-bridges be clocked, so here with T0 / 4. The sampling period Ts of the output current Ia is set so that at the time of sampling, a current branch leads the current average current, which is ensured according to the relation Ts = T0 * i / (2 * x). In this case, x represents the number of half bridges HBi HB2, HB3, HB4 and i a natural number of 1 to 2x. The sampled output current value requires the PWM control 2 for driving the synchronous converter 1. A relatively small duty cycle S is shown, i. the pulse durations t0 of the upper power switches Lo1, Lo2, Lo3, Lo4 are significantly lower than the pulse durations tu of the lower power switches Lu1, Lu2, Lu3, Lu4. The dead time Tt can be seen in each case between the individual pulses. The minimum pulse duration t0 of the upper power switches Lo1, Lo2, Lo3, Lo4 in a normal switching period T0 is thus limited by the minimum required pulse duration t0 of the upper power switches Lo1, Lo2, Lo3, Lo4 and in two ways by the length of the dead time Tt. The minimum pulse durations t0, tu of all the circuit breakers Lo1, Lu1, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4 are approximately on the order of the dead time Tt. Thus, the linear range of the duty cycle S and thus the minimum output voltage is limited in approximately three ways by the dead time Tt. At a high duty cycle S or at a negative output current la, the same problem arises with reversed roles of the upper power switches Lo1, Lo2, Lo3, Lo4 and the lower power switches Lu1, Lu2, Lu3, Lu4.
    In order to extend the range of the output voltage U2, ie the duty cycle to the otherwise unachievable values just below 100% or just above 0%, according to the invention, as soon as the duty cycle S exceeds an upper duty cycle threshold S0i or below a lower duty cycle threshold SU1, of the normal mode M0 in an operating mode M-ι, M2, M3, in which at least one of the circuit breaker Lo1, Lu1, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4 at least one half-bridge HB ^ HB2, HB3, HB4 over a period greater than the normal switching period T0 is permanently deactivated. "Deactivated" means that the circuit breaker does not deliver pulses, ie is open, and that the switching time of the opposite circuit breaker is not reduced by any dead time. Thus, compared to the normal mode M0 within a period corresponding to the normal switching period T0, the dead time Tt, which would limit the voltage range, is saved approximately at least three times.
    In order to describe the mode of operation of the exemplary operating modes M-1, M2, M3, blocking modes M-1, M2, and a low-current mode M3 are to be distinguished as operating modes (FIG.
    If the output current la is greater than a first positive output current threshold li + or less than a first negative output current threshold h. 4), the synchronous converter 1 can be switched to a blocking mode Mi, M2 by having all the lower circuit breakers Lu1, Lu2, Lu3, Lu4 (at la> li +) or all the upper circuit breakers Lo1, Lo2, Lo3, Lo4 (at la <I-1) are permanently deactivated as long as the multiphase synchronous converter 1 is in lock-up mode Mi, M2. For this purpose, as mentioned above, the output voltage U2 desired by the synchronous converter 1 must require a duty factor greater than the first upper duty cycle threshold Sol or less than the first lower duty factor threshold Sui
    Thus, if the upper or lower Tastgradschwelle S0i, Sui has been exceeded and the output current la, for example, exceeds the first positive output current threshold L +, all lower circuit breaker Lu1, Lu2, Lu3, Lu4 all half bridges HB ^ HB2, HB3, HB4 permanently disabled, which to lock mode Mi leads. The upper power switches Lo1, Lo2, Lo3, Lo4 continue to shift by the normal switching period T0 by the number of half-bridges HB-i, HB2, HB3, HB4 with a pulse duration t0 depending on the desired duty cycle S. However, there is the advantage that now higher and lower pulse durations t0 and thus higher and lower duty cycles S than in the normal mode M0. Since the lower power switches Lu1, l_u2, Lu3, Lu4 do not switch in lock mode Mi, no dead times Tt are required and the pulse durations t0 are not restricted.
    If the upper duty cycle threshold S0i has been exceeded, a high output voltage U2 is desired. This output voltage U2 can be arbitrarily set with a positive output current Ia by varying the pulse durations t0 of the upper power switches Lo1, Lo2, Lo3, Lo4. It is thus also a duty S in a range just below and up to one hundred percent possible, which would mean that the upper circuit breakers Lo1, Lo2, Lo3, Lo4 almost permanent (in the case of a multiphase synchronous converter 1 again offset) or permanently switched , In any case, the limitation by twice the dead time Tt and the minimum pulse duration tu (which usually corresponds approximately to a dead time Tt) of the lower power switch Lu1, Lu2, Lu3, Lu4 is no longer given. Thus, a higher output voltage U2, can be achieved. For small duty cycles S, an analogous situation applies. If the lower duty cycle threshold Sui has been undershot, all the lower power switches Lu1, Lu2, Lu3, Lu4 of all half-bridges HB1, HB3, HB4 are permanently deactivated as well. This eliminates equally dead times Tt and the pulse durations t0 of the upper power switches L0i, Lo2, Lo3, Lo4 can be chosen arbitrarily small (up to a pulse duration t0 in the order of the dead time Tt and even up to a pulse duration t0 of zero). Thus small duty cycles S are possible without both dead times Tt or disturbing pulses of the lower power switches Lu1, Lu2, Lu3, Lu4 contribute.
    However, if the output current la is the first negative output current threshold ^. falls below, all upper circuit breaker Lo1, Lo2, Lo3, Lo4 all half-bridges HB1; HB2, HB3, HB4 permanently disabled, resulting in the blocking mode M2. In this blocking mode M2, the lower power switches Lu1, Lu2, Lu3, Lu4 continue to shift and with pulse durations tu depending on the desired duty cycle S. Thus, even with negative output current la high and low duty cycles S can be made possible, since now the lower upper power switch L0i, Lo2, Lo3, Lo4 do not switch, and no dead times Tt flow. Compared to the aforementioned blocking mode M-1, ie with positive output current Ia, the roles of the upper power switches Lo1, Lo2, Lo3, Lo4 and lower power switches Lu1, Lu2, Lu3, Lu4 are reversed in the blocking mode M2 with negative output current la. For small output currents Ia, i. if the output current Ia is smaller than the second positive output current threshold I2 + and greater than the second negative output current threshold I2. is, that is, when the output current la is in a range around the current zero crossing, the synchronous converter 1 can be switched to a low-current mode M3 as an operating mode. Here, the circuit breakers Lu, L12, L21, L22, L31, L32, L41, L42 with a switching period T3 corresponding to the increased by a factor of z normal switching period T0, switched. This means that the half-bridges HB-i, HB2, HB3, HB4 are not clocked with the normal switching period T0, as in the normal mode M0. In other words, within a period corresponding to the normal switching period T0, not all the half bridges HBi, HB2, HB3, HB4 undergo a switching phase, i. not all upper circuit breakers Lo1, Lo2, Lo3, Lo4 and lower circuit breakers Lu1, Lu2, Lu3, Lu4 change state by being switched from conducting to blocked and vice versa. It follows from a factor z of at least two that within a period corresponding to the normal switching period T0 at least one of the power switches Lu, L12, L21, L22, L31, L32, L41, L42 is deactivated, although it would switch M0 in the normal mode.
    Advantageously, the factor z can be selected such that it satisfies the relation z = x / i, where i represents a value from 1 to x-1, and x represents the number of half-bridges.
    Furthermore, only one half-bridge HB-i, HB2, HB3, HB4 can be switched per sampling period Ts, which can be achieved, for example, by a suitable choice of the factor z and thus of the switching period T3.
    To sketch the facts, reference is made to FIG. The switching period T3 in this example corresponds to the z = 4-times sampling period Ts (with x = 4, i = 1). Thus, for example, at a sampling period Ts of% Τ0, this causes a switching period T3 of 3T0 and means that only one third of the dead times Tt occur within the same time period. In the low current mode M3, only eight dead times Tt are to be counted within the switching period T3 = 3 * T0. For comparison, it is to be considered 3 times as many, ie 24 dead times Tt in the normal mode M0 within the same period. Within a normal switching period T0, in the low-current mode M3, at least one of the power switches Lo1, Lu1, Lo2, Lu2,
    Lo3, Lu3, Lo4, Lu4 disabled, which would be active in normal mode M0. In the first normal switching period T0, this applies here to the circuit breakers Lo1, Lo2, Lo3, in the second normal switching period T0 the circuit breakers Lo1, Lo3, Lo4, etc.
    Advantageously, in the low-current mode M3, the pulse durations t0, tu of the circuit breakers Lo1, Lu1, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4 can simultaneously be increased by a factor m. The pulse durations t0, tu increased by the factor m also make it possible, for example, to output smaller output voltages U2 for very small duty cycles S, since the relation of pulse durations t0, tu to the dead time Tt improves by the factor m. Overall, there is a higher accumulated total pulse duration over the individual pulse durations t0, tu, which occur z times less often, but are m times wider.
    The factor m can be chosen equal to the factor z, which results in the same duty cycle S (ie the same sum of all pulse durations within a normal switching period T0) as in the normal mode M0, thus ensuring that the samples of the output current la occur at a time which is a phase in the average current value. Likewise, this also results in that the sampling of the output current Ia in the low-current mode M3 does not have to be changed.
    In order to avoid oscillations between the blocking modes M2 and the low current mode M3, a hysteresis H | + between the first positive output current threshold 1-1 + and the second positive output current threshold l2 + and a hysteresis H | _ between the first negative output current threshold U and the second negative output current threshold L2. will be realized. It must be provided that the first positive output current threshold l1 + greater than the second positive output current threshold l2 +, and the first negative output current threshold U. smaller than the second negative output current threshold L2. is.
    If, with the blocking mode M-1, M2 active (i.e., the first positive output current threshold l1 + is exceeded or has fallen below the first negative output current threshold), the output current la is greater than a second positive output current threshold l2 + or less than a second negative output current threshold l2. remains, the synchronous converter 1 can therefore according to the associated hysteresis Ημ, Ημ. remain in the respective blocking mode M-1, M2.
    If the output current Ia intersects with the active blocking mode M-1, M2 thus the second positive output current threshold I2 + or the second negative output current threshold I2_, the output current Ia approaches zero in absolute value, then the low-current mode M3 is activated.
    If, with active low-current mode M3 (ie, the output current has exceeded the second negative output current threshold I2, or the second positive output current threshold I2 + falls below), the output current Ia is smaller than the first positive output current threshold In and greater than the first negative output current threshold, then the synchronous converter So stay in the low current mode M3.
    If the output current Ia crosses the first positive output current threshold In or the first negative output current threshold in the case of active low-current mode M3, the low-current mode is deactivated and the blocking mode M1 or M3 is activated depending on the current direction.
    Corresponds to the first positive output current threshold l1 + the second positive output current threshold and / or the first negative output current threshold ^. the second negative output current threshold l2_, it is dispensed with a hysteresis H | +, or H | _.
    In order to prevent oscillations between the normal mode M0 and the operating modes M-1, M2, M3, at least one further hysteresis HSo, HSu can be realized. For this purpose, at least one further duty cycle threshold S02, SU2 is provided which is closer to a duty cycle of S = 50% than the upper duty cycle threshold S0i and the lower duty cycle threshold Sui. After crossing the further duty cycle threshold S02, SU2, the synchronous converter is switched to the normal mode M0 in each case.
    The possible operating states and realizable hysteresis Ηι +, Η,., HSo, HSu, and possible output current thresholds U., I2-, li +, l2 + and Tastgradschwellen S0i, S02, Sui, SU2 are plotted in Figure 4 on output current la and duty cycle S.
    5 shows a profile of the output current Ia through the zero crossing and thus the transition from the normal mode M0 first to the blocking mode M-1, then to the low-current mode M3 and further to the blocking mode M2. In the normal mode M0, all of the power switches Lo1, Lu1, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4 are switched according to a prior art PWM controller 2. Since, as a result, the duty cycle S decreases and the output current la is positive and sufficiently high, the blocking mode M-1 is activated by deactivating the lower power switches Lu1, Lu2, Lu3, Lu4. When the output current Ia approaches the zero crossing, the low-current mode M3 is activated when the duty cycle S remains low. In this mode, all the circuit breakers Lo1, Lu1, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4 switch again. However, as can be clearly seen, the switching period T3 has been increased to a z-fold (here four times) the sampling period Ts. Likewise, the pulse durations t0, tu were increased to m times. It should be noted that the sampling points (bottom graph) of the synchronous converter 1 remain unchanged, i. the sampling rate Ts does not change even in the low current mode M3. The sum of the pulse durations t0, tu in the low-current mode M3 still correspond to the sum of the pulse durations t0, tu in the normal mode M0, assuming the sampling rate Ts remains constant, whereupon the duty cycle S can be determined. After the (negative) output current la becomes large enough, the low-current mode M0 is switched to the blocking mode M2, since the duty cycle S remains small enough. This means according to the invention that all upper power switches Lo1, Lo2, Lo3, Lo4 are permanently deactivated.
    权利要求:
    Claims (10)
    [1]
    claims
    1. A method for driving a multiphase synchronous converter (1), consisting of a plurality of half-bridges (HB-i, HB2, HB3, HB4), in turn consisting of one upper circuit breaker (Lo1, Lo2, Lo3, Lo4) and one lower circuit breaker ( Lu1, Lu2, Lu3, Lu4.), By a pulse width modulation depending on a predetermined duty cycle (S) in the range of zero to one hundred percent, wherein the synchronous converter (1) an output current (la) is generated and the multiphase synchronous converter (1) in a normal mode (M0) is operated, in which the power switches (L0i, Lui, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4) with a defined by a predetermined normal switching frequency normal switching period (T0) and dependent on the current duty cycle (S) normal plus duration (t0, tu), characterized in that as soon as the duty cycle (S) exceeds an upper duty cycle threshold (S0i) or falls below a lower duty cycle threshold (Sui), the multiphase synchronous converter (1) from the normal mode (M0) in an operating mode (M-ι, M2, M3) is switched, in which at least one of the power switches (Lo1, Lu1, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4) at least one half-bridge (HB-i, HB2 , HB3, HB4) over a period of time which is greater than the normal switching period (T0) is permanently deactivated.
    [2]
    2. The method according to claim 1, characterized in that if the output current (la) is greater than a first positive output current threshold (l1 +) or less than a first negative output current threshold (h.), The polyphase synchronous converter (1) in a blocking mode (M -ι, M2) is switched as the operating mode by permanently deactivating all lower circuit-breakers (L12, L22, L32, L42) or all upper circuit breakers (Lo1, Lo2, Lo3, Lo4) while the multiphase synchronous converter (1) is in lock-up mode (M-1, M2) is located.
    [3]
    3. The method of claim 1 or 2, characterized in that a second positive output current threshold (l2 +) and a second negative output current threshold (l2.) Is present, the output current (la) is sampled with a sampling period (Ts) and that if the output current (la) is less than the second positive output current threshold (I2 +) and greater than the second negative output current threshold (I2), the synchronous converter (1) is switched to a low current mode (M3) as an operating mode by the circuit breakers (Lo1, Lu1, Lo2 , Lu2, Lo3, Lu3, Lo4, Lu4) are switched with a switching period (T3) corresponding to the sampling period (Ts) increased by a factor z.
    [4]
    4. The method according to claim 3, characterized in that at least the upper or the lower power switches (L0i, Lui, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4) with a pulse duration (t0, tu), the by a factor of m increased pulse duration (t0) corresponds, are switched.
    [5]
    5. The method according to claim 3 or 4, characterized in that within the sampling period (Ts) of the output current la, only the power switches (Lo1, Lu1, Lo2, Lu2, Lo3, Lu3, Lo4, Lu4) of a half-bridge (HBi, HB2, HB3 , HB4).
    [6]
    6. The method according to claim 4 or 5, characterized in that the factors z and m are equated.
    [7]
    7. The method according to claim 2, characterized in that if the output current (la) is greater than a second positive output current threshold (l2 +) or less than a second negative output current threshold (l2.), The synchronous converter (1) in the blocking mode (Mi, M2) remains.
    [8]
    8. The method according to any one of claims 3 to 6, characterized in that if the output current (la) is less than the first positive output current threshold (l1 +) and greater than the first negative output current threshold (h.), The synchronous converter (1) in the low-current mode (M3) remains.
    [9]
    9. The method according to claim 7, wherein the first positive output current threshold corresponds to the second positive output current threshold and / or the first negative output current threshold corresponds to the second negative output current threshold.
    [10]
    10. The method according to any one of claims 1 to 9, characterized in that at least one further Tastgradschwelle (S02, SU2) is present, which is closer to 50% than the upper Tastgradschwelle (S0i) and the lower Tastgradschwelle (Sui) and that after crossing the second further Tastgradschwelle (S02, SU2) of the synchronous converter (1) in each case in the normal mode (M0) is switched.
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    ES2895509T3|2022-02-21|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    ATA50829/2015A|AT517686B1|2015-10-01|2015-10-01|Method for driving a multiphase synchronous converter|ATA50829/2015A| AT517686B1|2015-10-01|2015-10-01|Method for driving a multiphase synchronous converter|
    DK16774685.8T| DK3357152T3|2015-10-01|2016-09-30|PROCEDURE FOR ACTIVATING A MULTIPHASE SYNCHRONIC CONVERTER|
    ES16774685T| ES2895509T3|2015-10-01|2016-09-30|Procedure for driving a multiphase synchronous converter|
    US15/764,740| US10523123B2|2015-10-01|2016-09-30|Method for actuating a multi-phase synchronous converter|
    PCT/EP2016/073405| WO2017055534A1|2015-10-01|2016-09-30|Method for actuating a multi-phase synchronous converter|
    EP16774685.8A| EP3357152B1|2015-10-01|2016-09-30|Method for actuating a multi-phase synchronous converter|
    CN201680057443.1A| CN108184334B|2015-10-01|2016-09-30|Method for controlling a multiphase synchronous converter|
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